Downward arch bridge type VDMOSFET device

Abstract

The invention discloses a downward arch bridge type VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor) device. The downward arch bridge type VDMOSFET device is provided with symmetrical step-shaped grooves which are formed by etching a semiconductor layer of the downward arch bridge type VDMOSFET device; the inner wall and two sides of the stepped groove are covered with a layer of first gate dielectric; a second gate medium is also arranged on the first gate medium in the step-shaped groove; the first gate dielectric and the second gate dielectric jointly form a thickened gate dielectric layer of the downward arch bridge type VDMOSFET device; the semiconductor layer is provided with a diversion region and a drift region, and the diversion region extends downwards from the surface of the stepped groove to the drift region. Under the condition that the minimum line width of the device is not reduced, the cell size of the arch bridge type VDMOSFET is reduced, and meanwhile the good dynamic characteristic is obtained by reducing the gate-drain capacitance; and the deeper P well and the thicker gate dielectric layer ensure the reliability of the device.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a downward arch bridge type VDMOSFET device. Background Art

[0002] In the overall positive environment of the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, have become a direct factor affecting the cost and efficiency of power electronic equipment. Although silicon-based power devices are already very mature at this stage, as power semiconductors gradually develop towards high power, high frequency and low power consumption, silicon (Si)-based devices are limited by their own physical characteristics and are beginning to be difficult to apply to some high-voltage, high-temperature, high-efficiency and high-power density application scenarios.

[0003] Silicon carbide (SiC) materials have begun to attract widespread attention from practitioners due to their superior physical properties, and as a result, SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) technology has developed accordingly. Compared with silicon-based devices, the high thermal conductivity and large bandgap of silicon carbide materials determine their application scenarios in high current density, high breakdown field strength, and high operating temperature. Compared with SiMOSFETs of the same level, the characteristic on-resistance and switching loss of SiC MOSFETs make them suitable for higher operating frequencies, and their high thermal conductivity greatly improves their high-temperature stability.

[0004] VDMOSFET (Vertical Double-diffused Metal-Oxide Semiconductor Field-Effect Transistor) is also known as vertical double diffused MOS transistor. Like lateral diffused MOSFET (LDMOSFET), it is a basic structure of power MOSFET and belongs to semiconductor power devices. Compared with LDMOSFET, VDMOSFET occupies a smaller area and has improved corresponding frequency characteristics.

[0005] In the related art, a common VDMOSFET structure is as follows Figure 1 As shown, the electric field of the VDMOSFET will be concentrated in the middle of the device gate oxide layer, and long-term electric field concentration will seriously affect the reliability of the device gate oxide layer. To address this problem, there is also a structure of an arch bridge VDMOSFET in the related art. Figure 2 As shown in Figure 1, this arch bridge VDMOSFET device reduces the gate-drain capacitance by increasing the thickness of the middle part. Figure 1 and Figure 2The gate-drain capacitance of the VDMOSFET shown cannot reduce the width of the gate electrode directly exposed to the drain terminal, resulting in the difficulty in effectively reducing the switching characteristics of the device. Therefore, how to make the VDMOSFET have better reliability and switching characteristics is still a technical problem at present. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a downward arch bridge VDMOSFET device.

[0007] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0008] A downward arch bridge VDMOSFET device, the downward arch bridge VDMOSFET device having a symmetrical stepped groove formed by etching its semiconductor layer; the inner wall and both sides of the stepped groove are covered with a first gate dielectric; wherein a second gate dielectric is further provided on the first gate dielectric in the stepped groove; the first gate dielectric and the second gate dielectric together constitute a thickened gate dielectric layer of the downward arch bridge VDMOSFET device;

[0009] A guide region and a drift region are provided in the semiconductor layer, and the guide region extends downward from the surface of the stepped groove to the drift region.

[0010] Optionally, the second gate dielectric fills up the remaining space outside the first gate dielectric in the stepped groove, and the second gate dielectric is flush with upper surfaces of the first gate dielectric on both sides of the stepped groove.

[0011] Optionally, the second gate dielectric fills up the remaining space outside the first gate dielectric in the stepped groove and is higher than the stepped groove, and two ends of the higher portion overlap the first gate dielectrics on both sides of the stepped groove.

[0012] Optionally, the raised portion partially covers the first gate dielectric just above the uppermost layer of the guide region.

[0013] Optionally, the remaining space outside the first gate dielectric in the stepped groove is filled with metal or polysilicon to form a grounding electrode; the second gate dielectric is superimposed on the grounding electrode and overlaps the first gate dielectric on both sides of the grounding electrode.

[0014] The present invention also provides another downward arch bridge type VDMOSFET device, comprising:

[0015] N-type substrate;

[0016] A semiconductor layer superimposed on the upper surface of the N-type substrate;

[0017] An N-type drift region formed by element doping the lower half of the semiconductor layer;

[0018] A symmetrical stepped groove formed by etching the upper half of the semiconductor layer;

[0019] A guide region extending downward from the surface of the stepped groove to the N-type drift region; wherein the bottom of the guide region is in contact with the N-type drift region;

[0020] The semiconductor layers on both sides of the guide area are doped with elements to form two parts of P wells, two parts of N+ source areas and two parts of P+ source areas; wherein the two parts of P wells are respectively located on both sides of the guide area; the upper ends of the two parts of P wells are avoided inwards to set the two parts of N+ source areas; the two parts of P+ source areas are respectively located on both sides of the two parts of P wells;

[0021] A first gate dielectric layer superimposed on the inner wall and both sides of the stepped groove;

[0022] A second gate dielectric located above the first gate dielectric in the stepped groove; wherein the first gate dielectric and the second gate dielectric together constitute a thickened gate dielectric layer of the downward arch bridge VDMOSFET device;

[0023] A gate electrode superimposed on the upper surface of the second gate dielectric and a portion of the upper surface of the first gate dielectric on both sides of the second gate dielectric;

[0024] An interlayer dielectric superimposed on the upper surface of the gate electrode and the upper surfaces of the first gate dielectric on both sides of the gate electrode;

[0025] A source electrode superimposed on the upper surface of the interlayer dielectric, the upper surfaces of the two portions of the N+ source regions, and the upper surfaces of the two portions of the P+ source regions;

[0026] A drain electrode is superimposed on the lower surface of the N-type substrate.

[0027] Optionally, the doping concentration of the guide area is 4E16cm -3 ~1E19cm -3 .

[0028] Optionally, the P-well is a multi-layer P-well formed by layered doping.

[0029] Optionally, the thickness of the thickened gate dielectric layer is greater than the thickness of the multi-layer P-well.

[0030] Optionally, in the multi-layer P well, the doping concentration of the top layer is 5E16cm -3 ~2E17cm -3 The doping concentration of the bottom layer is 5E16cm -3 ~5E19cm-3 .

[0031] In the downward arch bridge VDMOSFET device provided by the present invention, the gate dielectric layer of the VDMOSFET is raised by utilizing a stepped groove, thereby effectively increasing the thickness of the gate oxide dielectric layer, so that the VDMOSFET has better reliability; at the same time, a conduction region and a drift region are provided in the semiconductor layer, and the conduction region extends downward from the surface of the stepped groove to the drift region, so as to form a current path in the semiconductor layer and reduce the width of the gate electrode directly exposed to the drain end of the VDMOSFET. Therefore, the present invention can reduce the width between the gate electrode directly exposed to the drain electrode, so that the VDMOSFET also has better switching characteristics.

[0032] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of an existing common VDMOSFET;

[0034] Figure 2 It is a structural schematic diagram of an existing arch bridge VDMOSFET;

[0035] Figure 3 It is a partial structural schematic diagram of a first downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0036] Figure 4 It is a partial structural schematic diagram of a second downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0037] Figure 5 It is a partial structural schematic diagram of a third downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0038] Figure 6 It is a partial structural schematic diagram of a fourth downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0039] Figure 7 It is a schematic diagram of the overall structure of a first downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0040] Figure 8 It is a schematic diagram of the overall structure of a second downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0041] Fig. 9 1 is a schematic diagram of the overall structure of a third downward arch bridge VDMOSFET device provided by an embodiment of the present invention;

[0042] Fig.10 1 is a schematic diagram of the overall structure of a fourth downward arch bridge type VDMOSFET device provided by an embodiment of the present invention;

[0043] Fig.11 The thickness of the thickened gate dielectric layer and the width between the gate electrode directly exposed to the drain electrode are shown;

[0044] Fig.12 A schematic diagram showing shielding the capacitance of the gate electrode and the drain electrode to the capacitance between the gate electrode and the P-well in an embodiment of the present invention is shown;

[0045] Fig.13 It is a schematic diagram that the multi-layer P-well is thicker than the thickened gate dielectric layer;

[0046] Fig.14 The figure shows the location of the channel of the downward arch bridge VDMOSFET device provided by the embodiment of the present invention;

[0047] Fig.15 The current path of the downward arch bridge VDMOSFET device provided by the embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0049] In order to make the VDMOSFET have better reliability and switching characteristics, an embodiment of the present invention provides a downward arch bridge type VDMOSFET device. The downward arch bridge type VDMOSFET device provided by the embodiment of the present invention is described below through specific embodiments.

[0050] Embodiment 1:

[0051] The downward arch bridge VDMOSFET device provided in this embodiment 1 has a symmetrical stepped groove formed by etching its semiconductor layer A; the inner wall and both sides of the stepped groove are covered with a first gate dielectric 7; a second gate dielectric 8 is also provided on the first gate dielectric 7 in the stepped groove; the first gate dielectric 7 and the second gate dielectric 8 together constitute a thickened gate dielectric layer of the downward arch bridge VDMOSFET device; and a guide region 6 and a drift region are provided in the semiconductor layer A, and the guide region 6 extends downward from the surface of the stepped groove to the drift region, which is used to form a current path in the semiconductor layer A and reduce the width of the gate electrode 9 directly exposed to the drain end of the VDMOSFET.

[0052] Exemplarily, in one implementation, the conduction region 6 can be formed by implanting ions into the semiconductor layer A from the surface of the stepped groove, whereby the conduction region 6 forms a current path along the stepped groove, so that the width of the gate electrode 9 subsequently superimposed on the thickened gate dielectric layer and directly exposed to the drain electrode 12 can be made smaller.

[0053] In this embodiment 1, there are many specific implementations of combining the first gate dielectric 7 and the second gate dielectric 8 to form a thickened gate dielectric layer, which are described as follows:

[0054] In the first implementation, see Figure 3 The second gate dielectric 8 fills the remaining space outside the first gate dielectric 7 in the stepped groove, and the second gate dielectric 8 is flush with the upper surfaces of the first gate dielectric 7 on both sides of the stepped groove.

[0055] In the second implementation, see Figure 4 The second gate dielectric 8 fills the remaining space outside the first gate dielectric 7 in the stepped groove and is higher than the stepped groove, and both ends of the higher part overlap the first gate dielectric 7 on both sides of the stepped groove.

[0056] In the third implementation, Figure 4 Based on Figure 5 The second gate dielectric 8 fills the remaining space outside the first gate dielectric 7 in the stepped groove and is higher than the stepped groove, with both ends of the higher portion overlapping the first gate dielectric 7 on both sides of the stepped groove; and the higher portion partially covers the first gate dielectric 7 directly above the uppermost layer of the guide area 6.

[0057] In the fourth implementation, see Figure 6 The remaining space outside the first gate dielectric 7 in the stepped groove is filled with metal or polysilicon to form a grounding electrode 13; the second gate dielectric 8 is superimposed on the grounding electrode 13 and overlaps the first gate dielectric 7 on both sides of the grounding electrode 13.

[0058] Therefore, the gate dielectric layer of the VDMOSFET is raised by utilizing the stepped grooves, which effectively increases the thickness c of the gate oxide dielectric layer, so that the VDMOSFET has better reliability; at the same time, the presence of the conduction region 6 can reduce the width between the gate electrode 9 directly exposed to the drain electrode 12, so the VDMOSFET also has better switching characteristics.

[0059] In this embodiment 1, other structures included in the VDMOSFET device are not limited, and reference may be made to existing VDMOSFET devices, or to the following embodiment 2.

[0060] Embodiment 2:

[0061] Based on the same inventive concept as that of Example 1, Example 2 provides a specific downward arch bridge VDMOSFET device, see Figure 7 to Figure 10 , including: an N-type substrate 1, a semiconductor layer A, a first gate dielectric 7, a second gate dielectric 8, a gate electrode 9, an interlayer dielectric 10, a source electrode 11 and a drain electrode 12; wherein, the semiconductor layer A is provided with an N-type drift region 2, a stepped groove, a guide region 6, a P well 3, an N+ source region 4 and a P+ source region 5. Fig.14 The location of the channel region b of the device is shown in FIG. Fig.15 The current path of the device is shown in FIG.

[0062] Regarding the N-type substrate 1, its doping elements may be N (nitrogen), P (phosphorus) and other impurity ions that can form an N-type semiconductor, and its doping concentration may be 5E18cm -3 ~5E19cm -3 , and its thickness is preferably 200μm to 400μm.

[0063] Regarding the semiconductor layer A, it is superimposed on the upper surface of the N-type substrate 1; preferably, the material of the semiconductor layer A can be SiC, so that the downward arch bridge VDMOSFET device can be a silicon carbide device, which is more suitable for higher operating frequencies and has better stability at high temperatures. Of course, the material of the semiconductor layer A is not limited to SiC, for example, the semiconductor layer A can also be a silicon-based semiconductor layer A.

[0064] As for the N-type drift region 2 , it can be formed by doping the lower half of the semiconductor layer A with elements.

[0065] Preferably, the doping elements of the N-type drift region 2 are N, P and other impurity ions that can form N-type semiconductors, and the doping concentration is 5E14cm -3 ~2E16cm -3 The thickness of the N-type drift region 2 is determined by the voltage resistance level required by the device. For example, for a general 1200V-class device, the doping concentration of the N-type drift region 2 is preferably 8E15cm -3 , the thickness is preferably 9μm.

[0066] The stepped groove can be formed by etching the upper half of the semiconductor layer A; the groove width of the stepped groove increases step by step from bottom to top.

[0067] It should be noted that the embodiment of the present invention does not limit the groove width, groove depth and number of steps in the stepped groove, which can be determined through simulation optimization in practice.

[0068] As for the guide region 6 , it extends downward from the surface of the stepped groove to the N-type drift region, and its bottom is in contact with the N-type drift region.

[0069] In an optional implementation, the upper half of the semiconductor layer A may be N-type doped from the surface of the stepped groove to form the guide region 6 .

[0070] The conducting region 6 is used to form a current path in the semiconductor layer A, such as Fig.15 As shown in the path formed by the arrow in FIG. 1 , the guide region 6 starts from the upper surface of the semiconductor layer A and connects the P well 3 and extends to the upper surface or the inside of the N-type drift region 2; the guide region 6 can reduce the width w of the gate electrode 9 directly exposed to the drain terminal of the VDMOSFET, as shown in FIG. Fig.11 shown.

[0071] Preferably, the doping elements of the guide region 6 are N, P and other impurity ions that can form N-type semiconductors, and the doping concentration is 4E16cm -3 ~1E19cm -3 .

[0072] Regarding the P-well 3, N+ source region 4 and P+ source region 5, they can be formed by element doping the semiconductor layer A on both sides of the guide region 6, specifically forming two parts of the P-well 3, two parts of the N+ source region 4 and two parts of the P+ source region 5; wherein, the two parts of the P-well 3 are respectively located on both sides of the guide region 6; the two parts of the P+ source region 5 are respectively located on both sides of the two parts of the P-well 3, and the upper ends of the two parts of the P-well 3 are avoided inward and provided with two parts of the N+ source region 4; the two parts of the P+ source region 5 are respectively located on both sides of the two parts of the P-well 3 and the two parts of the N+ source region 4.

[0073] Preferably, the doping element of the P well 3 can be B (boron), AL (aluminum) and other impurity ions that can form a P-type semiconductor, and the doping concentration is preferably 5E16cm -3 ~5E19cm -3 The thickness is preferably 0.5 μm to 1.5 μm.

[0074] In a preferred implementation, the P well 3 is a multi-layer P well 3 formed by layered doping; wherein the doping concentration of the top layer determines the threshold voltage of the device, and the doping concentration is preferably 5E16cm -3 ~2E17cm -3 The bottom layer, which is the layer closest to the N-type drift region 2, has a doping concentration of 5E16cm because it has to bear the voltage together with the N-type drift region 2. -3 ~5E19cm -3 .

[0075] In a preferred implementation, the thickness c of the thickened gate dielectric layer is greater than the thickness k of the multilayer P well 3, see Fig.13 Thus, the thicker multilayer P-well 3 can push the electric field into the corner part of its body, such as Fig.13The two arcs in the middle represent the gathering places of the electric field. The P wells 3 on the left and right sides push the electric field into the silicon carbide body away from the gate dielectric layer. Therefore, the combination of thickened gate dielectric layer and multi-layer P wells 3 can greatly improve the reliability of the gate dielectric layer.

[0076] Preferably, the doping elements of the N+ source region 4 are N, P and other impurity ions that can form N-type semiconductors, and the doping concentration is 1E19cm -3 ~5E20cm -3 ; The thickness of the N+ source region 4 is preferably 0.1μm to 0.5μm.

[0077] Preferably, the doping element of the P+ source region 5 is B (boron), Al (aluminum) or other impurity ions that can form a P-type semiconductor, and the doping concentration is 1E19cm -3 ~5E20cm -3 , thickness is 0.5μm~1.5μm.

[0078] A first gate dielectric 7 is stacked on the bottom and both sides of the stepped groove. Exemplarily, the dielectric material of the first gate dielectric 7 can be silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiO N ), zirconium oxide (ZrO2) or zirconium oxynitride (ZrO N ) etc. The first gate dielectric 7 can be prepared by dry oxidation, wet oxidation, plasma oxidation, chemical vapor deposition (PECVD / LPCVD), atomic layer deposition and the like.

[0079] The second gate dielectric 8 is located above the first gate dielectric 7 in the stepped groove. The first gate dielectric 7 and the second gate dielectric 8 together form a thickened gate dielectric layer of the downward arch bridge VDMOSFET device. The thickness of the thickened gate dielectric layer is represented by c. Fig.11 and 13 . See Figure 7 to Figure 10 The specific implementation method of combining the first gate dielectric 7 and the second gate dielectric 8 to form a thickened gate dielectric layer is as follows: Figure 3 to Figure 6 The same is not repeated here.

[0080] Exemplarily, the dielectric material of the second gate dielectric 8 may be silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium oxide (Ga2O3), hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON) or spin-on glass, etc. The second gate dielectric 8 may be prepared by chemical vapor deposition (PECVD / LPCVD), atomic layer deposition, etc.

[0081] The gate electrode 9 is superimposed on the upper surface of the second gate dielectric 8 and on the upper surface of part of the first gate dielectric 7 on both sides of the second gate dielectric 8. For specific superposition methods, see Figure 7 to Figure 10 .

[0082] Preferably, the gate electrode 9 may be doped polysilicon, but is not limited thereto.

[0083] The interlayer dielectric 10 is superimposed on the upper surface of the gate electrode 9 and the upper surfaces of the first gate dielectric 7 on both sides of the gate electrode 9. For specific superposition methods, see Figure 7 to Figure 10 .

[0084] Preferably, the interlayer dielectric 10 may be spin-on glass, but is not limited thereto.

[0085] The source electrode 11 is superimposed on the upper surface of the interlayer dielectric 10 , the upper surfaces of two parts of the N+ source regions 4 , and the upper surfaces of two parts of the P+ source regions 5 ; both the N+ source regions 4 and the P+ source regions 5 form ohmic contacts with the source electrode 11 .

[0086] Preferably, the source electrode 11 may be metal Al, but is not limited thereto.

[0087] The drain electrode 12 is superimposed on the lower surface of the N-type substrate 1 .

[0088] Preferably, the drain electrode 12 may be metal Al, but is not limited thereto.

[0089] In the second embodiment, the gate dielectric layer of the VDMOSFET is also raised by using the stepped grooves, so that the VDMOSFET has better reliability; at the same time, the width w between the gate electrode 9 directly exposed to the drain electrode 12 is small, and the P well 3 below does not determine the threshold voltage of the device, so it can have a relatively high doping concentration, forming a P well 3 with good grounding quality, which can shield most of the gate-drain capacitance (such as Fig.12 As shown in the figure), the VDMOSFET also has better switching characteristics.

[0090] Furthermore, the area of ​​the gate electrode 9 directly exposed to the drain terminal in the second embodiment can be made smaller, and the thicker dielectric layer under the gate electrode 9 can also greatly reduce the gate-drain capacitance (eg Fig.12 The switching characteristics of the device are further improved.

[0091] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0092] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0093] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0094] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0095] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0096] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0097] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A downward arch bridge VDMOSFET device, characterized in that: The downward arch bridge VDMOSFET device has a symmetrical stepped groove formed by etching its semiconductor layer; the inner wall and both sides of the stepped groove are covered with a first gate dielectric; wherein a second gate dielectric is further provided on the first gate dielectric in the stepped groove; the first gate dielectric and the second gate dielectric together constitute a thickened gate dielectric layer of the downward arch bridge VDMOSFET device; A guide region and a drift region are provided in the semiconductor layer, and the guide region extends downward from the surface of the stepped groove to the drift region.

2. The downward arch bridge VDMOSFET device according to claim 1, characterized in that: The second gate dielectric fills up the remaining space outside the first gate dielectric in the stepped groove, and the second gate dielectric is flush with upper surfaces of the first gate dielectric on both sides of the stepped groove.

3. The downward arch bridge VDMOSFET device according to claim 1, characterized in that: The second gate dielectric fills the remaining space outside the first gate dielectric in the stepped groove and is higher than the stepped groove, with two ends of the higher portion overlapping the first gate dielectrics on both sides of the stepped groove.

4. The downward arch bridge VDMOSFET device according to claim 3, characterized in that: The raised portion partially covers the first gate dielectric just above the uppermost layer of the guide region.

5. The downward arch bridge VDMOSFET device according to claim 1, characterized in that: The remaining space outside the first gate dielectric in the stepped groove is filled with metal or polysilicon to form a grounding electrode; the second gate dielectric is superimposed on the grounding electrode and overlaps the first gate dielectric on both sides of the grounding electrode.

6. A downward arch bridge VDMOSFET device, characterized in that: include: N-type substrate; A semiconductor layer superimposed on the upper surface of the N-type substrate; An N-type drift region formed by element doping the lower half of the semiconductor layer; A symmetrical stepped groove formed by etching the upper half of the semiconductor layer; A guide region extending downward from the surface of the stepped groove to the N-type drift region; wherein the bottom of the guide region is in contact with the N-type drift region; The semiconductor layers on both sides of the guide area are doped with elements to form two parts of P wells, two parts of N+ source areas and two parts of P+ source areas; wherein the two parts of P wells are respectively located on both sides of the guide area; the upper ends of the two parts of P wells are avoided inwards to set the two parts of N+ source areas; the two parts of P+ source areas are respectively located on both sides of the two parts of P wells; A first gate dielectric layer superimposed on the inner wall and both sides of the stepped groove; A second gate dielectric located above the first gate dielectric in the stepped groove; wherein the first gate dielectric and the second gate dielectric together constitute a thickened gate dielectric layer of the downward arch bridge VDMOSFET device; A gate electrode superimposed on the upper surface of the second gate dielectric and a portion of the upper surface of the first gate dielectric on both sides of the second gate dielectric; An interlayer dielectric superimposed on the upper surface of the gate electrode and the upper surfaces of the first gate dielectric on both sides of the gate electrode; A source electrode superimposed on the upper surface of the interlayer dielectric, the upper surfaces of the two portions of the N+ source regions, and the upper surfaces of the two portions of the P+ source regions; A drain electrode is superimposed on the lower surface of the N-type substrate.

7. The downward arch bridge VDMOSFET device according to claim 6, characterized in that: The doping concentration of the guide area is 4E16cm -3 ~1E19cm -3 .

8. The downward arch bridge VDMOSFET device according to claim 6, characterized in that: The P-well is a multi-layer P-well formed by layered doping.

9. The downward arch bridge VDMOSFET device according to claim 8, characterized in that: The thickness of the thickened gate dielectric layer is greater than the thickness of the multi-layer P well.

10. The downward arch bridge VDMOSFET device according to claim 9, characterized in that: In the multi-layer P well, the doping concentration of the top layer is 5E16cm -3 ~2E17cm -3 The doping concentration of the bottom layer is 5E16cm -3 ~5E19cm -3 .

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