A trench type PMOS tube and manufacturing method

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a trench PMOS tube, which comprises: a P-type substrate, a P-type epitaxial layer, a cell region and a terminal region surrounding the cell region; the P-type epitaxial layer is located on the P-type substrate; the cell region and the terminal region are located on the P-type epitaxial layer; the cell trench of the cell region comprises a cell groove, a gate oxide layer and a gate polysilicon; the gate oxide layer is located on the bottom and sidewall of the cell groove, and the gate polysilicon is filled in the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer, and the boron-rich oxide layer is formed by injecting boron ions into the oxide layer. The PMOS tube has the advantages of low on-resistance, high avalanche withstand EAS capability and low voltage creep, thereby improving reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench-type PMOS transistor and a manufacturing method thereof. Background Art

[0002] A Trench PMOS (Positive Channel Metal Oxide Semiconductor) tube is a trench-type, P-type channel field-effect transistor. When a Trench PMOS tube is on, the majority carrier holes participate in the conduction. Its drive circuit is simpler than that of an NMOS tube and does not require a charge pump to boost the voltage. Instead, the I / O output of a control unit (such as an MCU) can drive the Trench PMOS tube on and off. Therefore, Trench PMOS tubes are often used in applications such as load switches, battery protection, motor drive high-side transistors, and power reverse protection.

[0003] Currently, trench PMOS transistors typically directly utilize the same structural design and process flow as NMOS transistors. The typical manufacturing process for trench PMOS transistors involves first forming trenches in the cell and terminal regions using a trench mask, then growing gate oxide and depositing gate polysilicon within the trenches, and finally forming the well region using a well mask. However, existing trench PMOS transistors fail to take their specific characteristics into account, resulting in higher on-resistance and lower reliability. Summary of the Invention

[0004] The embodiments of the present application provide a trench PMOS transistor and a manufacturing method, thereby solving the technical problem in the prior art that the trench PMOS transistor has a high on-resistance, resulting in low reliability of the trench PMOS transistor. This reduces the on-resistance of the trench PMOS transistor, improves the reliability of the trench PMOS transistor, saves the conduction loss of the trench PMOS transistor, and enables the trench PMOS transistor to have technical effects such as high avalanche withstand EAS capability and low voltage creep.

[0005] In a first aspect, an embodiment of the present invention provides a trench PMOS transistor, comprising: a P-type substrate, a P-type epitaxial layer, a cell region, and a terminal region surrounding the cell region;

[0006] The P-type epitaxial layer is located on the P-type substrate;

[0007] The cell region and the terminal region are located on the P-type epitaxial layer;

[0008] The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon;

[0009] The gate oxide layer is located on the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0010] Preferably, the boron ion implantation energy range is 10keV-30keV, and the boron ion implantation dose range is 1E10cm -2 ~2E12cm -2 .

[0011] Preferably, the cell region includes: n cell trenches, n+1 electrode regions, an N-type well region, a P+ contact region and a cell region dielectric layer, where n is a positive integer greater than 3;

[0012] The cell region dielectric layer is located on the P-type epitaxial layer;

[0013] The N-type well region is located in the P-type epitaxial layer, and the N-type well region is extended to contact a designated terminal trench of the terminal region, and the designated terminal trench is a terminal trench adjacent to the cell region;

[0014] The cell trenches and the electrode regions are alternately arranged, the cell trenches pass through the N-type well region and are located in the P-type epitaxial layer, and the electrode region passes through the cell region dielectric layer and is located in the N-type well region, wherein the depth of the cell trenches in the P-type epitaxial layer is greater than the depth of the N-type well region, and the upper surface of the N-type well region and the upper surface of the cell trenches are on the same horizontal plane as the upper surface of the P-type epitaxial layer;

[0015] The P+ contact region is located in the N-type well region, and the upper surface of the P+ contact region is at the same horizontal plane as the upper surface of the P-type epitaxial layer; the electrode regions except the electrode region adjacent to the designated cell trench all pass through the P+ contact region in the N-type well region, and the depth of the electrode region is greater than the junction depth of the P+ contact region, and the designated cell trench is the cell trench adjacent to the terminal region.

[0016] Preferably, the doping concentration range of the N-type well region is 2E16 cm-3-1E17 cm-3, so as to ensure that the voltage threshold of the trench PMOS tube reaches the target voltage value.

[0017] Preferably, each of the electrode regions comprises: a contact hole, a contact electrode and an N+ contact region;

[0018] The N+ contact region is located at the bottom of the contact hole;

[0019] The contact electrode is filled in the contact hole and is located above the N+ contact region.

[0020] Preferably, it further comprises: a source metal layer; the source metal layer is located on the cell region dielectric layer and covers the cell trench and the electrode region.

[0021] Preferably, the terminal region includes: a plurality of terminal grooves and a terminal region dielectric layer;

[0022] The plurality of terminal trenches are sequentially distributed outward from the cell region, each of the terminal trenches is located in the P-type epitaxial layer, and the upper surface of each terminal trench is in the same horizontal plane as the upper surface of the P-type epitaxial layer;

[0023] The terminal region dielectric layer is located on the P-type epitaxial layer and covers each of the terminal trenches.

[0024] Preferably, each of the terminal trenches comprises: a terminal groove, a terminal oxide layer and a terminal polysilicon;

[0025] The terminal oxide layer is located on the bottom and sidewalls of the terminal groove, wherein the terminal oxide layer is the boron-rich oxide layer;

[0026] The terminal polysilicon is filled in a space formed by the terminal oxide layer.

[0027] Preferably, it further comprises: a drain metal layer, wherein the drain metal layer is located below the P-type substrate.

[0028] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a trench-type PMOS transistor, which is used to manufacture the trench-type PMOS transistor described in the first aspect, and the manufacturing method comprises:

[0029] forming a P-type epitaxial layer on a P-type substrate;

[0030] forming a cell region and a terminal region on the P-type epitaxial layer;

[0031] The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon;

[0032] The gate oxide layer is located on the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0033] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0034] An embodiment of the present invention provides a trench PMOS transistor, comprising a P-type substrate, a P-type epitaxial layer, a cell region, and a termination region surrounding the cell region. The P-type epitaxial layer is located on the P-type substrate. The cell region and the termination region are located on the P-type epitaxial layer. A cell trench is defined in the cell region. The cell trench comprises a cell recess, a gate oxide layer, and gate polysilicon. The gate oxide layer is located on the inner wall of the cell recess, and the gate polysilicon fills the space formed by the gate oxide layer. The gate oxide layer is a boron-rich oxide layer formed by implanting boron ions into the oxide layer. Therefore, low-energy boron ions are implanted into the oxide layer to form the gate oxide layer, i.e., the boron-rich oxide layer. This reduces the on-resistance of the trench PMOS transistor without introducing oxide defects, while also optimizing the trench PMOS transistor's avalanche withstand (EAS) capability and negative voltage creep. The structural design of the trench PMOS transistor in the embodiment of the present invention greatly improves the reliability of the trench PMOS transistor and reduces the conduction loss of the trench PMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. Throughout the drawings, the same reference figures denote the same components. In the drawings:

[0036] Figure 1 A schematic structural diagram of a trench-type PMOS transistor in an embodiment of the present invention is shown;

[0037] Figure 2 A schematic structural diagram of the junction surface between the N-type well region and the P-type epitaxial layer of a conventional trench PMOS transistor in an embodiment of the present invention is shown;

[0038] Figure 3 A schematic diagram illustrating the structure of a conventional trench PMOS transistor in an embodiment of the present invention, in which a built-in electric field between an N-type well region and a P-type epitaxial layer causes hot carrier injection into a gate oxide layer when avalanche breakdown occurs;

[0039] Figure 4 Shown are on-resistance curves of a trench-gate PMOS transistor in which both the gate oxide layer of the cell trench and the terminal oxide layer of the terminal trench are oxide layers not implanted with low-energy boron ions, and a trench-gate PMOS transistor in which both the gate oxide layer of the cell trench and the terminal oxide layer of the terminal trench are boron-rich oxide layers in an embodiment of the present invention;

[0040] Figure 5A schematic structural diagram of the junction surface between the N-type well region and the P-type epitaxial layer of a trench PMOS transistor in an embodiment of the present invention is shown;

[0041] Figure 6 A schematic diagram of the structure of forming a P-type epitaxial layer on a P-type substrate, and forming a cell groove and a terminal groove in the P-type epitaxial layer in an embodiment of the present invention is shown;

[0042] Figure 7 A schematic diagram of the structure of forming a cell trench and a terminal trench in an embodiment of the present invention is shown;

[0043] Figure 8 A schematic structural diagram of forming an N-type well region in an embodiment of the present invention is shown;

[0044] Figure 9 A schematic structural diagram of forming a P+ contact region in an embodiment of the present invention is shown;

[0045] Figure 10 A schematic diagram showing the structure of forming a dielectric layer in a terminal region and a dielectric layer in a cell region in an embodiment of the present invention is shown;

[0046] Figure 11 A schematic diagram of the structure for forming a contact hole in an embodiment of the present invention is shown;

[0047] Figure 12 A schematic structural diagram of forming an N+ contact region and a contact electrode in a contact hole in an embodiment of the present invention is shown;

[0048] Figure 13 A schematic flow chart of the steps of a method for manufacturing a trench-type PMOS transistor in an embodiment of the present invention is shown.

[0049] In the figure, 101, P-type substrate; 102, P-type epitaxial layer; 200, cell region; 300, terminal region; 400, source metal layer; 500, drain metal layer;

[0050] 210, cell trench; 220, electrode region; 230, N-type well region; 240, P+ contact region; 250, cell region dielectric layer;

[0051] 211, cell groove; 212, gate oxide layer; 213, gate polysilicon;

[0052] 221, contact hole; 222, contact electrode; 223, N+ contact region;

[0053] 310, terminal trench; 320, terminal region dielectric layer;

[0054] 311. Terminal groove; 312. Terminal oxide layer; 313. Terminal polysilicon. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0056] Example 1

[0057] The first embodiment of the present invention provides a trench type PMOS transistor, such as Figure 1 As shown, it includes: a P-type substrate 101, a P-type epitaxial layer 102, a cell region 200, and a terminal region 300 surrounding the cell region 200. The P-type epitaxial layer 102 is located on the P-type substrate 101. The cell region 200 and the terminal region 300 are located on the P-type epitaxial layer 102. The cell trench 210 of the cell region 200 includes a cell groove 211, a gate oxide layer 212, and a gate polysilicon 213. The gate oxide layer 212 is located on the bottom and sidewalls of the cell groove 211, and the gate polysilicon 213 fills the space formed by the gate oxide layer 212. The gate oxide layer 212 is a boron-rich oxide layer, which is formed by implanting boron ions into the oxide layer.

[0058] It should be noted that the structure shown in the accompanying drawings of this embodiment is a schematic diagram of the smallest repeating unit of a trench-type PMOS transistor device. The P-type substrate 101 is a silicon-based substrate. The material of the P-type epitaxial layer 102 includes, but is not limited to, a silicon-based epitaxial layer. The cell trench 210 is located in the cell region 200. The cell trench 210 includes a cell recess 211, a gate oxide layer 212, and gate polysilicon 213. The gate oxide layer 212 is located on the bottom and sidewalls of the cell recess 211 and is a boron-rich oxide layer formed by implanting boron ions into the oxide layer. The oxide layer is made of oxide and boron ions. The gate polysilicon 213 fills the space formed by the gate oxide layer 212 and is made of a combination of polysilicon and polysilicon. The cell trench 210 serves as the gate of the trench-type PMOS transistor. In the accompanying drawings, the black and white checkered pattern area represents the boron-rich oxide layer.

[0059] This embodiment provides a trench-type PMOS transistor, which includes a P-type substrate 101, a P-type epitaxial layer 102, a cell region 200, and a terminal region 300 surrounding the cell region 200. The P-type epitaxial layer 102 is located on the P-type substrate 101. The cell region 200 and the terminal region 300 are located on the P-type epitaxial layer 102. A cell trench 210 is provided in the cell region 200. The cell trench 210 includes a cell groove 211, a gate oxide layer 212, and a gate polysilicon 213. The gate oxide layer 212 is located on the inner wall of the cell groove 211, and the gate polysilicon 213 fills the space formed by the gate oxide layer 212. The gate oxide layer 212 is a boron-rich oxide layer, which is formed by injecting boron ions into the oxide layer. Therefore, low-energy boron ions are injected into the oxide layer formed by the oxide to obtain the gate oxide layer 212, i.e., the boron-rich oxide layer. This reduces the on-resistance of the trench PMOS transistor without introducing oxide layer defects, while also optimizing the trench PMOS transistor's avalanche withstand (EAS) capability and negative voltage creep. The trench PMOS transistor's structural design in this embodiment significantly improves its reliability and reduces conduction losses.

[0060] Next, combine Figure 1 The structure of the trench PMOS transistor of this embodiment is described in detail:

[0061] The gate oxide layer 212 of the cell trench 210 is a boron-rich oxide layer. The boron-rich oxide layer is formed by low-energy boron ion implantation. The boron ion implantation energy range is 10keV-30keV, and the boron ion implantation dose range is 1E10cm -2 ~2E12cm -2 . The injection energy and injection dose of boron ions indicate that the injected boron ions are low-energy boron ions. Since boron ions are relatively light, that is, boron ions are light ions, most of the injection damage can be repaired in the subsequent thermal process. At the same time, the boron ions will diffuse into the silicon near the trench, causing the P-type doping concentration (the P-type doping concentration only refers to the doping concentration near the trench in the P-type epitaxial layer 102, where the trench is the cell trench 210 and the terminal trench 310) to increase. For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell trench 210 is conducive to expanding the current path and reducing the on-resistance. In addition, low-energy boron ions are injected into the oxide layer, so that the injection damage is small, which prevents the sensitive gate oxide layer from being subjected to large injection damage and affecting the quality of the gate oxide layer. The low-energy boron ions are used to ensure the reliability of the gate oxide layer 212 and the reliability of the trench-type PMOS tube.

[0062] Furthermore, the boron-rich oxide layer is formed by performing a single, maskless, low-energy boron ion implantation on the oxide layer within the trench, resulting in a simple and efficient formation. Furthermore, this formation process is cost-effective.

[0063] The cell region 200 includes: n cell trenches 210, n+1 electrode regions 220, an N-type well region 230, a P+ contact region 240, and a cell region dielectric layer 250, where n is a positive integer greater than 3. The cell region dielectric layer 250 is located on the P-type epitaxial layer 102. The N-type well region 230 is located in the P-type epitaxial layer 102. The N-type well region 230 extends to contact a designated terminal trench 310 of the terminal region 300. The designated terminal trench 310 is the terminal trench 310 adjacent to the cell region 200. The cell trenches 210 and the electrode regions 220 are arranged alternately. The cell trenches 210 pass through the N-type well region 230 and are located in the P-type epitaxial layer 102. The electrode region 220 passes through the cell region dielectric layer 250 and is located in the N-type well region 230. The depth of the cell trench 210 in the P-type epitaxial layer 102 is greater than the depth of the N-type well region 230. The upper surface of the N-type well region 230 and the upper surface of the cell trench 210 are coplanar with the upper surface of the P-type epitaxial layer 102. The P+ contact region 240 is located in the N-type well region 230. The upper surface of the P+ contact region 240 is coplanar with the upper surface of the P-type epitaxial layer 102. All electrode regions 220, except for the electrode region 220 adjacent to a designated cell trench 210, pass through the P+ contact region 240 in the N-type well region 230. The depth of the electrode region 220 is greater than the junction depth of the P+ contact region 240. The designated cell trench 210 is the cell trench 210 adjacent to the terminal region 300.

[0064] Specifically, if Figure 1The illustrated cell region 200 includes two cell trenches 210, three electrode regions 220, an N-type well region 230, a P+ contact region 240, and a cell region dielectric layer 250. The N-type well region 230 is located in the P-type epitaxial layer 102. The N-type well region 230 is an N-type doped region. The dotted patterned area with a white background in the accompanying drawings represents the N-type well region 230. The junction depth of the N-type well region 230 ranges from 0.5 μm to 1.5 μm, and the dopant in the N-type well region 230 includes, but is not limited to, phosphorus (P). The two cell trenches 210 are spaced apart and located in the P-type epitaxial layer 102 and the N-type well region 230. The depth of each cell trench 210 in the P-type epitaxial layer 102 is greater than the depth of the N-type well region 230. The P+ contact region 240 is located in the N-type well region 230 and to the left of the cell trench 210, away from the terminal region 300. The P+ contact region 240 is a heavily doped P-type well region. The dopant material of the P+ contact region 240 includes, but is not limited to, boron B and / or boron difluoride. The upper surface of the N-type well region 230, the upper surfaces of the two cell trenches 210, and the upper surface of the P+ contact region 240 are coplanar with the upper surface of the P-type epitaxial layer 102.

[0065] The cell region dielectric layer 250 is located above the P-type epitaxial layer 102. The cell region dielectric layer 250 covers the P+ contact region 240 and each cell trench 210. The material of the cell region dielectric layer 250 is nitride or oxide. The three electrode regions 220 all pass through the cell region dielectric layer 250 and are located in the N-type well region 230. The depth of each electrode region 220 is greater than the junction depth of the P+ contact region 240. The upper surfaces of the three electrode regions 220 are on the same horizontal plane as the upper surface of the cell region dielectric layer 250. The three electrode regions 220 are respectively the first electrode region, the second electrode region, and the third electrode region. The first electrode region is located on the left side of the cell trench 210 away from the terminal region 300 and passes through the P+ contact region 240 in the N-type well region 230. The second electrode region is located between the two cell trenches 210, and the third electrode region is located on the right side of the cell trench 210 of the adjacent terminal region 300, that is, the second electrode region and the third electrode region are respectively distributed on both sides of the designated cell trench 210, and are adjacent to the designated cell trench 210, so the two do not need to pass through the P+ contact region 240.

[0066] The doping concentration range of the N-type well region 230 is 2E16 cm -3 -1E17cm -3 Since the oxide layer forms a boron-rich oxide layer, i.e., the gate oxide layer 212, after being implanted with low-energy boron ions, the implanted boron ions will neutralize a portion of the doping concentration near the channel of the N-type well region 230. Therefore, compared with the N-type well region 230 of a conventional PMOS transistor with the same voltage specification and grain size, the doping concentration of the N-type well region 230 of this embodiment needs to be increased to ensure that the voltage threshold of the trench PMOS transistor of this embodiment reaches the target voltage value.

[0067] In this way, the oxide layer becomes a boron-rich oxide layer after low-energy boron ion implantation. Since boron ions are relatively light, most of the implantation damage can be repaired in the subsequent thermal process. At the same time, the boron ions will diffuse into the silicon near the trench, increasing the P-type doping concentration. For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell trench 210 is conducive to expanding the current path and reducing the on-resistance. At the same time, in order to compensate for the decrease in the relative doping concentration of the channel caused by the diffusion of boron ions, the doping concentration of the N-type well region 230 can be increased accordingly during the design; this not only ensures that the voltage threshold of the trench PMOS tube reaches the target voltage value, but also brings the additional benefits of reducing the parasitic transistor base resistance and improving the avalanche withstand EAS capability of the trench PMOS tube device. This in turn improves the reliability of the trench PMOS tube.

[0068] It should be noted that the voltage threshold of the trench PMOS transistor can be set according to actual needs. The voltage threshold of the trench PMOS transistor is proportional to the doping concentration of the N-type well region 230 .

[0069] Each electrode region 220 includes a contact hole 221, a contact electrode 222, and an N+ contact region 223. In the accompanying drawings, the black dot pattern area represents the N+ contact region 223, and the diamond pattern area represents the contact electrode 222. The N+ contact region 223 is located at the bottom of the contact hole 221. The N+ contact region 223 is a heavily N-type doped region, and the doping concentration of the N+ contact region 223 is greater than the doping concentration of the N-type well region 230. The dopant material of the N+ contact region 223 includes, but is not limited to, arsenic (As). The contact electrode 222 is filled in the contact hole 221 and is located above the N+ contact region 223. The material of the contact electrode 222 includes, but is not limited to, tungsten.

[0070] The trench PMOS transistor further includes a source metal layer 400. The source metal layer 400 is located on the P-type epitaxial layer 102 and covers the cell trench 210 and the electrode region 220. The material of the source metal layer 400 includes, but is not limited to, aluminum and copper.

[0071] The termination region 300 includes a plurality of termination trenches 310 and a termination region dielectric layer 320. The plurality of termination trenches 310 are sequentially distributed outward from the cell region 200. Each termination trench 310 is located in the P-type epitaxial layer 102, and the upper surface of each termination trench 310 is coplanar with the upper surface of the P-type epitaxial layer 102. The termination region dielectric layer 320 is located above the P-type epitaxial layer 102 and covers each termination trench 310.

[0072] Specifically, if Figure 1The termination region 300 shown includes three termination trenches 310 and a termination region dielectric layer 320. The number of termination trenches 310 can be adjusted based on actual needs. The three termination trenches 310 are a first termination trench, a second termination trench, and a third termination trench. Each termination trench 310 is located in the P-type epitaxial layer 102, and the upper surface of each termination trench 310 is coplanar with the upper surface of the P-type epitaxial layer 102. The first termination trench is located near the adjacent cell region 200, i.e., the first termination trench is the designated termination trench 310. The third termination trench is located away from the cell region 200, and the second termination trench is located between the first and third termination trenches. In the termination region 300, the termination trench 310 farthest from the cell region 200 is also referred to as a stop trench, and the third termination trench is also referred to as a stop trench. The termination region dielectric layer 320 is located above the P-type epitaxial layer 102 and covers each termination trench 310. Furthermore, both the terminal region dielectric layer 320 and the cell region dielectric layer 250 are ILD (Inter-Layer Dielectric) layers. An ILD layer is a dielectric material formed between the device and the metal layer, providing electrical isolation. ILD layers can effectively reduce parasitic capacitance between the metal and the substrate, improving parasitic field-effect transistors formed when metal crosses different regions.

[0073] Each terminal trench 310 includes a terminal recess 311, a terminal oxide layer 312, and a terminal polysilicon 313. The terminal oxide layer 312 is located on the bottom and sidewalls of the terminal recess 311 and is a boron-rich oxide layer. The terminal polysilicon 313 fills the space formed by the terminal oxide layer 312 and is made of a combination of polycrystalline silicon.

[0074] The terminal oxide layer 312 of the terminal trench 310 in this embodiment is a boron-rich oxide layer. For the terminal region 300, the boron-rich oxide layer reaches the saturated solubility of boron, significantly reducing the "boron absorption" phenomenon. The junction between the N-type well region 230 and the P-type epitaxial layer 102 approaches an ideal planar junction state, perpendicular to the gate oxide layer 212 and the terminal oxide layer 312 (i.e., the boron-rich oxide layer). The built-in electric field direction of the depletion layer (i.e., the depletion layer formed at the metallurgical interface of the PN junction) changes from the traditional oblique direction to the vertical direction, thereby reducing hot carrier injection into the terminal oxide layer 312 and significantly improving the voltage creep of the device. This further improves the reliability of the trench PMOS transistor.

[0075] The trench PMOS transistor further includes a drain metal layer 500, which is located below the P-type substrate 101. The drain metal layer 500 is made of titanium nickel silver.

[0076] In order to better understand the structural principle of the trench PMOS transistor of this embodiment, it is necessary to explain the existing trench PMOS transistor:

[0077] For existing trench-type PMOS transistors, since PMOS transistors conduct electricity primarily through hole carriers with relatively slow mobility and saturation drift velocity, compared to NMOS devices with the same voltage specifications and grain size, PMOS transistors with the same design structure have higher on-resistance. In addition, due to the "boron absorption and phosphorus expulsion" phenomenon of the oxide layer of the PMOS transistor, the junction between the N-type well region (N-body) and the P-type epitaxial layer (P-EPI) is not ideally perpendicular to the trench, but bends toward the bottom of the trench (i.e., the cell trench 210 and the terminal trench 310), as shown in Figure 2. Figure 2 As shown in the figure. As can be seen from the curvature effect, a curved junction surface will lead to electric field concentration, thereby reducing the device's withstand voltage. At the same time, since the electric field direction in the depletion layer of the PMOS tube is from the ionized donor in the N-type well region to the ionized acceptor in the P-epitaxial layer, when the device undergoes avalanche breakdown, the terminal oxide layer 312 near the N-body region of the N-type well region and the P-epitaxial layer P-EPI will be severely injected with hot carriers (electrons), as shown in the figure. Figure 3 As shown. This results in a more concentrated electric field distribution at the junction of the N-type well region, the P-type epitaxial layer, and the terminal oxide layer 312, ultimately causing the device's withstand voltage to further decrease after each avalanche breakdown. Furthermore, to ensure that the voltage threshold reaches the target voltage, the doping concentration of the N-type well region of existing trench PMOS transistors is typically low. This can easily cause the parasitic transistor formed by the P+ contact region 240, the N-type well region, and the P-type epitaxial layer to conduct during the switching process of non-embedded inductive loads, resulting in a failure of the device's avalanche withstand EAS.

[0078] The structural principle of the trench-type PMOS tube of this embodiment: the gate oxide layer 212 of the cell trench 210 and / or the terminal oxide layer 312 of the terminal trench 310 of the trench-type PMOS tube of this embodiment is a boron-rich oxide layer, that is, the oxide layer of the trench is formed by injecting low-energy boron ions into the boron-rich oxide layer. Since boron ions are relatively light, most of the implantation damage can be repaired in the subsequent thermal process. At the same time, boron ions will diffuse into the silicon near the trench, thereby increasing the P-type doping concentration. In addition, the junction surface between the N-type well region 230 and the P-type epitaxial layer 102 is close to an ideal planar junction state, perpendicular to the gate oxide layer 212 and the terminal oxide layer 312, especially perpendicular to the terminal oxide layer 312, and the direction of the built-in electric field in the depletion layer is changed from the traditional oblique direction to the longitudinal direction, thereby ensuring the voltage resistance performance of the device.

[0079] For the cell region 200, the increase of the P-type doping concentration at the bottom of the cell trench 210 is beneficial to expanding the current path and reducing the on-resistance. Figure 4At the same time, to compensate for the decrease in relative channel doping concentration caused by boron ion diffusion, the doping concentration of the N-type well region 230 can be increased accordingly during design. This not only ensures that the voltage threshold of the trench PMOS transistor reaches the target voltage value, but also has the additional benefits of reducing the parasitic transistor base resistance and improving the device's avalanche withstand EAS capability. For the terminal region 300, the boron-rich oxide layer has reached the saturated solubility of boron, and the "boron absorption" phenomenon will be greatly improved, as shown in FIG. Figure 5 As shown, the junction surface between the N-type well region 230 and the P-type epitaxial layer 102 is close to an ideal planar junction state, which is perpendicular to the terminal oxide layer 312. The direction of the built-in electric field in the depletion layer is changed from the traditional oblique direction to the vertical direction, which reduces the hot carrier injection of the terminal oxide layer 312 and greatly improves the voltage creep of the device.

[0080] Among them, Figure 4 As shown, the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both oxide layers that have not been implanted with low-energy boron ions is compared with the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both boron-rich oxide layers. The yellow dotted curve represents the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both boron-rich oxide layers, and the blue solid curve represents the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both oxide layers that have not been implanted with low-energy boron ions. Figure 4 In the figure, the abscissa represents the drain-source voltage Vds, and the ordinate represents the drain current Id. The slopes of the two curves show that the yellow curve has a significantly lower on-resistance than the blue curve, indicating that the on-resistance of the trench-gate PMOS transistor in which both the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are boron-rich oxide layers is lower than the on-resistance of the trench-gate PMOS transistor in which both the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are oxide layers that have not been implanted with low-energy boron ions.

[0081] Therefore, since boron ions are relatively light, most of the implantation damage can be repaired during the subsequent thermal process. At the same time, the boron ions will diffuse into the silicon near the trench, increasing the P-type doping concentration. For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell trench 210 is conducive to expanding the current path and reducing the on-resistance. At the same time, in order to compensate for the decrease in the relative doping concentration of the channel caused by the diffusion of boron ions, the doping concentration of the N-type well region 230 can be increased accordingly during the design. This not only ensures that the voltage threshold reaches the target voltage value, but also brings the additional benefits of reducing the parasitic transistor base resistance and improving the device's avalanche withstand EAS capability.

[0082] The following describes the manufacturing process of the trench PMOS transistor of this embodiment:

[0083] like Figure 6 As shown, a P-type epitaxial layer 102 is grown on the surface of a P-type substrate 101 (i.e., a silicon substrate). Photolithography, epitaxial layer etching, and other processes are performed at designated locations on the P-type epitaxial layer 102 to form multiple grooves, thereby forming the unit cell groove 211 and the terminal groove 311. The grooves (i.e., the unit cell groove 211 and the terminal groove 311) have a depth ranging from 0.8 μm to 2 μm, and a width ranging from 0.18 μm to 3 μm. Typically, the depth of the terminal groove 311 is greater than the depth of the unit cell groove 211.

[0084] like Figure 7 As shown, a gate dielectric layer is deposited on the wafer surface (specifically, on the surface of the P epitaxial layer), and low-energy boron ion implantation is performed without a mask to form a boron-rich oxide layer, namely, a gate oxide layer 212 and a terminal oxide layer 312. The gate dielectric layer is made of oxide, and the thickness of the gate dielectric layer ranges from 0.03 μm to 0.08 μm. The boron ion implantation energy ranges from 10 keV to 30 keV, and the boron ion implantation dose ranges from 1E10 to 2E12 cm -2 Polysilicon is deposited on the surface of the gate dielectric layer and etched back to be flush with the silicon plane to form dielectric trenches, namely, the cell trench 210 and the terminal trench 310 .

[0085] like Figure 8 As shown, photolithography and N-type ion implantation are performed at designated locations through a mask to form an N-type well region 230. The junction depth of the N-type well region 230 is in the range of 0.5um to 1.5um.

[0086] like Figure 9 As shown, photolithography and P-type ion implantation are performed at designated locations in the N-type well region 230 through a mask. The ion concentration after implantation is higher than the doping concentration of the P-type epitaxial layer, forming a P+ contact region 240. The junction depth of the P+ contact region 240 ranges from 0.15um to 0.3um.

[0087] like Figure 10 As shown, an ILD dielectric layer is deposited on the P-type epitaxial layer 102 to form a termination region dielectric layer 320 and a cell region dielectric layer 250. The ILD dielectric layer is made of nitride or oxide, and has a thickness ranging from 0.4 μm to 1 μm. That is, the thickness of the termination region dielectric layer 320 and the cell region dielectric layer 250 also ranges from 0.4 μm to 1 μm.

[0088] like Figure 11As shown, photolithography and dielectric layer etching are performed at designated locations using a mask to form contact holes 221, with the etching depth being greater than the junction depth of the P+ contact region 240. The width of the contact holes 221 ranges from 0.2 μm to 0.6 μm.

[0089] like Figure 12 As shown, an N+ contact region 223 is formed by maskless N-type ion implantation at a higher dose than that of the N-type well region 230 to reduce the contact resistance of the electrode. A contact electrode 222 is then filled in the contact hole 221 and is located above the N+ contact region 223.

[0090] like Figure 1 As shown, a source metal layer 400 is formed on the cell region dielectric layer 250 , and a drain metal layer 500 is formed under the P-type substrate 101 .

[0091] The manufacturing process of this embodiment allows boron ion implantation of the oxide layer without the need for additional masks, thus saving manufacturing time and costs and improving manufacturing efficiency. The trench PMOS transistor formed by the manufacturing process of this embodiment reduces the on-resistance of the trench PMOS transistor, improves the reliability of the trench PMOS transistor, reduces the conduction loss of the trench PMOS transistor, and also enables the trench PMOS transistor to have high avalanche withstand (EAS) capability and low voltage creep.

[0092] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0093] By performing maskless, low-energy boron ion implantation on the conventional gate oxide layer, a boron-rich gate oxide layer is created. Since the solubility of boron ions in the oxide layer reaches saturation, the curvature effect caused by the "boron absorption" phenomenon is greatly improved. At the same time, the direction of the electric field in the depletion layer changes from oblique to vertical, significantly reducing hot carrier injection into the oxide layer. Furthermore, the diffusion of boron into the silicon near the trench not only increases the current diffusion path and reduces the on-resistance of the trench PMOS transistor, but also increases the doping concentration of the designed N-type well region. Ultimately, while reducing the on-resistance of the trench PMOS transistor, the device's avalanche withstand (EAS) capability and negative voltage creep are also optimized.

[0094] Example 2

[0095] Based on the same inventive concept, the second embodiment of the present invention further provides a method for manufacturing a trench-type PMOS transistor, such as Figure 13 As shown, the manufacturing method for the trench-type PMOS transistor according to the first embodiment includes:

[0096] S601, forming a P-type epitaxial layer on a P-type substrate;

[0097] S602, forming a cell region and a terminal region on the P-type epitaxial layer;

[0098] The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon;

[0099] The gate oxide layer is located on the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0100] Since the manufacturing method of the trench-type PMOS transistor described in this embodiment is the manufacturing method adopted for implementing the trench-type PMOS transistor in the first embodiment of the present application, those skilled in the art will be able to understand the specific implementation methods and various variations of the manufacturing method of the trench-type PMOS transistor of this embodiment based on the trench-type PMOS transistor described in the first embodiment of the present application. Therefore, how the manufacturing method of the trench-type PMOS transistor realizes the trench-type PMOS transistor in the first embodiment of the present application will not be described in detail here. As long as those skilled in the art can implement the manufacturing method of the trench-type PMOS transistor adopted in the first embodiment of the present application, it falls within the scope of protection to be provided by this application.

[0101] It will be understood by those skilled in the art that although preferred embodiments of the present invention have been described, further changes and modifications may be made to these embodiments once those skilled in the art are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0102] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A trench PMOS tube, characterized in that: include: A P-type substrate, a P-type epitaxial layer, a cell region, and a terminal region surrounding the cell region; The P-type epitaxial layer is located on the P-type substrate; The cell region and the terminal region are located on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

2. The trench PMOS transistor according to claim 1, characterized in that: The boron ion implantation energy range is 10keV-30keV, and the boron ion implantation dose range is 1E10cm -2 ~2E12cm -2 .

3. The trench PMOS transistor according to claim 2, characterized in that: The cell region includes: n cell grooves, n+1 electrode regions, an N-type well region, a P+ contact region and a cell region dielectric layer, where n is a positive integer greater than 3; The cell region dielectric layer is located on the P-type epitaxial layer; The N-type well region is located in the P-type epitaxial layer, and the N-type well region is extended to contact a designated terminal groove of the terminal region, and the designated terminal groove is a terminal groove adjacent to the cell region; The cell grooves and the electrode regions are alternately arranged, the cell grooves pass through the N-type well region and are located in the P-type epitaxial layer, and the electrode region passes through the cell region dielectric layer and is located in the N-type well region, wherein the depth of the cell grooves in the P-type epitaxial layer is greater than the depth of the N-type well region, and the upper surface of the N-type well region and the upper surface of the cell grooves are on the same horizontal plane as the upper surface of the P-type epitaxial layer; The P+ contact region is located in the N-type well region, and the upper surface of the P+ contact region is at the same horizontal plane as the upper surface of the P-type epitaxial layer; the electrode regions except the electrode region adjacent to the designated cell groove all pass through the P+ contact region in the N-type well region, and the depth of the electrode region is greater than the junction depth of the P+ contact region, and the designated cell groove is the cell groove adjacent to the terminal region.

4. The trench PMOS transistor according to claim 3, characterized in that: The doping concentration range of the N-type well region is 2E16cm -3 -1E17cm -3 , to ensure that the voltage threshold of the trench PMOS tube reaches the target voltage value.

5. The trench PMOS transistor according to claim 3, characterized in that: Each of the electrode regions comprises: a contact hole, a contact electrode and an N+ contact region; The N+ contact region is located at the bottom of the contact hole; The contact electrode is filled in the contact hole and is located on the N+ contact region.

6. The trench PMOS transistor according to claim 3, characterized in that: Also includes: source metal layer; The source metal layer is located on the cell region dielectric layer and covers the cell trench and the electrode region.

7. The trench PMOS transistor according to claim 1, characterized in that: The terminal area includes: a plurality of terminal grooves and a terminal area dielectric layer; The plurality of terminal grooves are distributed outward in sequence from the cell region, each of the terminal grooves is located in the P-type epitaxial layer, and the upper surface of each terminal groove is in the same horizontal plane as the upper surface of the P-type epitaxial layer; The terminal region dielectric layer is located on the P-type epitaxial layer and covers each of the terminal trenches.

8. The trench PMOS transistor according to claim 7, characterized in that: Each of the terminal grooves comprises: a terminal groove, a terminal oxide layer and a terminal polysilicon; The terminal oxide layer is located on the bottom and sidewalls of the terminal groove, wherein the terminal oxide layer is the boron-rich oxide layer; The terminal polysilicon fills the space formed by the terminal oxide layer.

9. The trench PMOS transistor according to claim 1, characterized in that: Also includes: A drain metal layer is located below the P-type substrate.

10. A method for manufacturing a trench PMOS tube, characterized in that: Used to manufacture the trench PMOS transistor according to any one of claims 1 to 9, the manufacturing method comprising: forming a P-type epitaxial layer on a P-type substrate; forming a cell region and a terminal region on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

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