Differential analog-to-digital converter, conversion method and electronic equipment

Abstract

The invention provides a differential analog-to-digital converter, a conversion method and electronic equipment, and the converter comprises an analog-to-digital conversion module, and lower electrode plates of sampling capacitors of a first switched capacitor array and a second switched capacitor array are respectively connected with positive and negative phase input signals through switches; an upper pole plate of the sampling capacitor is respectively connected with positive and negative phase input ends of the pre-amplifier; two ends of the first resistor and the second resistor are respectively connected with a group of in-phase input and output ends of the pre-amplifier through switches; the quantization circuit is connected with the output end of the pre-amplifier and generates a switch control signal of the switched capacitor array; the first compensation module and the second compensation module are respectively connected with a group of inverted input and output ends of the pre-amplifier, and compensate the change of an input signal coupled to the input end of the pre-amplifier. The sampling thermal noise elimination technology is adopted, the signal bandwidth limited by the saturation problem of the amplifier is increased through the first-order approximate compensation module, and the sampling thermal noise elimination circuit has the advantages of being small in sampling capacitance, low in noise, small in occupied area, large in signal bandwidth and the like.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a differential analog-to-digital converter, a conversion method and electronic equipment. Background Art

[0002] An analog to digital converter (ADC) is a device that converts analog signals into digital signals. Analog signals are continuously changing signals, while digital signals are composed of a series of discrete values. The function of an analog to digital converter is to convert analog signals into digital signals that can be processed by computers or other digital devices.

[0003] With the continuous development of science and technology, the requirements for the accuracy, resolution, sampling rate, occupied area, power consumption, etc. of analog-to-digital converters are getting higher and higher. In order to overcome the limitation of sampling thermal noise on sampling capacitors, the solution that has attracted much attention at present is to reduce the impact of sampling thermal noise on ADC performance through double sampling; this solution can effectively eliminate noise under low-frequency input signals, however, in the case of high-frequency input signals, the rapidly changing input signal will cause the amplifier output to saturate, which greatly reduces the sampling thermal noise elimination effect and seriously reduces the linearity of the system.

[0004] Therefore, how to achieve high-quality sampling thermal noise elimination in both low-frequency input signals and high-frequency input signals while reducing the occupied area of ​​the analog-to-digital converter has become one of the urgent problems to be solved by technicians in this field.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a differential analog-to-digital converter, a conversion method and an electronic device, which are used to solve the problems of poor sampling thermal noise elimination effect, influence on system linearity, large occupied area, etc. in the prior art under the condition of high-frequency input signals.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a differential analog-to-digital converter, the differential analog-to-digital converter comprising at least:

[0008] An analog-to-digital conversion module, a first compensation module and a second compensation module;

[0009] The analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of a differential input signal; the analog-to-digital conversion module includes a first switch, a first switch capacitor array, a second switch, a third switch, a first capacitor, a first resistor, a fourth switch, a second switch capacitor array, a fifth switch, a sixth switch, a second capacitor, a second resistor, a preamplifier and a quantization circuit; the lower plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input signal via the first switch, and is also connected to the positive phase reference voltage and the negative phase reference voltage through the corresponding switches respectively; the upper plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input terminal of the preamplifier; both ends of the first resistor The positive phase input terminal and the positive phase output terminal of the preamplifier are connected via the second switch and the third switch respectively; the lower plate of the sampling capacitor in the second switch capacitor array is connected to the negative phase input signal via the fourth switch, and is also connected to the positive phase reference voltage and the negative phase reference voltage through corresponding switches respectively; the upper plate of the sampling capacitor in the second switch capacitor array is connected to the negative phase input terminal of the preamplifier; the two ends of the second resistor are connected to the negative phase input terminal and the negative phase output terminal of the preamplifier via the fifth switch and the sixth switch respectively; the quantization circuit is connected to the output terminal of the preamplifier, and generates switch control signals of the first switch capacitor array and the second switch capacitor array;

[0010] The input end of the first compensation module is connected to the inverting output end of the pre-amplifier, and the output end is connected to the non-inverting input end of the pre-amplifier, so as to compensate for the change of the non-inverting input signal coupled to the non-inverting input end of the pre-amplifier;

[0011] The input end of the second compensation module is connected to the non-phase output end of the pre-amplifier, and the output end is connected to the inverting input end of the pre-amplifier, so as to compensate for the change of the inverting input signal coupled to the inverting input end of the pre-amplifier;

[0012] Before sampling, the first switch capacitor array, the second switch capacitor array, and the pre-amplifier are reused to form a differential circuit with the first resistor and the second resistor.

[0013] Optionally, the first compensation module and the second compensation module both include a seventh switch, an eighth switch and a compensation capacitor;

[0014] One end of the seventh switch is connected to the corresponding output end of the pre-amplifier, and the other end is connected to the lower plate of the compensation capacitor;

[0015] One end of the eighth switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor;

[0016] The upper plate of the compensation capacitor is connected to the corresponding input terminal of the pre-amplifier;

[0017] The sampling timing of the seventh switch is consistent with the sampling timing of the sampling capacitor in the analog-to-digital conversion module, and the on-off state of the eighth switch is opposite to that of the seventh switch.

[0018] More optionally, the differential analog-to-digital converter satisfies:

[0019] Δt=R d ·C R ;

[0020] Among them, Δt is the time difference between the two samples, R d is the resistance value of the first resistor and the second resistor, C R is the value of the compensation capacitor.

[0021] More optionally, the analog-to-digital conversion module is a SAR ADC structure.

[0022] More optionally, the quantization circuit includes a ninth switch, a first noise elimination capacitor, a tenth switch, an eleventh switch, a second noise elimination capacitor, a twelfth switch, a latch, and a SAR logic unit;

[0023] The lower plate of the first noise elimination capacitor is connected to the non-inverting output terminal of the pre-amplifier via the ninth switch; one end of the tenth switch is connected to the upper plate of the first noise elimination capacitor, and the other end is connected to the common mode voltage; the lower plate of the second noise elimination capacitor is connected to the inverting output terminal of the pre-amplifier via the eleventh switch; one end of the twelfth switch is connected to the upper plate of the second noise elimination capacitor, and the other end is connected to the common mode voltage;

[0024] The input end of the latch is respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; the SAR logic unit is connected to the output end of the latch, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on the output signal of the latch.

[0025] More optionally, the analog-to-digital conversion module is a Pipe-SAR ADC structure.

[0026] More optionally, the quantization circuit includes a ninth switch, a first noise elimination capacitor, a tenth switch, an eleventh switch, a second noise elimination capacitor, a twelfth switch, a comparator, a SAR logic unit, a post-amplifier, a thirteenth switch, a fourteenth switch, a first feedback capacitor, a fifteenth switch, a sixteenth switch, a second feedback capacitor and at least one SAR ADC unit;

[0027] The lower plate of the first noise elimination capacitor is connected to the non-inverting output terminal of the pre-amplifier via the ninth switch; one end of the tenth switch is connected to the upper plate of the first noise elimination capacitor, and the other end is connected to the common mode voltage; the lower plate of the second noise elimination capacitor is connected to the inverting output terminal of the pre-amplifier via the eleventh switch; one end of the twelfth switch is connected to the upper plate of the second noise elimination capacitor, and the other end is connected to the common mode voltage;

[0028] The input end of the comparator is respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor;

[0029] The SAR logic unit is connected to the output end of the comparator, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on the output signal of the comparator;

[0030] The input end of the post-stage amplifier is respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor, and forms a ring amplifier with the pre-amplifier;

[0031] The lower plate of the first feedback capacitor is connected to the common mode voltage via the thirteenth switch, and is also connected to the first output end of the post-stage amplifier via the fourteenth switch; the upper plate of the first feedback capacitor is connected to the output end of the first switch capacitor array; the lower plate of the second feedback capacitor is connected to the common mode voltage via the fifteenth switch, and is also connected to the second output end of the post-stage amplifier via the sixteenth switch; the upper plate of the second feedback capacitor is connected to the output end of the second switch capacitor array;

[0032] The SAR ADC units of each stage are cascaded in sequence to the output end of the post-stage amplifier.

[0033] More optionally, the quantization circuit also includes a seventeenth switch, an eighteenth switch, a third resistor and a fourth resistor; the third resistor is connected between the tenth switch and the common mode voltage, and the seventeenth switch is connected in parallel across the third resistor; the fourth resistor is connected between the twelfth switch and the common mode voltage, and the eighteenth switch is connected in parallel across the fourth resistor.

[0034] To achieve the above object and other related objects, the present invention further provides an analog-to-digital conversion method, which is implemented based on the above differential analog-to-digital converter, and the analog-to-digital conversion method at least includes:

[0035] Differentiating the input signal to obtain a compensation voltage, collecting the input signal and the sampled thermal noise to the input end of the preamplifier at a first sampling moment, and simultaneously loading the compensation voltage to the input end of the preamplifier to compensate for the voltage change of the input signal coupled to the input end of the preamplifier;

[0036] At the second sampling moment, sampling and storing the signals that have been compensated and pre-amplified in sequence;

[0037] In the quantization stage, the sampling thermal noise stored at the output of the preamplifier and the sampling thermal noise sampled at the input of the preamplifier are offset by the closed loop of the preamplifier; the potential of the lower plate of the sampling capacitor is adjusted based on successive approximation logic, thereby realizing analog-to-digital conversion.

[0038] To achieve the above object and other related objects, the present invention further provides an electronic device, which at least includes: the above differential analog-to-digital converter.

[0039] As described above, the differential analog-to-digital converter, conversion method and electronic device of the present invention have the following beneficial effects:

[0040] 1. The differential analog-to-digital converter, conversion method and electronic device of the present invention offset the voltage change coupled from the input signal through the compensation module, thereby reducing the signal change at the pre-amplifier input node, avoiding saturation of the pre-amplifier output, greatly improving the spurious-free dynamic range of the analog-to-digital converter, and improving the stability and reliability of the analog-to-digital converter under high-frequency signals; at the same time, the differentiation of the compensation voltage is achieved by multiplexing the sampling capacitor and the pre-amplifier, further reducing the occupied area.

[0041] 2. The differential analog-to-digital converter, conversion method and electronic device of the present invention eliminate sampling thermal noise based on double sampling technology, effectively reduce equivalent input noise, and thus reduce the area of ​​the sampling capacitor.

[0042] 3. The differential analog-to-digital converter, conversion method and electronic device of the present invention have significant advantages in improving analog-to-digital conversion performance and widening signal bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Shown is a structural schematic diagram of the differential analog-to-digital converter of the present invention.

[0044] Figure 2 Shown is a schematic structural diagram of the compensation module of the present invention.

[0045] Figure 3 Shown is another structural schematic diagram of the differential analog-to-digital converter of the present invention.

[0046] Figure 4 Display as Figure 1and Figure 3 Schematic diagram of the working timing of the differential analog-to-digital converter.

[0047] Figure 5 Shown is another structural schematic diagram of the differential analog-to-digital converter of the present invention.

[0048] Figure 6 Display as Figure 5 Schematic diagram of the working timing of the differential analog-to-digital converter.

[0049] Figure 7 It is a schematic diagram showing the principle of the output saturation of the pre-amplifier of the present invention when a high-frequency signal is applied.

[0050] Component number description

[0051] 1 Differential analog-to-digital converter

[0052] 11 Analog-to-digital conversion module

[0053] 111a, 111b Switched capacitor array

[0054] 112 Pre-amplifier

[0055] 113 Quantization Circuit

[0056] 113a Latch

[0057] 113b SAR logic unit

[0058] 113c Comparator

[0059] 113d Power Amplifier

[0060] 113e SAR ADC Unit

[0061] 12a, 12b The first and second compensation modules DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] See also Figure 1 to Figure 7It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0064] like Figure 1 and Figure 5 As shown, the present invention provides a differential analog-to-digital converter 1, which includes: an analog-to-digital conversion module 11, a first compensation module 12a and a second compensation module 12b. The analog-to-digital conversion module 11 eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of a differential input signal; the input end of the first compensation module 12a is connected to the inverting output end of the preamplifier in the analog-to-digital conversion module 11, and the output end is connected to the positive input end of the preamplifier to compensate for the change of the positive input signal Vip coupled to the positive input end of the preamplifier; the input end of the second compensation module 12b is connected to the positive output end of the preamplifier, and the output end is connected to the inverting input end of the preamplifier to compensate for the change of the inverting input signal Vin coupled to the inverting input end of the preamplifier.

[0065] like Figure 1 and Figure 5 As shown, the analog-to-digital conversion module 11 includes a first switch K1, a first switch capacitor array 111a, a second switch K2, a third switch K3, a first capacitor C1, a first resistor R1, a fourth switch K4, a second switch capacitor array 111b, a fifth switch K5, a sixth switch K6, a second capacitor C2, a second resistor R2, a preamplifier 112 and a quantization circuit 113. The lower plate of the sampling capacitor in the first switch capacitor array 11a is connected to the positive phase input signal Vip via the first switch K1, and is also connected to the positive phase reference voltage V through the corresponding switches. RP And the inverting reference voltage V RN ; The first switch K1 is controlled by the first control signal The upper plate of the sampling capacitor in the first switch capacitor array 111a is connected to the non-inverting input terminal of the pre-amplifier 112. The two ends of the first resistor R1 are connected to the non-inverting input terminal and the non-inverting output terminal of the pre-amplifier 112 via the second switch K2 and the third switch K3, respectively. The second switch K2 and the third switch K3 are both controlled by the first control signal The connection relationship between the fourth switch K4, the second switch capacitor array 111b, the fifth switch K5, the sixth switch K6, the second resistor R2 and the second capacitor C2 is similar and will not be described in detail here. In this embodiment, the preamplifier 112 is configured as a high-bandwidth low-noise amplifier. The quantization circuit 113 is connected to the output end of the preamplifier 112 and generates switch control signals for the first switch capacitor array 111a and the second switch capacitor array 111b.

[0066] like Figure 2 As shown, in this embodiment, the first compensation module 12a and the second compensation module 12b both include a seventh switch K7, an eighth switch K8 and a compensation capacitor C R One end of the seventh switch K7 is connected to the corresponding output end of the preamplifier 112, and the other end is connected to the compensation capacitor C R The seventh switch K7 is controlled by the first control signal One end of the eighth switch K8 is connected to the common mode voltage V CM , the other end is connected to the compensation capacitor C R The eighth switch K8 is controlled by the first control signal The counter signal That is, the on-off state of the eighth switch K8 is opposite to that of the seventh switch K7. R The upper plate of the compensation module is used as the output end of the compensation module (connected to the corresponding input end of the preamplifier 112). The input end and the output end of the preamplifier 112 connected to the same compensation module have opposite polarities. The sampling timing of the seventh switch K7 is consistent with the sampling timing of the sampling capacitor in the analog-to-digital conversion module 11. Figure 4 As shown, in the sampling stage, the first switch capacitor array 111a, the second switch capacitor array 111b, and the preamplifier 112 are multiplexed, and a differential circuit is formed with the first resistor R1 and the second resistor R2. After the input signal is differentiated, it is loaded to the input end of the preamplifier 112 through the corresponding compensation module to compensate for the change in the input signal coupled to the input end of the preamplifier. Any circuit structure that can load the differentially processed signal output by the preamplifier 112 to the corresponding input end of the preamplifier 112 is applicable to the compensation module of the present invention, and is not limited to this embodiment.

[0067] As an implementation of the present invention, the analog-to-digital conversion module 11 is a SAR ADC structure. Figure 1 As shown, as an example, the quantization circuit 113 includes a ninth switch K9, a first noise elimination capacitor C NCa , the tenth switch K10, the eleventh switch K11, the second noise elimination capacitor C NCb , a twelfth switch K12, a latch 113a and a SAR logic unit 113b.

[0068] Specifically, the first noise elimination capacitor C NCa The lower electrode plate is connected to the positive phase output terminal of the preamplifier 112 via the ninth switch K9; the ninth switch K9 is controlled by the first control signal The counter signal One end of the tenth switch K10 is connected to the first noise elimination capacitor C NCa The other end is connected to the common mode voltage V CMThe tenth switch K10 is controlled by the second control signal The eleventh switch K11 and the second noise elimination capacitor C NCb The connection relationship between the latch 113a and the twelfth switch K12 is similar, and will not be repeated here. The input terminals of the latch 113a are respectively connected to the first noise elimination capacitor C NCa The second noise elimination capacitor C NCb The preamplifier 112 and the latch 113a form a comparator. The SAR logic unit 113b is connected to the output end of the latch 113a, and controls each switch in the first switch capacitor array 111a and the second switch capacitor array 111b to switch to the corresponding reference voltage (positive phase reference voltage V RP Or inverting reference voltage V RN ) to achieve successive approximation analog-to-digital conversion.

[0069] Furthermore, if Figure 3 As shown, the analog-to-digital conversion module 11 further includes a seventeenth switch K17, an eighteenth switch K18, a third resistor R3 and a fourth resistor R4. The third resistor R3 is connected to the tenth switch K10 and the common mode voltage V CM The seventeenth switch K17 is connected in parallel to both ends of the third resistor R3, and the seventeenth switch K17 is controlled by the fourth control signal Used to adjust the first noise elimination capacitor C NCa The potential of the upper plate is the first noise elimination capacitor C after the sampling capacitor sampling is completed and before the noise elimination capacitor sampling NCa The potential of the upper plate changes from the common mode voltage V CM The voltage is adjusted up to the sum of the common mode voltage and the voltage drop on the third resistor; similarly, the connection relationship and function of the fourth resistor R4 and the eighteenth switch K18 are similar and will not be described in detail here.

[0070] The control timing of the analog-to-digital conversion module 11 of this implementation is as follows: Figure 4 As shown. Any SAR ADC structure that eliminates sampling thermal noise based on a double sampling method is applicable to the present invention, and is not limited to this embodiment. The analog-to-digital conversion module 11 based on the SAR ADC structure of the present invention embeds a noise elimination capacitor at the output end of the pre-amplifier 112, and cooperates with the original sampling capacitor Cs to achieve double sampling, collect sampling thermal noise and eliminate the noise in the process of successive approximation quantization; therefore, the analog-to-digital converter can achieve a high signal-to-noise and distortion ratio (SNDR).

[0071] As another implementation of the present invention, in order to improve the quantization speed, the analog-to-digital conversion module 11 is set to a Pipe-SAR ADC structure. Figure 5As shown, as an example, the quantization circuit 113 includes a ninth switch K9, a first noise elimination capacitor C NCa , the tenth switch K10, the eleventh switch K11, the second noise elimination capacitor C NCb , a twelfth switch K12, a comparator 113c, a SAR logic unit 113b, a post-amplifier 113d, a thirteenth switch K13, a fourteenth switch K14, a first feedback capacitor C FBa , a fifteenth switch K15, a sixteenth switch K16, a second feedback capacitor C FBb and at least one SAR ADC unit 113e; wherein the ninth switch K9, the first noise elimination capacitor C NCa , the tenth switch K10, the eleventh switch K11, the second noise elimination capacitor C NCb , the twelfth switch K12 and Figure 1 The first input terminal and the second input terminal of the comparator 113c are respectively connected to the first noise elimination capacitor C NCa The second noise elimination capacitor C NCb The SAR logic unit 113b is connected to the output terminal of the comparator 113c, and controls each switch in the first switch capacitor array 111a and the second switch capacitor array 111b to switch to the corresponding reference voltage based on the output signal (the comparison result of each bit) of the comparator 113c. The first input terminal and the second input terminal of the post-amplifier 113d are respectively connected to the first noise elimination capacitor C NCa And the second noise elimination capacitor C NCb The first feedback capacitor C FBa The lower plate of is connected to the common mode voltage V via the thirteenth switch K13 CM , and is also connected to the first output terminal of the post-stage amplifier 113d via the fourteenth switch K14; the thirteenth switch K13 is controlled by the second control signal The fourteenth switch K14 is controlled by the third control signal The first feedback capacitor C FBa The upper plate of the second feedback capacitor C is connected to the output end of the first switch capacitor array 111a; FBbThe connection relationship of the fifteenth switch K15 and the sixteenth switch K16 is similar, and will not be repeated here. Each level of SAR ADC unit 117 is cascaded in sequence to the output end of the post-stage amplifier 113d; in this example, only one level of SAR ADC unit 117 is set as the second level SAR ADC. Similarly, further, the analog-to-digital conversion module 11 of this implementation method may also include a seventeenth switch K17, an eighteenth switch K18, a third resistor R3 and a fourth resistor R4, and the connection relationship and function are the same as Figure 3 The same, I will not elaborate here one by one.

[0072] The control timing of the analog-to-digital conversion module 11 of this implementation is as follows: Figure 6 As shown, the analog-to-digital conversion module 11 of this implementation can achieve a high signal-to-noise-distortion ratio and a high sampling rate.

[0073] like Figure 1 to Figure 6 As shown in the figure, at sampling time t1, the sampling capacitor Cs is controlled to sample based on the lower plate, and an additional sampling time t2 is added on this basis to control the sampling of the noise elimination capacitor; there is a delay Δt between sampling time t1 and sampling time t2. The sampling thermal noise at sampling time t1 is regarded as dynamic offset, and the influence of the sampling thermal noise is offset by self-zeroing through double sampling of the sampling capacitor Cs and the noise elimination capacitor. For simplicity, Figure 5 Take the single side of the differential structure as an example to illustrate, Figure 7 As shown, in the initial state, the first switch K1, the second switch K2, the third switch K3, the tenth switch K10 and the thirteenth switch K13 are in the state of the first control signal and the second control signal Under the control of, they are all in a closed state; at the sampling time t1, the first control signal The second switch K2 and the third switch K3 are controlled to be disconnected, and the ninth switch K9 is closed. At this time, the sampling thermal noise is fixed. For a continuously working analog-to-digital converter, this noise can be regarded as random noise of the system, but for the current sampling quantization process, this noise can also be regarded as dynamic offset. In this example, in order to increase energy efficiency, the amplifier in the multiplexed SAR ADC comparator is used as a pre-amplifier to treat the sampling thermal noise as the offset of the pre-amplifier after Δt (sampling time t2), and the output offset self-zeroing method is used to offset the impact of this noise on the performance of the analog-to-digital conversion system, thereby breaking through the limitation of the signal-to-noise and distortion ratio (SNDR) of a small sampling capacitor.

[0074] During Δt, the positive input signal V ip is also changing and is coupled to the input terminal V of the preamplifier 112 through the sampling capacitor Cs. TP; Sampling thermal noise and coupling to V through sampling capacitor Cs TP The changing input signals of the nodes are amplified by the preamplifier 112. In simple terms, the output voltage of the preamplifier 112 satisfies at sampling time t2:

[0075] A 1out (t2) = A1 · [V ip (t2)-V ip (t1)+v ns1 ] (1);

[0076] Where A1 is the gain of the preamplifier 112, V ip (t2) is the value of the input signal at sampling time t2, V ip (t1) is the value of the input signal at sampling time t1, v ns1 is the sampling thermal noise on the sampling capacitor Cs at sampling time t1. It is worth noting that formula (1) does not include the influence of other non-ideal factors such as the offset and noise of the pre-amplifier 112; nor does it consider the gain coefficient caused by the parasitic capacitance and feedback capacitance at the input end of the pre-amplifier 112 on the output calculation of the pre-amplifier 112.

[0077] The noise introduced by the preamplifier 112 at the sampling time t2 is equivalent to the input end, satisfying the following relationship:

[0078]

[0079] Where γ is the noise coefficient, k is the Boltzmann constant, T is the temperature, C NC is the capacitance of the noise elimination capacitor.

[0080] Under low frequency input signal, due to the positive phase input signal V ip The change itself is relatively slow. In the Δt time period, the positive input signal V ip The change in the amount is relatively small; however, when the positive input signal V ip When it is a high frequency signal, due to the rapid change, the positive phase input signal V ip The variation of is relatively large, such as Figure 7 As shown, if the sampling capacitor C S The change in the coupled input signal is amplified (A1·[V ip (t2)-V ip(t1)]) exceeds the output range of the preamplifier 112, the performance of the analog-to-digital converter will be seriously reduced; the above problem can be alleviated by reducing the delay Δt or reducing the gain of the preamplifier 112. Combining formula (1) and formula (2), reducing the delay Δt requires increasing the bandwidth of the preamplifier 112 to better collect the sampling thermal noise on the noise elimination capacitor; if the noise introduced by the preamplifier 112 at the sampling time t2 is to be guaranteed to remain unchanged, the power consumption of the preamplifier 112 needs to be increased, which may seriously reduce the overall energy efficiency of the system. On the other hand, reducing the gain of the preamplifier 112 can also alleviate the problem of amplifier saturation, but this will also cause the preamplifier 112 to introduce greater noise at the sampling time t2, reducing the overall signal-to-noise distortion ratio of the analog-to-digital converter. This limitation limits the ability of sampling thermal noise elimination technology to improve signal bandwidth.

[0081] The compensation module 12 of the present invention compensates the influence of the change signal on the input node of the preamplifier 112 through a first-order approximate compensation path, effectively canceling the input signal (satisfying ) is coupled to the input node of the preamplifier 112, so that the preamplifier 112 can work in a smaller input range, which not only ensures the elimination of sampling thermal noise, but also improves the linearity of the system. and the second control signal When the first switch K1, the second switch K2, the third switch K3 and the seventh switch K7 are all closed, at this time, the first resistor R1 and the first capacitor C1 are connected in parallel between the input end and the output end of the pre-amplifier 112, and the compensation capacitor C1 in the first compensation module 12a is R The charge on the sampling capacitor Cs is equal to the charge on the first capacitor C1, and they cancel each other out; the sampling capacitor Cs, the first resistor R1 and the preamplifier 112 form a differential circuit. Without considering the limited gain and limited bandwidth of the operational amplifier in the differential circuit, the output V op satisfy:

[0082] V op =-R d ·C S ·dV ip (3);

[0083] Among them, R d is the resistance value of the first resistor R1, C S is the capacitance of the sampling capacitor Cs, dV ip It is the differential of the positive phase input signal Vip.

[0084] At sampling time t1, the second switch K2, the third switch K3 and the seventh switch K7 are turned off, the eighth switch K8 and the ninth switch K9 are turned on, and the compensation capacitor C RThe lower plate of the CM , the compensation path passes through the compensation capacitor C R V TP The voltage change of the node satisfies:

[0085]

[0086] Among them, C P V TP The parasitic capacitance of the node, C R is the value of the compensation capacitor. Combining formula (1) and formula (4), we can get if:

[0087]

[0088] That is, Δt=R d ·C R (6); then V TP The voltage of the node is compensated in a first-order approximation, which can reduce the sampling thermal noise while avoiding the saturation of the output voltage of the preamplifier 112. In addition, this compensation condition is independent of the input signal frequency.

[0089] It should be noted that the above principle is described based on a differential analog-to-digital converter with a Pipe-SAR ADC structure. The principle of a differential analog-to-digital converter based on a SAR ADC structure is similar and will not be described in detail here.

[0090] The present invention also provides an analog-to-digital conversion method, which is implemented based on the differential analog-to-digital converter of the present invention. The method comprises:

[0091] 1) The input signal is differentiated to obtain a compensation voltage. At the first sampling time t1, the input signal and the sampled thermal noise are collected to the input end of the preamplifier 112, and the compensation voltage is loaded to the input end of the preamplifier 112 to compensate for the voltage change of the input signal coupled to the input end of the preamplifier 112.

[0092] Specifically, in this embodiment, Figure 5 The Pipe-SAR ADC structure of the differential analog-to-digital converter is taken as an example. In the initial state, the first control signal and the second control signal is high level, the third control signal is low level, the seventh switch K7 in each compensation module is closed, and the eighth switch K8 is opened; the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the tenth switch K10, the twelfth switch K12, the thirteenth switch K13 and the fifteenth switch K15 in the analog-to-digital conversion module are closed, and the ninth switch K9, the eleventh switch K11, the fourteenth switch K14 and the sixteenth switch K16 are opened. At this time, the sampling capacitor Cs, the preamplifier 112 and the first resistor R1 and the second resistor R2 form a differential circuit to differentiate the differential input signal. At the first sampling time t1, the first control signal The voltage jumps to a low level, the seventh switch K7 in each compensation unit is disconnected, and the eighth switch K8 is closed; the second switch K2, the third switch K3, the fifth switch K5 and the sixth switch K6 in the analog-to-digital conversion module are disconnected, the ninth switch K9 and the eleventh switch K11 are closed, the first resistor R1, the second resistor R2, the first capacitor C1 and the second capacitor C2 are disconnected from the circuit, the lower plate of the noise elimination capacitor is connected to the circuit, and the compensation capacitor C R The lower plate is switched to the common mode voltage V CM , the sampling capacitor Cs completes sampling, at which time the sampled thermal noise is collected on the upper plate of the sampling capacitor Cs. Before the second sampling time t2 arrives, the change in the input signal is coupled to the upper plate of the sampling capacitor Cs and offset by the compensation voltage, and the change in the input signal of the preamplifier 112 becomes smaller, thereby making the output signal of the preamplifier 112 within the output range.

[0093] 2) At the second sampling time t2, the signals that have been compensated and pre-amplified are sampled and stored.

[0094] Specifically, at the second sampling time t2, the second control signal The first switch K1, the tenth switch K10, the thirteenth switch K13, the fourth switch K4, the twelfth switch K12 and the fifteenth switch K15 are disconnected, and the upper plate of the noise elimination capacitor is connected from the common mode voltage V CM Disconnect, the input signal and sampled thermal noise are sampled and stored on the noise elimination capacitor. At this time, the noise elimination capacitor completes sampling.

[0095] 3) In the quantization stage, the sampling thermal noise stored at the output of the preamplifier 112 and the sampling thermal noise sampled at the input of the preamplifier 112 are offset by the preamplifier 112; the potential of the lower plate of the sampling capacitor is adjusted based on the successive approximation logic, thereby realizing analog-to-digital conversion.

[0096] Specifically, after the double sampling is completed, the third control signal It jumps to a high level, and the fourteenth switch K14 and the sixteenth switch K16 are turned on to achieve inter-electrode amplification; in this process, since the sampling thermal noise at the input end of the pre-amplifier 112 is in antiphase with the sampling thermal noise on the noise elimination capacitor, noise cancellation is achieved on the noise elimination capacitor.

[0097] The present invention also provides an electronic device, which includes the differential analog-to-digital converter 1 of the present invention, thereby achieving high-performance analog-to-digital conversion and meeting requirements such as accuracy, linearity, power consumption, and conversion speed. The electronic device is applicable to the fields of audio processing, video processing, medical equipment, industrial automation, consumer electronics, automotive electronics, and energy management, and will not be described in detail here.

[0098] In summary, the present invention provides a differential analog-to-digital converter, a conversion method and an electronic device, including: an analog-to-digital conversion module, a first compensation module and a second compensation module; the analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of a differential input signal; the analog-to-digital conversion module includes a first switch, a first switch capacitor array, a second switch, a third switch, a first capacitor, a first resistor, a fourth switch, a second switch capacitor array, a fifth switch, a sixth switch, a second capacitor, a second resistor, a preamplifier and a quantization circuit; the lower plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input signal via the first switch, and is also connected to the positive phase reference voltage and the negative phase reference voltage through the corresponding switches respectively; the upper plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input terminal of the preamplifier; the two ends of the first resistor are connected to the positive phase input terminal and the positive phase output terminal of the preamplifier via the second switch and the third switch respectively; the lower plate of the sampling capacitor in the second switch capacitor array is connected to the negative phase reference voltage via the fourth switch phase input signal, and is also connected to the positive phase reference voltage and the negative phase reference voltage through corresponding switches respectively; the upper plate of the sampling capacitor in the second switch capacitor array is connected to the inverting input terminal of the preamplifier; the two ends of the second resistor are connected to the inverting input terminal and the inverting output terminal of the preamplifier via the fifth switch and the sixth switch respectively; the quantization circuit is connected to the output terminal of the preamplifier, and generates switch control signals of the first switch capacitor array and the second switch capacitor array; the input end of the first compensation module is connected to the inverting output terminal of the preamplifier, and the output end is connected to the positive phase input terminal of the preamplifier, and the change of the positive phase input signal coupled to the positive phase input terminal of the preamplifier is compensated; the input end of the second compensation module is connected to the positive phase output terminal of the preamplifier, and the output end is connected to the inverting input terminal of the preamplifier, and the change of the inverting input signal coupled to the inverting input terminal of the preamplifier is compensated; wherein, in the sampling stage, the first switch capacitor array, the second switch capacitor array, and the preamplifier are reused, and form a differential circuit with the first resistor and the second resistor. The differential analog-to-digital converter, conversion method and electronic device of the present invention adopt sampling thermal noise elimination technology, and form a differential circuit by multiplexing sampling capacitors and pre-amplifiers, so as to increase the signal bandwidth limited by the amplifier saturation problem by using a first-order approximate compensation module, and have the advantages of small sampling capacitors, low noise, small occupied area and large signal bandwidth. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A differential analog-to-digital converter, characterized in that: The differential analog-to-digital converter comprises at least: An analog-to-digital conversion module, a first compensation module and a second compensation module; The analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of a differential input signal; the analog-to-digital conversion module includes a first switch, a first switch capacitor array, a second switch, a third switch, a first capacitor, a first resistor, a fourth switch, a second switch capacitor array, a fifth switch, a sixth switch, a second capacitor, a second resistor, a preamplifier and a quantization circuit; the lower plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input signal via the first switch, and is also connected to the positive phase reference voltage and the negative phase reference voltage through the corresponding switches respectively; the upper plate of the sampling capacitor in the first switch capacitor array is connected to the positive phase input terminal of the preamplifier; both ends of the first resistor The positive phase input terminal and the positive phase output terminal of the preamplifier are connected via the second switch and the third switch respectively; the lower plate of the sampling capacitor in the second switch capacitor array is connected to the negative phase input signal via the fourth switch, and is also connected to the positive phase reference voltage and the negative phase reference voltage through corresponding switches respectively; the upper plate of the sampling capacitor in the second switch capacitor array is connected to the negative phase input terminal of the preamplifier; the two ends of the second resistor are connected to the negative phase input terminal and the negative phase output terminal of the preamplifier via the fifth switch and the sixth switch respectively; the quantization circuit is connected to the output terminal of the preamplifier, and generates switch control signals of the first switch capacitor array and the second switch capacitor array; The input end of the first compensation module is connected to the inverting output end of the pre-amplifier, and the output end is connected to the non-inverting input end of the pre-amplifier, so as to compensate for the change of the non-inverting input signal coupled to the non-inverting input end of the pre-amplifier; The input end of the second compensation module is connected to the non-phase output end of the pre-amplifier, and the output end is connected to the inverting input end of the pre-amplifier, so as to compensate for the change of the inverting input signal coupled to the inverting input end of the pre-amplifier; Before sampling, the first switch capacitor array, the second switch capacitor array, and the pre-amplifier are reused to form a differential circuit with the first resistor and the second resistor.

2. The differential analog-to-digital converter according to claim 1, characterized in that: The first compensation module and the second compensation module both include a seventh switch, an eighth switch and a compensation capacitor; One end of the seventh switch is connected to the corresponding output end of the pre-amplifier, and the other end is connected to the lower plate of the compensation capacitor; One end of the eighth switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor; The upper plate of the compensation capacitor is connected to the corresponding input terminal of the pre-amplifier; The sampling timing of the seventh switch is consistent with the sampling timing of the sampling capacitor in the analog-to-digital conversion module, and the on-off state of the eighth switch is opposite to that of the seventh switch.

3. The differential analog-to-digital converter according to claim 2, characterized in that: The differential analog-to-digital converter satisfies: Δt=R d ·C R ; Among them, Δt is the time difference between double sampling, R d is the resistance value of the first resistor and the second resistor, C R is the value of the compensation capacitor.

4. The differential analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The analog-to-digital conversion module is a SARADC structure.

5. The differential analog-to-digital converter according to claim 4, characterized in that: The quantization circuit includes a ninth switch, a first noise elimination capacitor, a tenth switch, an eleventh switch, a second noise elimination capacitor, a twelfth switch, a latch and a SAR logic unit; The lower plate of the first noise elimination capacitor is connected to the non-phase output terminal of the pre-amplifier via the ninth switch; one end of the tenth switch is connected to the upper plate of the first noise elimination capacitor, and the other end is connected to the common mode voltage; the lower plate of the second noise elimination capacitor is connected to the inverting output terminal of the pre-amplifier via the eleventh switch; One end of the twelfth switch is connected to the upper plate of the second noise elimination capacitor, and the other end is connected to the common mode voltage; The input end of the latch is connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor respectively; The SAR logic unit is connected to the output end of the latch, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on an output signal of the latch.

6. The differential analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The analog-to-digital conversion module is a Pipe-SAR ADC structure.

7. The differential analog-to-digital converter according to claim 6, characterized in that: The quantization circuit includes a ninth switch, a first noise elimination capacitor, a tenth switch, an eleventh switch, a second noise elimination capacitor, a twelfth switch, a comparator, a SAR logic unit, a post-amplifier, a thirteenth switch, a fourteenth switch, a first feedback capacitor, a fifteenth switch, a sixteenth switch, a second feedback capacitor and at least one SAR ADC unit; The lower plate of the first noise elimination capacitor is connected to the non-phase output terminal of the pre-amplifier via the ninth switch; one end of the tenth switch is connected to the upper plate of the first noise elimination capacitor, and the other end is connected to the common mode voltage; the lower plate of the second noise elimination capacitor is connected to the inverting output terminal of the pre-amplifier via the eleventh switch; One end of the twelfth switch is connected to the upper plate of the second noise elimination capacitor, and the other end is connected to the common mode voltage; The input end of the comparator is respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; The SAR logic unit is connected to the output end of the comparator, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on the output signal of the comparator; The input end of the post-stage amplifier is respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor, and forms a ring amplifier with the pre-amplifier; The lower plate of the first feedback capacitor is connected to the common mode voltage via the thirteenth switch, and is also connected to the first output end of the post-stage amplifier via the fourteenth switch; the upper plate of the first feedback capacitor is connected to the output end of the first switch capacitor array; the lower plate of the second feedback capacitor is connected to the common mode voltage via the fifteenth switch, and is also connected to the second output end of the post-stage amplifier via the sixteenth switch; the upper plate of the second feedback capacitor is connected to the output end of the second switch capacitor array; The SAR ADC units of each stage are cascaded in sequence to the output end of the post-stage amplifier.

8. The differential analog-to-digital converter according to claim 5 or 7, characterized in that: The quantization circuit also includes a seventeenth switch, an eighteenth switch, a third resistor and a fourth resistor; the third resistor is connected between the tenth switch and the common mode voltage, and the seventeenth switch is connected in parallel across the third resistor; the fourth resistor is connected between the twelfth switch and the common mode voltage, and the eighteenth switch is connected in parallel across the fourth resistor.

9. An analog-to-digital conversion method, implemented based on the differential analog-to-digital converter according to any one of claims 1 to 8, characterized in that: The analog-to-digital conversion method at least comprises: Differentiating the input signal to obtain a compensation voltage, collecting the input signal and the sampled thermal noise to the input end of the preamplifier at a first sampling moment, and simultaneously loading the compensation voltage to the input end of the preamplifier to compensate for the voltage change of the input signal coupled to the input end of the preamplifier; At the second sampling moment, sampling and storing the signals that have been compensated and pre-amplified in sequence; In the quantization stage, the sampling thermal noise stored at the output of the preamplifier and the sampling thermal noise sampled at the input of the preamplifier cancel each other out; the potential of the lower plate of the sampling capacitor is adjusted based on successive approximation logic, thereby achieving analog-to-digital conversion.

10. An electronic device, characterized in that: The electronic device comprises at least: a differential analog-to-digital converter as described in any one of claims 1-8.

Images