Self-aligned embedded gate metal MOSFET and manufacturing method

Abstract

The invention discloses a self-aligned embedded gate metal MOSFET and a manufacturing method, the self-aligned embedded gate metal MOSFET comprises a semiconductor layer arranged on a substrate, a body region and a drift region are sequentially arranged in the semiconductor layer from the surface to the substrate, and a source region located below the surface of the semiconductor layer is arranged in the body region; the pair of first side walls are arranged on the surface of the semiconductor layer above the source region; the trench gate is arranged in the semiconductor layer between the pair of first side walls and penetrates through the source region; the gate metal is embedded between the pair of first side walls and is connected with the trench gate; the source region contact groove is formed in the semiconductor layer on one side of the trench gate; the source region contact metal is filled in the source region contact groove and is connected with the source region; and the gate metal and the source region contact metal are respectively connected with the metal interconnection layer through the conductive contact holes. According to the invention, the conduction speed can be accelerated, the switching frequency can be increased, the area of the device can be reduced, the short-circuit resistance can be reduced and the performance of the device can be improved while the photomasks are reduced and the overlay error is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit technology, and in particular to a self-aligned buried gate metal MOSFET and a manufacturing method thereof. Background Art

[0002] Compared with planar MOSFET, trench MOSFET can provide a shorter current path between source and drain, thereby reducing on-resistance, allowing more current to flow through the switch, and significantly reducing power loss. Reducing the spacing between structures in MOSFET devices makes MOSFET devices have a smaller die area, which can further reduce the resistance per square area and increase the current density.

[0003] However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance also increases.

[0004] On the other hand, as the device area continues to shrink, when the voltage is turned on by directly connecting the tungsten contact hole to the polysilicon gate in the trench gate, it will become unreliable and the conduction speed will be reduced, that is, the switching frequency will be reduced. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a self-aligned buried gate metal MOSFET and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a self-aligned buried gate metal MOSFET, comprising:

[0008] A semiconductor layer disposed on a substrate, wherein a body region and a drift region are sequentially disposed in the semiconductor layer from the surface toward the substrate, and a source region located below the surface of the semiconductor layer is disposed in the body region;

[0009] A pair of first sidewall spacers disposed on the surface of the semiconductor layer above the source region;

[0010] A trench gate disposed in the semiconductor layer between a pair of the first sidewalls and passing through the source region;

[0011] A gate metal embedded between a pair of the first sidewalls and connected to the trench gate;

[0012] A source region contact trench provided in the semiconductor layer on one side of the trench gate, and a source region contact metal filled in the source region contact trench and connected to the source region;

[0013] The gate metal and the source region contact metal are respectively connected to the metal interconnection layer through conductive contact holes.

[0014] Furthermore, the trench gate is provided with a polysilicon gate, and the polysilicon gate is connected to the gate metal.

[0015] Furthermore, the bottom of the trench gate also passes through the body region and is located in the drift region.

[0016] Furthermore, the bottom of the source contact trench is located in the body region, a transition connection portion is provided in the semiconductor layer along the wall of the source contact trench, and the source contact metal is also connected to the source region and the body region through the transition connection portion.

[0017] Furthermore, a plurality of the source regions and the source region contact grooves are alternately connected and arranged along the surface of the semiconductor layer, a pair of the first side walls are provided on the surface of the semiconductor layer above each source region, the gate metal and the trench gate are provided between each pair of the first side walls, and the source region contact metal is buried between two adjacent pairs of the first side walls and fills the source region contact groove.

[0018] The present invention also provides a method for manufacturing a self-aligned buried gate metal MOSFET, comprising:

[0019] providing a substrate, and forming a semiconductor layer on a surface of the substrate;

[0020] forming a drift region in the semiconductor layer, and forming a body region located on the drift region below a surface of the semiconductor layer;

[0021] forming a source region in the body region below a surface of the semiconductor layer;

[0022] forming a pair of first spacers on the surface of the semiconductor layer above the source region;

[0023] forming a trench gate passing through the source region in the semiconductor layer between a pair of the first spacers;

[0024] forming a gate metal buried between a pair of the first sidewalls and connected to the trench gate;

[0025] forming a source region contact trench in the semiconductor layer on one side of the trench gate;

[0026] forming a source region contact metal filled in the source region contact trench and connected to the source region;

[0027] forming an interlayer dielectric layer on top surfaces of the first sidewall spacer, the gate metal, and the source region contact metal;

[0028] Forming a conductive contact hole in the interlayer dielectric layer, the bottom of which is respectively connected to the gate metal and the source region contact metal;

[0029] A metal interconnection layer connected to the top of the conductive contact hole is formed on the interlayer dielectric layer.

[0030] Further, forming a source region located in the body region below the surface of the semiconductor layer specifically includes:

[0031] forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer;

[0032] Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns located on adjacent sides;

[0033] Forming a third hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and performing back etching to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides, and exposing the tops of the first hard mask layer pattern and the second hard mask layer pattern;

[0034] removing the second hard mask layer pattern, and forming an injection window between the first hard mask layer pattern and the third hard mask layer pattern;

[0035] A source region located in the body region is formed below the surface of the semiconductor layer below the implantation window through the implantation window and by adopting a multi-directional ion implantation process.

[0036] Further, forming a pair of first sidewalls on the surface of the semiconductor layer above the source region, forming a trench gate passing through the source region in the semiconductor layer between the pair of first sidewalls, and forming a gate metal buried between the pair of first sidewalls and connected to the trench gate, specifically includes:

[0037] Forming first sidewall spacers on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively, so as to form a pair of first sidewall spacers formed by two adjacent first sidewall spacers on the surface of the semiconductor layer above the source region, and expose the surface of the semiconductor layer between the pair of first sidewall spacers;

[0038] Using the first hard mask layer pattern and the first sidewalls on both sides thereof and the third hard mask layer pattern and the first sidewalls on both sides thereof as a common mask, a gate trench penetrating the source region is formed downward on the surface of the semiconductor layer between a pair of the first sidewalls;

[0039] Forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer, thereby forming a trench gate;

[0040] A first metal is filled between the pair of first sidewalls, and is etched back to form a gate metal buried between the pair of first sidewalls and connected to the trench gate.

[0041] Furthermore, forming a source region contact trench in the semiconductor layer on one side of the trench gate, and forming a source region contact metal filled in the source region contact trench and connected to the source region, specifically includes:

[0042] Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back;

[0043] Using the gate metal and the first sidewalls on both sides thereof as a common mask, a source region contact trench is formed downward on the surface of the semiconductor layer exposed between two adjacent first sidewalls, so that the sidewall of the source region contact trench is in contact with the source region, and the bottom of the source region contact trench is located in the body region;

[0044] Filling a second metal between two adjacent first sidewalls, and removing excess second metal other than the tops of the two adjacent first sidewalls to expose the top of the gate metal, forming a source region contact metal buried between the two adjacent first sidewalls and filled in the source region contact trench and connected to the source region;

[0045] Or include:

[0046] Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back;

[0047] forming a second side wall on the outer sides of the pair of first side walls;

[0048] Using the gate metal and the first sidewalls and the second sidewalls on both sides thereof as a common mask, a source region contact trench is formed downward on the surface of the semiconductor layer exposed between two second sidewalls on adjacent sides, so that the sidewall of the source region contact trench is in contact with the source region, and the bottom of the source region contact trench is located in the body region;

[0049] The second sidewall is removed, and then the second metal is filled between the two first sidewalls on the adjacent sides, and the excess second metal except the top of the two first sidewalls on the adjacent sides is removed to expose the top of the gate metal, thereby forming the source region contact metal buried between the two first sidewalls on the adjacent sides and filled in the source region contact groove and connected to the source region.

[0050] Furthermore, after the source region contact groove is formed, a transition connection portion is first formed in the semiconductor layer along the wall of the source region contact groove by ion implantation, and then the source region contact metal filled in the source region contact groove is formed, so that the source region contact metal is connected to the source region and the body region through the transition connection portion.

[0051] It can be seen from the above technical scheme that the present invention forms a gate metal connected to the trench gate on the trench gate, so that the gate (for example, a polysilicon gate) in the trench gate can be connected to the conductive contact hole through the gate metal, so that the voltage conducted from the conductive contact hole can be reliably conducted to the trench gate through the gate metal, thereby effectively reducing the contact resistance between the trench gate and the conductive contact hole, and improving the reliability of voltage conduction between the conductive contact hole and the trench gate, thereby accelerating the conduction speed, that is, increasing the switching frequency, thereby effectively solving the problem of reduced conduction speed, that is, reduced switching frequency, when the existing method of directly connecting the tungsten contact hole and the polysilicon gate in the trench gate is used to conduct voltage. Furthermore, by forming a pair of first sidewalls in self-alignment above the source region, a trench gate self-aligned with the source region can be formed in the semiconductor layer between the pair of first sidewalls, and a source region contact trench and source region contact metal self-aligned with the trench gate can be formed on one side of the pair of first sidewalls (trench gates), so that not only can the spacing between structures in the MOSFET device be reduced while reducing the mask, so that the MOSFET device has a smaller tube core area, the resistance per square area can be further reduced, and the current density can be increased, and the overlay error can be eliminated, thereby effectively reducing the short-circuit resistance. Further, by forming a second sidewall on the outside of the first sidewall to adjust the size of the source region contact trench, not only can the size of the source region located between the source region contact trench and the trench gate be adjusted, but also after removing the second sidewall, the filled source region contact metal can be connected to the source region from the top and side of the source region, thereby increasing the contact area, thereby meeting the requirements of good source region ohmic contact and current carrying capacity, thereby further improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of the structure of a self-aligned buried gate metal MOSFET according to a preferred embodiment of the present invention;

[0053] Figure 2-Figure 9 The figure is a process flow chart of a method for manufacturing a self-aligned buried gate metal MOSFET according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0055] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0056] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type may be formed by injecting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by injecting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0057] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0058] refer to Figure 1 The self-aligned buried gate metal MOSFET of the present invention comprises, from bottom to top, a substrate 10, a semiconductor layer 23, a metal layer, an interlayer dielectric layer 20 (ILD) and a metal interconnection layer 19.

[0059] The following description is made by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example.

[0060] The substrate 10 may be a heavily doped N+ type silicon substrate 10 (N+ substrate).

[0061] The semiconductor layer 23 may be an epitaxial silicon semiconductor layer 23 disposed on the surface of the substrate 10. A drift region 11 (drift) and a body region 12 are disposed in the semiconductor layer 23. The body region 12 is located above the drift region 11 and below the surface of the semiconductor layer 23 away from the substrate 10. The body region 12 may be a lightly doped P-type body region 12 (P-body), and the drift region 11 may be an epitaxial N-type drift region 11 (N drift EPI).

[0062] A source region 24 is disposed in the body region 12; the source region 24 is located below the surface of the semiconductor layer 23. The source region 24 may be a heavily doped N+ type source region 24.

[0063] The metal layer is provided with a gate metal 21 and a source contact metal 15. The gate metal 21 and the source contact metal 15 are isolated by a first spacer 22.

[0064] The first sidewall spacer 22 includes a pair of first sidewall spacers 22 correspondingly disposed on the surface of the semiconductor layer 23 above the source region 24. The first sidewall spacers 22 can be vertically disposed on the surface of the semiconductor layer 23 and at a certain distance, and the distance should ensure that the pair of first sidewall spacers 22 are both located above the same source region 24. The first sidewall spacers 22 can be formed of a dielectric material.

[0065] A trench gate 28 is disposed in the semiconductor layer 23 between the pair of first spacers 22 ; the trench gate 28 is disposed through the source region 24 . The size of the trench gate 28 is determined by the distance between the pair of first spacers 22 .

[0066] A gate metal 21 is embedded in the gap between the pair of first spacers 22 ; the bottom of the gate metal 21 is ohmically connected to the top of the trench gate 28 .

[0067] A source contact trench 14 is provided in the semiconductor layer 23 on one side of the trench gate 28; the opening of the source contact trench 14 is located on the surface of the semiconductor layer 23. The source contact trench 14 is filled with a source contact metal 15; the source contact metal 15 is ohmically connected to the source region 24 through the groove wall of the source contact trench 14.

[0068] The interlayer dielectric layer 20 and the metal interconnection layer 19 are sequentially arranged on the metal layer. A plurality of conductive contact holes 16 are arranged in the interlayer dielectric layer 20; the bottom of the conductive contact hole 16 is ohmically connected to the top of the gate metal 21 and the top of the source contact metal 15 respectively, and the top of the conductive contact hole 16 is ohmically connected to the metal interconnection layer 19, so that the trench gate 28 is interconnected with the metal interconnection layer 19 through the gate metal 21 and the conductive contact hole 16, and the source region 24 is interconnected with the metal interconnection layer 19 through the source contact metal 15 and the conductive contact hole 16.

[0069] refer to Figure 1 In some embodiments, a trench gate 28 is formed in the gate trench 25. A heavily doped N+ type polysilicon gate 26 (poly 1) is provided in the gate trench 25; the top of the polysilicon gate 26 is ohmically connected to the bottom of the gate metal 21. A gate oxide layer 27 is provided between the inner wall of the gate trench 25 and the polysilicon gate 26; the polysilicon gate 26 is isolated from the source region 24 by the gate oxide layer 27.

[0070] In some embodiments, the bottom of the trench gate 28 is located in the drift region 11 through the body region 12 .

[0071] The top of the trench gate 28 may be protruded from the surface of the semiconductor layer 23 .

[0072] In some embodiments, the bottom of the source contact groove 14 is located in the body region 12, and the sidewall of the source contact groove 14 is connected to the side (end face) of the source region 24. A transition connection portion 13 is also provided in the semiconductor layer 23 along the groove wall of the source contact groove 14; the source contact metal 15 also forms an ohmic connection with the source region 24 and the body region 12 through the transition connection portion 13. The transition connection portion 13 can be a heavily doped P+ type transition connection portion 13. The bottom of the transition connection portion 13 is located in the body region 12.

[0073] In some embodiments, a pair of first sidewalls 22 are located within the two sides (ends) of the source region 24, and the source region contact metal 15 is connected to the source region 24 at the top and side of the source region 24 outside the pair of first sidewalls 22 to increase the contact area with the source region 24.

[0074] In some embodiments, the gate metal 21 material and / or the source contact metal 15 includes at least one of Au, Ag, Pt, Al, and W.

[0075] Adhesion layers (not shown) may be provided respectively between the gate metal 21 and the first spacer 22 and the top of the trench gate 28, and between the source contact metal 15 and the first spacer 22 (including the top of the source region 24 outside the pair of first spacers 22) and the groove wall of the source contact groove 14. The adhesion layer material includes at least one of Ti, TiN, and TaN.

[0076] In some embodiments, the conductive contact hole 16 may be a tungsten contact hole.

[0077] refer to Figure 1 In some embodiments, the source regions 24 and the source region contact grooves 14 are alternately connected and arranged in a plurality of ways along the surface of the semiconductor layer 23 ( Figure 1 2 source regions 24 and 3 source region contact trenches 14 are exemplarily shown in the figure. A pair of first sidewalls 22 are provided on the surface of the semiconductor layer 23 above each source region 24, and a gate metal 21 and a trench gate 28 are provided between each pair of first sidewalls 22; the source region contact metal 15 is embedded in the gap between two adjacent pairs of first sidewalls 22 and fills the source region contact trench 14.

[0078] It can be seen that each trench gate 28 is self-aligned and penetrates a corresponding source region 24 through a pair of first sidewalls 22 formed above the source region 24; the gate metal 21 is filled between the pair of first sidewalls 22 and self-aligned and connected to the trench gate 28 below to form a buried gate metal 21. The source region contact trench 14 is self-aligned between two adjacent trench gates 28 through two adjacent pairs of first sidewalls 22, and each source region contact trench 14 is simultaneously connected to the sides of the two source regions 24 on both sides.

[0079] In some embodiments, a dielectric passivation layer 17 is disposed on the metal interconnection layer 19 ; a pad window 18 (for forming a pad) connected to the metal interconnection layer 19 is disposed on the surface of the passivation layer 17 .

[0080] A method for manufacturing a self-aligned buried gate metal MOSFET of the present invention is described in detail below through specific implementations and in conjunction with the accompanying drawings.

[0081] refer to Figure 2-Figure 9 The self-aligned buried gate metal MOSFET manufacturing method of the present invention can be used to manufacture the above-mentioned Figure 1 A self-aligned buried gate metal MOSFET of the present invention may include the following steps:

[0082] Step S1 : providing a substrate 10 , and forming a semiconductor layer 23 on a surface of the substrate 10 .

[0083] like Figure 2 As shown, a heavily doped N+ type silicon substrate 10 (N+ substrate) may be used, and an epitaxial silicon semiconductor layer 23 may be formed on the silicon substrate 10 .

[0084] Step S2 : forming a drift region 11 in the semiconductor layer 23 , and forming a body region 12 located on the drift region 11 below the surface of the semiconductor layer 23 .

[0085] like Figure 2As shown, when forming the epitaxial silicon semiconductor layer 23, a doping process can be used to form an N-type epitaxial silicon semiconductor layer 23. After forming the N-type epitaxial silicon semiconductor layer 23, an ion implantation process can be used to form a lightly doped P-type body region 12 (P-body) below the surface of the semiconductor layer 23. In this way, an epitaxial N-type drift region 11 (N drift EPI) is formed in the N-type semiconductor layer 23 below the body region 12. In other words, the body region 12 is formed in the drift region 11 and is located below the surface of the semiconductor layer 23.

[0086] Step S3 : forming a source region 24 located in the body region 12 below the surface of the semiconductor layer 23 .

[0087] like Figure 2 As shown, a first hard mask layer material may be deposited on the surface of the semiconductor layer 23. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 29 (HM1) are formed on the surface of the semiconductor layer 23 by photolithography and etching. Figure 2 FIG. 2 exemplarily shows that two first hard mask layer patterns 29 are formed, but the present invention is not limited thereto. Afterwards, the photoresist remaining on the first hard mask layer patterns 29 is removed.

[0088] The first hard mask layer material may be a conventional hard mask layer material, for example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0089] like Figure 3 As shown, a conformal CVD process can be used to form a second hard mask layer on the surface of the semiconductor layer 23 to cover the first hard mask layer pattern 29. Then, the second hard mask layer is etched back to form a second hard mask layer pattern 30 (HM2) on both sides of each first hard mask layer pattern 29, and to expose the top of the first hard mask layer pattern 29 and the surface of the semiconductor layer 23 between the two second hard mask layer patterns 30 located on the adjacent sides (i.e., the two second hard mask layer patterns 30 located on the inner sides of the two adjacent first hard mask layer patterns 29).

[0090] When the second hard mask layer is deposited, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0091] The second hard mask layer material may be a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0092] like Figure 3As shown, a deposition process may be used to form a third hard mask layer on the surface of the semiconductor layer 23, covering the first hard mask layer pattern 29 and the second hard mask layer pattern 30, and completely filling the gap between the two second hard mask layer patterns 30 on the adjacent sides. Then, the third hard mask layer material may be etched back to form a third hard mask layer pattern 31 (HM3) between the two second hard mask layer patterns 30 on the adjacent sides, and expose the tops of the first hard mask layer pattern 29 and the second hard mask layer pattern 30.

[0093] By conformally forming a second hard mask layer on the first hard mask layer pattern 29 and back-etching to form a second hard mask layer pattern 30 on both sides of the first hard mask layer pattern 29, a third hard mask layer pattern 31 can be self-aligned between the second hard mask layer patterns 30, thereby achieving a reduction in pitch while saving one photomask.

[0094] The third hard mask layer material may be a conventional hard mask layer material, for example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0095] like Figure 4 As shown, then, the second hard mask layer pattern 30 can be removed by utilizing different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material, exposing the surface of the semiconductor layer 23 located between the first hard mask layer pattern 29 and the third hard mask layer pattern 31, thereby forming a first injection window 32 between the first hard mask layer pattern 29 and the third hard mask layer pattern 31.

[0096] Then, through the first injection window 32, a multi-directional ion implantation process is adopted to form a heavily doped N+ type source region 24 located in the body region 12 below the surface of the semiconductor layer 23 below the first injection window 32. For example, by adopting an inclined implantation angle in the surrounding directions of the first injection window 32, a heavily doped N+ type source region 24 located in the body region 12 and having a boundary larger than the boundary of the first injection window 32 can be formed below the surface of the semiconductor layer 23 below the first injection window 32. Figure 4 FIG. 5 exemplarily shows that two source regions 24 are formed, but the present invention is not limited thereto.

[0097] Step S4 : forming a pair of first spacers 22 on the surface of the semiconductor layer 23 above the source region 24 .

[0098] like Figure 4As shown, next, a spacer process can be used to deposit a spacer material on the surface of the semiconductor layer 23 exposed between the first hard mask layer pattern 29, the third hard mask layer pattern 31, and each pattern, and then back-etching is performed to form a first spacer 22 (Spacer) structure on both sides of each first hard mask layer pattern 29 and each third hard mask layer pattern 31. The first spacers 22 located on two adjacent sides between the first hard mask layer pattern 29 and the third hard mask layer pattern 31 are simultaneously located on the surface of the semiconductor layer 23 above the same source region 24, forming a pair of first spacers 22.

[0099] When forming the first side wall 22, the horizontal width of the first side wall 22 formed by back etching can be adjusted by controlling the deposition thickness of the first side wall 22 material, so as to adjust the spacing between a pair of first side walls 22, that is, adjust the width of the surface of the semiconductor layer 23 exposed between a pair of first side walls 22, thereby achieving the adjustment of the horizontal width of the gate trench 25 formed by etching later.

[0100] The first spacer 22 material may be a conventional spacer material having different etching selectivity ratios with the first hard mask layer material and the third hard mask layer material.

[0101] Step S5 : forming a trench gate 28 passing through the source region 24 in the semiconductor layer 23 between the pair of first spacers 22 .

[0102] like Figure 5 As shown, next, using the first hard mask layer pattern 29 and the combined pattern of the first side walls 22 on both sides thereof and the combined pattern of the third hard mask layer pattern 31 and the first side walls 22 on both sides thereof as a common mask, etching is performed downward on the surface of the semiconductor layer 23 between a pair of first side walls 22 to form a gate trench 25 passing through the source region 24 in the semiconductor layer 23. Figure 5 2 shows two parallel gate trenches 25 formed through the source region 24 , and by etching, the bottom of the gate trench 25 is further passed through the body region 12 and is located in the drift region 11 below.

[0103] Then, a gate oxide layer 27 material is fully deposited on the inner wall surface of the gate trench 25 and on the exposed surfaces of the first side wall 22, the first hard mask layer pattern 29, and the third hard mask layer pattern 31, and further, a gate electrode 26 material is filled in the gate trench 25 within the gate oxide layer 27 material, until the gap between a pair of first side walls 22 is filled, so that the gate electrode 26 material covers the gate oxide layer 27 material.

[0104] Next, the gate 26 material and the gate oxide layer 27 material may be etched back to form a gate oxide layer 27 on the inner wall of the gate trench 25, and a gate 26 may be formed in the gate trench 25 within the gate oxide layer 27, thereby forming a trench gate 28. The formed gate 26 may be an N+ type polysilicon gate 26 (poly 1).

[0105] When etching back the gate 26 material and the gate oxide layer 27 material, the etching back time can be controlled so that the tops of the formed gate 26 and the gate oxide layer 27 protrude above the surface of the semiconductor layer 23 and are lower than the top of the first spacer 22 .

[0106] Step S6 : forming a gate metal 21 buried between a pair of first spacers 22 and connected to the trench gate 28 .

[0107] like Figure 6 As shown, then, a first adhesive layer (not shown) can be deposited on the exposed surfaces of the pair of first spacers 22 and the first hard mask layer pattern 29 and the third hard mask layer pattern 31 through a deposition process. Then, the first metal is continuously deposited on the first adhesive layer to fill the gap between the pair of first spacers 22 and fill the gap between the pair of first spacers 22 above the trench gate 28. Then, the first metal and the first adhesive layer are etched back or chemically mechanically polished (CMP) to remove the redundant first metal and the first adhesive layer on the top surfaces of the first spacers 22 and the first hard mask layer pattern 29 and the third hard mask layer pattern 31, thereby forming a gate metal 21 buried between the pair of first spacers 22 and connected to the trench gate 28.

[0108] The first metal (gate metal 21 ) includes at least one of Au, Ag, Pt, Al, and W.

[0109] The first adhesive layer material includes at least one of Ti, TiN, and TaN.

[0110] Step S7 : forming a source contact trench 14 in the semiconductor layer 23 on one side of the trench gate 28 .

[0111] like Figure 7 As shown, then, the first hard mask layer pattern 29 and the third hard mask layer pattern 31 are removed by back etching to expose the surface of the semiconductor layer 23 between the two first spacers 22 on the adjacent sides.

[0112] Then, a spacer process may be used to further form a second spacer 33 on the outer sides of the pair of first spacers 22 .

[0113] The second spacer 33 needs to be made of another spacer material having a different etching selectivity ratio with the first spacer 22 material.

[0114] Using the gate metal 21 and the first side walls 22 and the second side walls 33 on both sides thereof as a common mask, a source region contact groove 14 is formed by etching downward on the surface of the semiconductor layer 23 exposed between the two second side walls 33 on the adjacent sides, so that the side walls of the formed source region contact groove 14 are connected to the side surfaces of the source region 24, and the bottom of the source region contact groove 14 is located in the body region 12 between the two adjacent source regions 24.

[0115] When forming the second side wall 33, the horizontal width of the second side wall 33 formed by back etching can be adjusted by controlling the deposition thickness of the second side wall 33 material, so as to adjust the spacing between the two second side walls 33 on the adjacent sides, that is, adjust the width of the surface of the semiconductor layer 23 exposed between the two second side walls 33 on the adjacent sides, thereby achieving the adjustment of the horizontal width of the source region contact groove 14 formed by etching later.

[0116] After the source contact groove 14 is formed, ion implantation can be performed, and the gap between the two second sidewalls 33 on the adjacent sides is used as the second implantation window 34 to form a transition connection portion 13 in the semiconductor layer 23 along the wall of the source contact groove 14. P-type ion implantation can be performed, for example, by ion implantation of boron and boron difluoride (BF2), to implant the source contact groove 14 region, and perform rapid thermal annealing (RTA), so as to form a heavily doped P+ type transition connection portion 13 (P+imp) in the body region 12 within a certain area of ​​the semiconductor layer 23 along the wall of the source contact groove 14, so as to improve the dynamic reliability of the formed device.

[0117] Step S8 : forming a source contact metal 15 filling the source contact trench 14 and connecting the source region 24 .

[0118] like Figure 8 As shown, the second sidewall 33 can then be removed by etching back to expose the first sidewall 22. Then, a second adhesive layer (not shown) can be deposited on the exposed surfaces of the two first sidewalls 22 and the gate metal 21 on the adjacent sides, and on the exposed surface of the semiconductor layer 23 (i.e., the surfaces of the two sides of the source region 24 exposed after removing the second sidewall 33 and the groove wall of the source region contact groove 14) through a deposition process, and the second metal can be continuously deposited on the second adhesive layer to fill the gap between the two first sidewalls 22 on the adjacent sides, and fill the gap between the two first sidewalls 22 on the adjacent sides above the source region contact groove 14. Then, the second metal and the second adhesion layer are etched back or chemically mechanically polished (CMP) to remove the excess second metal and the second adhesion layer on the top surface of the first sidewall 22 and the gate metal 21, exposing the top of the first sidewall 22 and the gate metal 21, thereby forming a source contact metal 15 buried between the two first sidewalls 22 on the adjacent sides, filling the source contact groove 14 and connecting the source region 24 and the body region 12 through the transition connection portion 13.

[0119] In other embodiments, the second sidewall 33 may not be formed. Instead, after the first hard mask layer pattern 29 and the third hard mask layer pattern 31 are removed by back etching, the gate metal 21 and the first sidewalls 22 on both sides thereof are directly used as a common mask to etch downward on the surface of the semiconductor layer 23 exposed between the two first sidewalls 22 on the adjacent sides to form a source region contact groove 14, so that the sidewall of the source region contact groove 14 is connected to the source region 24, and the bottom of the source region contact groove 14 is located in the body region 12. Afterwards, the aforementioned method may be used to form a heavily doped P+ type transition connection portion 13, and to form a source region contact metal 15 buried between the two first sidewalls 22 on the adjacent sides, filled in the source region contact groove 14, and connecting the source region 24 and the body region 12 through the transition connection portion 13. When this method is used, the sizes of the first hard mask layer pattern 29 and the third hard mask layer pattern 31 need to be controlled respectively, so the process requirements are relatively strict.

[0120] Step S9 : forming an interlayer dielectric layer 20 on the top surfaces of the first spacer 22 , the gate metal 21 and the source contact metal 15 .

[0121] like Figure 8 As shown, then, an interlayer dielectric layer 20 (ILD) may be formed on the top surfaces of the first spacer 22, the gate metal 21 and the source contact metal 15 by a deposition process. The interlayer dielectric layer 20 may be made of conventional interlayer dielectric materials.

[0122] Step S10: forming a conductive contact hole 16 in the interlayer dielectric layer 20, the bottom of which is respectively connected to the gate metal 21 and the source contact metal 15.

[0123] like Fig. 9 As shown, then, a contact hole can be formed in the interlayer dielectric layer 20 by photolithography and etching processes, and the bottom of the contact hole is respectively located on the top surface of the gate metal 21 and the source contact metal 15. Then, by performing a planarization process of filling the contact hole metal and removing the redundant contact hole metal, a conductive contact hole 16 whose bottom is respectively connected to the gate metal 21 and the source contact metal 15 is formed in the interlayer dielectric layer 20. For example, the tungsten conductive contact hole 16 can be formed by filling the contact hole with tungsten and planarizing it.

[0124] Step S11 : forming a metal interconnection layer 19 on the interlayer dielectric layer 20 and connected to the top of the conductive contact hole 16 .

[0125] like Fig. 9 As shown, then, a metal interconnection layer 19 connected to the top of the conductive contact hole 16 can be formed on the surface of the interlayer dielectric layer 20 through an interconnection process.

[0126] Finally, a dielectric passivation layer 17 (Passivation) can be formed on the metal interconnection layer 19 through a deposition process, and a pad window 18 connected to the metal interconnection layer 19 can be formed on the surface of the passivation layer 17 through a photolithography and etching process, and the pad window 18 can be filled with pad metal and planarized to form a pad (not shown).

[0127] In summary, the present invention forms a gate metal 21 connected to the trench gate 28 on the trench gate 28, so that the gate 26 (for example, the polysilicon gate 26) in the trench gate 28 can be connected to the conductive contact hole 16 through the gate metal 21, so that the voltage conducted by the conductive contact hole 16 can be reliably conducted to the trench gate 28 through the gate metal 21, thereby effectively reducing the contact resistance between the trench gate 28 (polysilicon gate 26) and the conductive contact hole 16, and improving the reliability of voltage conduction between the conductive contact hole 16 and the trench gate 28, so as to speed up the conduction speed, that is, increase the switching frequency, thereby effectively solving the problem that when the existing tungsten contact hole is directly connected to the polysilicon gate in the trench gate to conduct the voltage, the conduction speed is easily reduced, that is, the switching frequency is reduced. Furthermore, by forming a pair of first side walls 22 in a self-aligned manner above the source region 24, a trench gate 28 self-aligned with the source region 24 can be formed in the semiconductor layer 23 between the pair of first side walls 22, and a source region contact trench 14 and a source region contact metal 15 self-aligned with the trench gate 28 can be formed on one side of the pair of first side walls 22 (trench gate 28). Therefore, it is possible to reduce the mask while reducing the spacing between structures in the MOSFET device, so that the MOSFET device has a smaller die area, further reduce the resistance per square area, increase the current density, and eliminate the overlay error, thereby effectively reducing the short-circuit resistance. Furthermore, a second side wall 33 can be formed on the outer side of the first side wall 22 to adjust the size of the source contact groove 14 (including the injection size of the transition connection portion 13). Not only can the size of the source region 24 located between the source contact groove 14 and the trench gate 28 be adjusted, but also after removing the second side wall 33, the filled source contact metal 15 can be connected to the source region 24 from the top and side of the source region 24, thereby increasing the contact area, thereby meeting the requirements of good source region ohmic contact and current carrying capacity, thereby further improving the device performance.

[0128] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A self-aligned buried gate metal MOSFET, characterized in that: include: A semiconductor layer disposed on a substrate, wherein a body region and a drift region are sequentially disposed in the semiconductor layer from the surface toward the substrate, and a source region located below the surface of the semiconductor layer is disposed in the body region; A pair of first sidewall spacers disposed on the surface of the semiconductor layer above the source region; A trench gate disposed in the semiconductor layer between a pair of the first sidewalls and passing through the source region; A gate metal embedded between a pair of the first sidewalls and connected to the trench gate; A source region contact trench provided in the semiconductor layer on one side of the trench gate, and a source region contact metal filled in the source region contact trench and connected to the source region; The gate metal and the source region contact metal are respectively connected to the metal interconnection layer through conductive contact holes.

2. The self-aligned buried gate metal MOSFET according to claim 1, characterized in that The trench gate is provided with a polysilicon gate, and the polysilicon gate is connected to the gate metal.

3. The self-aligned buried gate metal MOSFET according to claim 1, characterized in that: The bottom of the trench gate also passes through the body region and is located in the drift region.

4. The self-aligned buried gate metal MOSFET according to claim 1, characterized in that: The bottom of the source contact groove is located in the body region, and a transition connection portion is provided in the semiconductor layer along the wall of the source contact groove. The source contact metal is also connected to the source region and the body region through the transition connection portion.

5. The self-aligned buried gate metal MOSFET according to claim 1, characterized in that: The source regions and the source region contact grooves are arranged alternately and connectedly along the surface of the semiconductor layer, a pair of the first side walls are provided on the surface of the semiconductor layer above each source region, the gate metal and the trench gate are provided between each pair of the first side walls, and the source region contact metal is buried between two adjacent pairs of the first side walls and fills the source region contact groove.

6. A method for manufacturing a self-aligned buried gate metal MOSFET, characterized in that: include: providing a substrate, and forming a semiconductor layer on a surface of the substrate; forming a drift region in the semiconductor layer, and forming a body region located on the drift region below a surface of the semiconductor layer; forming a source region in the body region below a surface of the semiconductor layer; forming a pair of first spacers on the surface of the semiconductor layer above the source region; forming a trench gate passing through the source region in the semiconductor layer between a pair of the first spacers; forming a gate metal buried between a pair of the first sidewalls and connected to the trench gate; forming a source region contact trench in the semiconductor layer on one side of the trench gate; forming a source region contact metal filled in the source region contact trench and connected to the source region; forming an interlayer dielectric layer on top surfaces of the first sidewall spacer, the gate metal, and the source region contact metal; Forming a conductive contact hole in the interlayer dielectric layer, the bottom of which is respectively connected to the gate metal and the source region contact metal; A metal interconnection layer connected to the top of the conductive contact hole is formed on the interlayer dielectric layer.

7. The method for manufacturing a self-aligned buried gate metal MOSFET according to claim 6, characterized in that: The step of forming a source region in the body region below the surface of the semiconductor layer specifically includes: forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer; Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns located on adjacent sides; Forming a third hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and performing back etching to form a third hard mask layer pattern between two second hard mask layer patterns located on adjacent sides, and exposing the tops of the first hard mask layer pattern and the second hard mask layer pattern; removing the second hard mask layer pattern, and forming an injection window between the first hard mask layer pattern and the third hard mask layer pattern; A source region located in the body region is formed below the surface of the semiconductor layer below the implantation window through the implantation window and by adopting a multi-directional ion implantation process.

8. The method for manufacturing a self-aligned buried gate metal MOSFET according to claim 7, characterized in that: The step of forming a pair of first sidewalls on the surface of the semiconductor layer above the source region, forming a trench gate passing through the source region in the semiconductor layer between the pair of first sidewalls, and forming a gate metal buried between the pair of first sidewalls and connected to the trench gate specifically includes: Forming first sidewall spacers on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively, so as to form a pair of first sidewall spacers formed by two adjacent first sidewall spacers on the surface of the semiconductor layer above the source region, and expose the surface of the semiconductor layer between the pair of first sidewall spacers; Using the first hard mask layer pattern and the first sidewalls on both sides thereof and the third hard mask layer pattern and the first sidewalls on both sides thereof as a common mask, a gate trench penetrating the source region is formed downward on the surface of the semiconductor layer between a pair of the first sidewalls; Forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer, thereby forming a trench gate; A first metal is filled between the pair of first sidewalls, and is etched back to form a gate metal buried between the pair of first sidewalls and connected to the trench gate.

9. The method for manufacturing a self-aligned buried gate metal MOSFET according to claim 8, characterized in that: The forming of a source region contact trench in the semiconductor layer on one side of the trench gate and the forming of a source region contact metal filled in the source region contact trench and connected to the source region specifically include: Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back; Using the gate metal and the first sidewalls on both sides thereof as a common mask, a source region contact trench is formed downward on the surface of the semiconductor layer exposed between two adjacent first sidewalls, so that the sidewall of the source region contact trench is in contact with the source region, and the bottom of the source region contact trench is located in the body region; Filling a second metal between two adjacent first sidewalls, and removing excess second metal other than the tops of the two adjacent first sidewalls to expose the top of the gate metal, forming a source region contact metal buried between the two adjacent first sidewalls and filled in the source region contact trench and connected to the source region; Or include: Removing the first hard mask layer pattern and the third hard mask layer pattern by etching back; forming a second side wall on the outer sides of the pair of first side walls; Using the gate metal and the first sidewalls and the second sidewalls on both sides thereof as a common mask, a source region contact trench is formed downward on the surface of the semiconductor layer exposed between two second sidewalls on adjacent sides, so that the sidewall of the source region contact trench is in contact with the source region, and the bottom of the source region contact trench is located in the body region; The second sidewall is removed, and then the second metal is filled between the two first sidewalls on the adjacent sides, and the excess second metal except the top of the two first sidewalls on the adjacent sides is removed to expose the top of the gate metal, thereby forming the source region contact metal buried between the two first sidewalls on the adjacent sides and filled in the source region contact groove and connected to the source region.

10. The method for manufacturing a self-aligned buried gate metal MOSFET according to claim 9, characterized in that: After the source region contact groove is formed, a transition connection portion is first formed in the semiconductor layer along the wall of the source region contact groove by ion implantation, and then the source region contact metal filled in the source region contact groove is formed, so that the source region contact metal is connected to the source region and the body region through the transition connection portion.

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