Clock tree adaptive optimization method using useful deviation based on RISC-V architecture

Abstract

The invention discloses a novel clock tree adaptive optimization method using useful deviation based on an RISC-V architecture. The method comprises the following steps: S1, layout; s2, layout is carried out; s3, after the clock tree is synthesized, S10, optimizing a time sequence path between registers; and S20, optimizing a time sequence path from the register to the memory after wiring in the step S4. According to the invention, through adaptive iteration, a tedious algorithm is not needed, the defect of auto use skew of an EDA tool is overcome, the time sequence problem is repaired to the maximum extent, and meanwhile, a delay unit merging method is adopted, so that the win-win effect of high performance and low power consumption of chip design is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of IC design and relates to a novel clock tree adaptive optimization method based on RISC-V architecture and utilizing useful deviation. Background Art

[0002] With the advancement of semiconductor process design, the scale and integration of chips have significantly increased, the market's requirements for chip performance have become higher and higher, and the clock structure inside the chip has become more complex. Therefore, the timing convergence of the design has become a huge challenge for engineers. The clock network occupies a significant position in the power consumption increment, usually accounting for 15%-40% of the power consumption of the whole chip. The quality of the clock tree has a significant impact on the power efficiency and performance of the processor. Traditional optimization strategies may no longer be able to meet the timing requirements of the design, which makes the optimization of the clock tree through new optimization methods in the chip design process an important link that cannot be ignored. At the same time, with the increase in integration, the cost and cost of chip tape-out have increased rapidly, and cost has become an increasingly important consideration in the chip design process.

[0003] In digital IC design, ideally, the clock reaches all timing units at the same time, resulting in a "zero-skew" clock tree. But in reality, due to different distances, the clock reaches different timing units with different clock delays. In order to obtain a reasonable clock tree structure, it is necessary to minimize the delay difference of the clock signal reaching each unit as much as possible while arriving at the same time. In today's VLSI, how to design a reasonable clock network is a question worth considering.

[0004] A synchronous sequential circuit model contains two sequential units, where A is the launch register, B is the capture register, P is the combinational logic delay of the sequential path, and L and C represent the delay of the clock signal reaching registers A and B respectively. Assuming the clock cycle is T, the delay of the combinational logic is Tc, the internal delay of the sequential unit is Tclk-q, and the clock skew of the two clock paths is Tskew = |LC|. Before and after the signal jump,

[0005] To meet the setup time constraint, Tsetup needs to satisfy the following formula: Tclk-q+Tc <T+Tskew-Tsetup

[0006] To meet the hold time constraint, Thold needs to satisfy the following formula: Tclk-q+Tc>Tskew+Thold

[0007] When there are setup and hold time violations on a timing path, they can be fixed by adjusting the clock skew. Useful skew refers to the difference in clock delays that allows certain registers to meet timing requirements. If the preceding and following paths of a register meet the timing requirements and there is a timing margin, these timing margins can be used to fix the violating paths by adjusting the positions of certain registers on the clock path (forward or backward), thereby improving overall timing convergence. For example, when a path has a setup time violation, and the subsequent path of the path has a timing margin on the setup time constraint, the network delay from the clock source to the register between adjacent paths can be adjusted without affecting the clock tree function, creating clock skew to fix the timing violation.

[0008] With the development of Moore's Law, the process of integrated circuits is becoming more and more advanced, but for integrated circuit design engineers, the cost of tape-out is getting higher and higher. Therefore, in order to allow the chip to be tape-out normally and save costs, it is particularly important to reduce power consumption while meeting performance requirements. Using the useful deviation method to fix timing violations will greatly increase the number of buffers used, and most buffers use low-voltage transistors (LVT), which will cause a sharp increase in power consumption and increase costs. Therefore, in order to meet the market's dual demands for high chip performance and low power consumption, it is extremely critical to consider the rationality of the timing convergence solution and the subsequent joint optimization measures for power consumption and performance.

[0009] The prior art proposes a useful deviation execution method of bidirectional timing continuous borrowing, which simultaneously considers the timing margins of the previous and next paths of the critical path with timing violations, and borrows the timing margins from the previous and next paths when correcting the timing violations of the critical path, thereby accelerating the convergence of timing. In addition, when the timing margins of the previous and next level paths are insufficient, this solution can also continuously borrow the timing margins of the previous and next multi-level paths, thereby making full use of the timing margins in the integrated circuit design, reducing the iteration time and the strong dependence of the back-end staff on the EDA tools, and greatly improving the efficiency of timing convergence.

[0010] The prior art has at least the following disadvantages:

[0011] 1. Existing methods do not repair timing violations to the maximum extent;

[0012] 2. The existing relatively close method uses the traditional method of repairing the timing with useful deviation. In order to solve the problem that the current useful deviation function does not fully borrow the timing margin, resulting in the inability to correct the critical path timing, the method of borrowing the timing step by step is adopted. However, from the formula of the setup time and hold time constraints, it can be seen that while borrowing the timing step by step forward and backward to repair the setup time violation, the adjustment of the clock deviation to make the setup time constraint meet the requirements often causes the hold time violation. After discovering the hold time violation, the EDA tool usually takes measures such as replacing the delay unit on the path, which will cause the clock path length to deviate from the expected target;

[0013] 3. The existing solution is to borrow timing step by step forward and backward, but in practice, the effect of applying early useful skew is not always ideal. The use of early useful skew is expected to reduce the clock network delay, but in reality it will increase. This is because the early useful skew is specified to achieve the goal, but in order to ensure the normal operation of the chip function, the clock path is difficult to advance. Therefore, the EDA tool may introduce additional delays on the clock path and extend the total length of the clock tree to meet the early useful skew requirement. Assuming that the total length of the clock tree is 500ps, optimizing the target path requires an early useful skew of 100ps, and the length of the clock path is close to the limit, and the clock path cannot be made smaller. At this time, the tool will increase the total length of the clock tree to 600ps to meet the demand, and the network delay of the clock tree will increase, and the timing loss cost caused by process variation (on chip variation, OCV) will increase;

[0014] 4. The existing design only addresses the violation problem between registers. However, in a design, the timing path between registers and memory may also have hold time violation problems. Moreover, the tool will introduce a large number of buffers on the timing path to fix the violation.

[0015] 5. In the prior art, timing violation problems are only repaired in a single process;

[0016] 6. Using the step-by-step forward and backward borrowing timing will introduce a large number of buffers on the clock path, which will greatly increase the power consumption and cost of chip design, but there are no subsequent optimization measures. Summary of the invention

[0017] To solve the above problems, the technical solution of the present invention is a clock tree adaptive optimization method based on RISC-V architecture using useful deviations, in which S1, layout; S2, placement; S3, after clock tree synthesis, S10, register-to-register timing path optimization is performed; in S4, after routing, S20, register-to-memory timing path optimization is performed.

[0018] Preferably, the S10 comprises the following steps:

[0019] S11, screening the target critical path between registers;

[0020] S12, determining whether there are deviations that can be optimized;

[0021] If yes, then S13 generates a guidance document for early intervention of clock tree synthesis with feedback;

[0022] If not, exit the loop and proceed to S4, wiring.

[0023] Preferably, the S10 comprises the following steps:

[0024] S101, establish a critical path matrix, create a new optimization path list, and initialize the delay variable delayA=0;

[0025] S102, determining whether there are deviations that can be optimized;

[0026] If not, exit the loop and proceed to S4, wiring;

[0027] If yes, then S103, determine the optimization parameter value delay;

[0028] S104, reading the optimized path list;

[0029] S105, determining whether there is a critical path in the list;

[0030] If yes, then S106, update delay=delay+delayA;

[0031] If not, then S107, delayA=delay;

[0032] S108, netlist is written into critical path;

[0033] S109, adding a key path parameter delayA;

[0034] S110, generating a guidance file for clock tree synthesis.

[0035] Preferably, the S20 includes the following steps:

[0036] S21, screening the target path from register to memory that can be optimized;

[0037] S22, integrated clock model adds driver layout;

[0038] S23, executing the timing engineering change command;

[0039] S24, determining whether there are deviations that can be optimized;

[0040] If yes, return to S21;

[0041] If no, then complete S20 and execute S5 to optimize the power consumption and timing jointly.

[0042] Preferably, S5 includes adding a buffer to increase the path delay, and when the clock signal is transmitted to two physically adjacent registers, the two adjacent registers use the same buffer.

[0043] The present invention has at least the following beneficial effects: in different processes of digital IC design, the novel ADFF (Adaptive Full Flow) optimization method is used to screen the critical paths and perform loop iterations for different violation problems between registers and between registers and memories, and not only the early intervention of the clock tree synthesis stage is guided by feedback, but also the driver is added in the wiring stage to adaptively repair the violation and make the timing more convergent. At the same time, through the joint optimization means of power consumption and performance, the number of buffers used by the method is reduced, and the cost and power consumption of the entire chip design are reduced.

[0044] Through adaptive iteration, there is no need for cumbersome algorithms, which solves the shortcomings of the EDA tool's own auto useful skew and repairs the timing problem to the greatest extent. At the same time, the use of the delay unit method is combined to achieve a win-win effect of high performance and low power consumption in chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A flowchart of the steps of a clock tree adaptive optimization method using useful deviation based on a RISC-V architecture according to an embodiment of the present invention;

[0046] Figure 2 This is a flowchart of the specific steps of S10 of the clock tree adaptive optimization method using useful deviation based on RISC-V architecture according to an embodiment of the present invention;

[0047] Figure 3 A time violation model diagram is maintained for the prior art repair;

[0048] Figure 4 Fixing hold time violation model graphs for prior art EDA tools;

[0049] Figure 5 A model diagram of the present invention using useful deviation to repair hold time violation;

[0050] Figure 6 A schematic diagram of a merged delay unit of a clock tree adaptive optimization method using useful deviation based on a RISC-V architecture according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] On the contrary, the present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention as defined by the claims. Further, in order to make the public have a better understanding of the present invention, some specific details are described in detail in the detailed description of the present invention below. Those skilled in the art can fully understand the present invention without the description of these details.

[0053] See also Figure 1 , which is a flow chart of a method embodiment of the present invention, during S1, layout; S2, placement; S3, clock tree synthesis, S10, register-to-register timing path optimization is performed; during S4, routing, S20, register-to-memory timing path optimization is performed.

[0054] S10 includes the following steps:

[0055] S11, screening the target critical path between registers;

[0056] S12, determining whether there are deviations that can be optimized;

[0057] If yes, then S13 generates a guidance document for early intervention of clock tree synthesis with feedback;

[0058] If not, exit the loop and proceed to S4, wiring.

[0059] S20 includes the following steps:

[0060] S21, screening the target path from register to memory that can be optimized;

[0061] S22, integrated clock model adds driver layout;

[0062] S23, executing the timing engineering change command;

[0063] S24, determining whether there are deviations that can be optimized;

[0064] If yes, return to S21;

[0065] If no, then complete S20 and execute S5 to optimize the power consumption and timing jointly.

[0066] See also Figure 2 , S10 comprises the following steps:

[0067] S101, establish a critical path matrix, create a new optimization path list, and initialize the delay variable delayA=0;

[0068] S102, determining whether there are deviations that can be optimized;

[0069] If not, exit the loop and execute S4 to wire.

[0070] If yes, then S103, determine the optimization parameter value delay;

[0071] S104, reading the optimized path list;

[0072] S105, determining whether there is a critical path in the list;

[0073] If yes, then S106, update delay=delay+delayA;

[0074] If not, then S107, delayA=delay;

[0075] S108, netlist is written into critical path;

[0076] S109, adding a key path parameter delayA;

[0077] S110, generating a guidance file for clock tree synthesis.

[0078] The present invention proposes a novel ADFF (Adaptive Full Flow) clock tree optimization method. Chip physical design usually includes Floorplan, Place, CTS (clock tree synthesis), Route and timing ECO (Engineering Change Order). In the conventional process, designers usually use the tool to optimize the timing with useful deviation after layout and routing. This paper proposes a method of joint feedback optimization in the CTS and Route stages. In the CTS stage, the timing path is traversed and feedback is obtained, and the feedback information is returned to the pre-CTS stage for early intervention, and adaptive iteration is implemented to accurately identify all critical paths and solve the problem of setup time violations; in the Route stage, the synthesis strategy is applied in a targeted manner based on the hold time violation, and finally the full process repair and power consumption improvement of the clock tree timing violation are achieved through the joint optimization of power consumption and timing.

[0079] For the reg2reg (register-register) path, after a round of ordinary clock tree synthesis, taking late useful skew as an example, an optimization measure based on a loop iteration algorithm is proposed. By dynamically adjusting the path delay, the clock tree synthesis guidance file is updated to iteratively optimize the timing of the critical path. First, the delay variable delayA=Δ=0 is initialized, and a new optimization path list file DelayList is created to store the optimizable path. The optimizable timing path must meet the following two conditions: there is sufficient timing margin for the establishment time constraint of the subsequent path, and the target path retention time constraint is still satisfied. In each loop process after the second round, if the target optimization path does not exist in the list, the path and the delay value to be adjusted are updated to the list; if the path already exists in the list, the delay value to be adjusted is superimposed with the delay value already in the list and written to the list. Subsequently, the clock tree synthesis guidance file is generated using the updated path and delay value, and fed back to the pre-CTS stage for re-synthesis to continue iteratively repairing the timing. After establishing the critical path matrix, the loop formula is as follows:

[0080] For i=1to n

[0081] If(Si>Sth and Hi>Hth)Then

[0082] If Then

[0083] Δ=D0

[0084] Else

[0085] Di=D0+Δ

[0086] Δ=Di

[0087] DelayList←DelayList∪{(Pi,Di)}

[0088] WriteToGuidanceFile(Pi,Di)

[0089] Run CTS

[0090] Where D0 represents the determined optimization parameter value, Pi is the i-th path in the table, Si>Sth and Hi>Hth represent two timing margin prerequisites that the optimizable path must meet. Through the above cycle, an adaptive iterative optimization path is achieved.

[0091] The core of the clock tree synthesis guidance file of this method is to use the set_clock_balance_points-delay command to add a virtual delay value. Tools usually use the principle of balancing clock trees, and this virtual delay does not actually exist. Therefore, the introduction of virtual delay will increase the network delay of the clock path, thereby helping to resolve the setup time violation of the target path.

[0092] S5 includes adding a buffer to increase the path delay, and when the clock signal is transmitted to two physically adjacent registers, the two adjacent registers use the same buffer.

[0093] For the reg2mem (register-to-memory) path, use usefulskew to fix this type of hold time violation by reducing the clock-to-memory delay. Figure 3 In order to basically fix the hold time violation model, there are several registers connected to the memory. Assume that the delay of the clock to the register is 300ps, the delay to the memory is 350ps, and the path delay from the register to the memory is 40ps. Ignore clock jitter, clock uncertainty, and memory hold time requirements. According to the hold time constraint formula, these several timing paths from register to memory all have hold time violations.

[0094] See also Figure 4 The way to fix this type of hold time violation for EDA tools is to insert a large number of buffers at the violation locations to increase the path delay. Figure 5 , reducing the delay from the clock to the memory, using usefull skew to fix the hold time violation. From the setup time constraint formula, if the clock path network delay from the clock source to the start of the timing path is reduced, the setup time violation of the path will also be fixed. Therefore, the setup time constraint of the subsequent mem2reg path will also be improved. Reducing the clock delay of the memory by 10ps can not only fix the 10ps hold time violation of the reg2mem path, but also increase the setup time constraint margin of the subsequent path mem2reg by 10ps.

[0095] When optimizing timing, due to the need for high performance, the buffers inserted when adding drivers are all low voltage transistors (LVT), which will significantly increase power consumption and chip cost. Therefore, we use the merge optimization delay unit method to strictly control the number of units and achieve joint optimization of power consumption and timing. Figure 6When the clock signal is transmitted to two physically close registers, if the buffer added to the last-level clock path is added to fix the timing violation, it is planned to merge the buffers of multiple registers into one delay unit. Under the premise of keeping the function unchanged and meeting the design rules, the network cables on the path (such as Figure 6 ), connect it to the network line after the buffer on another path, so that the delay units of the two paths can be shared, which can greatly reduce power consumption.

[0096] In order to distinguish the buffers inserted by the adaptive full flow and the tool automatically, the "indelaybuffer" suffix is ​​added when naming the delay unit. Traverse all nets and filter out all nets connected with two or more inserted buffers. These nets connect two registers and ensure that all subsequent delay units are inserted by this method. The screening method is as follows:

[0097] get_net-of[get_cells*indelaybuffer*-hier]

[0098] For i=1to n get_pins-of nets

[0099] sizeof_collection pins number=2.

[0100] The present invention implements a new Adaptive Full Flow (ADFF) clock tree adaptive optimization method based on RISC-V architecture, which efficiently utilizes useful skew. In conventional processes, designers usually use the useful skew of the tool to optimize timing after layout and routing. However, this invention uses timing feedback at different stages to perform iterative cycle optimization, and finally adopts a joint strategy of power consumption and timing to improve the quality of the clock tree and reduce the burden on the chip.

[0101] Although modern EDA (Electronic Design Automation) tools generally have the "auto useful skew" function, these tools still have significant limitations in practical applications. When using the automatic function, the clock tree is optimized by setting prepone and postpone. Although increasing the prepone and postpone parameter values ​​set in the tool can improve the timing, it will introduce additional buffers on the smaller violation paths that could have been repaired through the normal layout and routing process, resulting in a significant increase in the number of clock cells. Too many buffers will not only cause longer routing time and higher routing resource consumption, but also increase clock jitter and reduce the quality of the clock tree. This effect is particularly significant in high-frequency designs. Conversely, if the parameter setting is too small, the timing violations on the critical path may not be effectively repaired.

[0102] In the design of the present invention, in the Clock Tree Synthesis (CTS) stage of the IC design process, the timing path is traversed and feedback is obtained, and the feedback information is returned to the pre-CTS stage for early intervention, and adaptive iteration is implemented to accurately identify all critical paths and solve the problem of setup time violations; in the routing stage, the synthesis strategy is applied targetedly based on the hold time violation, and finally the full process repair of the clock tree timing violation and the improvement of power consumption are achieved through the joint optimization of power consumption and timing.

[0103] The present invention can not only make the timing of chip design more convergent, but also greatly reduce the cost and power consumption required for useful deviations, and can repair more timing violations that cannot be optimized by normal layout and routing processes.

[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A clock tree adaptive optimization method based on RISC-V architecture using useful deviation, characterized in that: In S1, layout; S2, layout; After clock tree synthesis in S3, S10 is performed to optimize the timing path between registers; after routing in S4, S20 is performed to optimize the timing path between registers and memories.

2. The method according to claim 1, characterized in that The S10 comprises the following steps: S11, screening target critical paths between registers; S12, determining whether there are deviations that can be optimized; If yes, then S13 generates a guidance document for early intervention of clock tree synthesis with feedback; If not, exit the loop and proceed to S4, wiring.

3. The method according to claim 1, characterized in that The S10 comprises the following steps: S101, establish the critical path matrix, create a new optimization path list file, and initialize the delay variable delayA=0; S102, determining whether there are deviations that can be optimized; If not, exit the loop and proceed to S4, wiring; If yes, then S103, determine the optimization parameter value delay; S104, reading a list of paths to be optimized; S105, determining whether the key path exists in the list; If yes, then S106, update delay=delay+delayA; If not, then S107, delayA=delay; S108, netlist is written into critical path; S109, adding a key path parameter delayA; S110, generating a guidance file for clock tree synthesis.

4. The method according to claim 1, characterized in that: The S20 includes the following steps: S21, screening the optimizable register-to-memory target path; S22, integrated clock model adds driver layout; S23, executing the timing engineering change command; S24, determining whether there are deviations that can be optimized; If yes, return to S21; If no, then complete S20 and execute S5 to optimize the power consumption and timing jointly.

5. The method according to claim 4, characterized in that The S5 includes adding a buffer to increase the path delay, and when the clock signal is transmitted to two physically adjacent registers, the two adjacent registers use the same buffer through a merging operation.

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