Core particle and testing method thereof

Abstract

The invention provides a core particle and a test method thereof, and the core particle comprises a home terminal generator which is used for generating and sending a test code to a sending channel for transmission; wherein one test code is transmitted through one sending channel, and the number of the test codes is the same as that of the sending channels; the home terminal multiplexer is used for receiving the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; and the home terminal checker is used for generating a corresponding check code according to the received detection code and checking the corresponding detection code through the check code, if the check is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code is transmission fault. According to the core particle and the test method thereof provided by the invention, the requirements of a serial transmission test of a single channel and a parallel transmission test of a plurality of transmission channels can be met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a core particle and a testing method thereof. Background Art

[0002] In modern electronic communication systems, it is very important to ensure the quality, latency and power consumption of data transmission. Traditional electrical physical layer testing mainly relies on test circuits based on pseudo-random binary sequences (PRBS). PRBS test circuit is a commonly used test method, especially in serdes (serial deserializer) high-speed serial interfaces, which is used to generate and check pseudo-random sequences for a single transmission channel. However, the application scenarios of existing PRBS test circuits are relatively single and can only be used for testing a single channel, and cannot meet the parallel transmission test requirements of multiple transmission channels. Therefore, there is room for improvement. Summary of the invention

[0003] The object of the present invention is to provide a core particle and a test method thereof, which can meet the needs of serial transmission testing of a single channel and parallel transmission testing of multiple transmission channels.

[0004] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides a core particle, comprising:

[0006] Core particle body;

[0007] The local test module is arranged in the core particle body, and the local test module includes:

[0008] A local generator, used to generate and send a test code to a transmission channel for transmission; wherein one test code is transmitted through one transmission channel, and the number of test codes is the same as the number of the transmission channels;

[0009] A local multiplexer, used for receiving detection codes through receiving channels; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels;

[0010] The local checker is used to generate a corresponding verification code according to the received detection code, and verify the corresponding detection code through the verification code. If the verification is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code has a transmission failure.

[0011] In one embodiment of the present invention, in the serial test mode, the local generator is used to generate and send a test code within one clock cycle, and according to the number N of the sending channels, N test codes are generated within N clock cycles, and different test codes are transmitted in sequence through the corresponding sending channels according to the order of the sending channels.

[0012] In one embodiment of the present invention, in a parallel test mode, the local generator is used to generate a group of test codes within a single clock cycle, and send the group of test codes in parallel to the corresponding sending channel for transmission; wherein the number of the test codes in a group is consistent with the number of the sending channels.

[0013] In one embodiment of the present invention, the local generator is provided with a first shift register, the first shift register is used to buffer the initial code, and each bit of the initial code is represented as S0, ..., S6 in sequence;

[0014] The local generator is used to process the data in the first shift register to generate a first intermediate test code, wherein each bit of the first intermediate test code is represented by F0, ..., F7; wherein Fn+1=Sn^Sn-1, F1=S6^F7, F0=F7^F6, n=1, ..., 6;

[0015] The local generator is further configured to generate a test code according to the data in the first shift register and the lowest bit of the first intermediate test code, wherein each bit of the test code is represented as S0, ..., S6, F7.

[0016] In an embodiment of the present invention, the local generator is further configured to sequentially cache the bits except the lowest bit in the first intermediate test code into the first shift register to update the data in the first shift register.

[0017] In one embodiment of the present invention, the local generator is also used to continuously generate test codes based on the data in the first shift register, and after each test code is generated, the other bits except the lowest bit in the latest first intermediate test code are cached in the first shift register in sequence to update the data in the first shift register.

[0018] In one embodiment of the present invention, the local checker is configured with a second shift register, and the second shift register is used to buffer the detected code;

[0019] The local checker generates a corresponding second intermediate test code according to the data in the second shift register, and each bit of the second intermediate test code is represented by K0, ..., K7; wherein Kn+1=Sn^Sn-1, K1=S6^K7, K0=K7^K6, n=1, ..., 6, S0, ..., S6 are bits of the initial code;

[0020] The remote checker is also used to generate a check code based on the other bits except the lowest bit in the data in the second shift register and the lowest bit of the second intermediate test code, and each bit of the check code or remote check code is represented as S0, ..., S6, K7.

[0021] In an embodiment of the present invention, the remote checker is further used to sequentially cache the second intermediate test codes into the second shift register to update data in the second shift register.

[0022] In one embodiment of the present invention, the local checker is also used to continuously generate the check code according to the data in the second shift register, and after each check code is generated, cache the latest second intermediate test code in the second shift register in sequence to update the data in the second shift register.

[0023] The present invention also discloses a core particle testing method, which is applied to the core particle, wherein the core particle includes a core particle body, a local end generator, a local end multiplexer and a local end checker, and the testing method includes:

[0024] The local generator generates and sends a test code to a transmission channel for transmission; wherein one test code is transmitted through one transmission channel, and the number of test codes is the same as the number of transmission channels;

[0025] The local multiplexer receives the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels;

[0026] The local checker generates a corresponding verification code based on the received detection code, and verifies the corresponding detection code through the verification code; if the verification is successful, the transmission channel corresponding to the detection code is unobstructed; otherwise, the transmission channel corresponding to the detection code has a transmission failure.

[0027] As described above, the present invention provides a core particle and a test method thereof, which greatly improves the applicability and functionality of the existing PRBS test circuit by introducing multi-channel parallel test mode, flexible test pattern configuration, transmission delay calculation and other functions. It not only solves the limitations of single channel testing, but also enhances the test capability for multi-channel transmission, and is particularly suitable for complex, high-speed modern communication systems. It makes significant improvements in data transmission quality control, delay optimization and overall test efficiency.

[0028] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0030] Figure 1 Schematic diagram of the local core particle and the distal core particle in one embodiment of the present invention;

[0031] Figure 2 Schematic diagram of a local test module in one embodiment of the present invention;

[0032] Figure 3 A schematic diagram of a local generator in one embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of a remote inspector in one embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of a remote generator in one embodiment of the present invention;

[0035] Figure 6 FIG. 1 is a schematic diagram of a local checker in an embodiment of the present invention.

[0036] In the figure: 100, local end chip; 110, local end test module; 111, local end generator; 1111, first shift register; 112, local end checker; 113, local end multiplexer;

[0037] 120, Advanced Peripheral Bus; 130, Physical Layer; 131, Main Band; 132, Side Band;

[0038] 200, remote core particle; 210, remote detector; 220, remote generator. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The present invention provides a chiplet, which may be a processor chiplet, a memory chiplet, an I / O chiplet, and the like. A plurality of chiplets with different functions may be packaged into a chip to improve the performance of the chip. The chiplets may be interconnected via the UCIe (Universal Chiplet Interconnect Express) protocol to form a fully functional system. The UCIe protocol supports high-speed data transmission, ensuring high bandwidth and low latency for data exchange between chiplets. In this embodiment, the chiplets may be divided into a local chiplet 100 and a remote chiplet 200.

[0041] See also Figure 1 In one embodiment, the local chiplet 100 may include a chiplet body, a local test module 110 (Pseudo-Random Binary Sequence, PRBS), an advanced peripheral bus 120 (Advanced Peripheral Bus, APB), a physical layer 130 (physical layer) and a control status register.

[0042] In one embodiment, the core particle body refers to the core functional modules inside the core particle, such as computing units, storage units or dedicated processing units (such as AI accelerators, GPU cores, etc.), which are responsible for executing the main computing tasks of the core particle.

[0043] See also Figure 2 In one embodiment, the local test module 110 may be disposed in the core body (on the SOC). The local test module 110 may include a local generator 111 (PRBS Generator), a local checker 112 (PRBS Checker), and a local multiplexer 113 (Multiplexer).

[0044] In one embodiment, the local generator 111 can generate a local test code, namely a pseudo-random binary sequence (PRBS). The pseudo-random binary sequence can be used to simulate a real signal in data transmission and perform a transmission quality test. During the test, the pseudo-random binary sequence generated by the local generator 111 will be sent to a transmission channel (e.g., a parallel bus) to simulate transmission conditions under different conditions.

[0045] In one embodiment, the local checker 112 can be used to receive and analyze the pseudo-random binary sequence obtained from the PRBS test. The local checker 112 can check the received pseudo-random binary sequence with the expected generated sequence to detect errors in the transmission process and calculate key performance indicators such as bit error rate (BER).

[0046] In one embodiment, the local multiplexer 113 can be used to select different test signals and data sources, and switch according to the specific needs and modes of the test. In different test modes, for example: in the local loopback mode (LocalLoopback Mode), the data source is the local local generator 111, that is, the signal does not pass through the external interface after generation, but directly returns to the receiving end to verify the correctness of the sending and receiving modules themselves. In the remote loopback and normal through mode (Remote Loopback and Normal Through Mode), the data source comes from the uploaded data of the external interface (ephyinterface). In this mode, the signal will pass through a more complex transmission path, involving remote devices and external interfaces, to evaluate the performance of the entire link. The local multiplexer 113 can flexibly select different data sources, so that the same test circuit can be applied to a variety of test scenarios, increasing the flexibility and applicability of the test.

[0047] In one embodiment, the advanced peripheral bus 120 may be used to connect the control status register with the local test module 110 and the remote chiplet 200, providing a channel through which control signals may be transferred from the register to the target module.

[0048] In one embodiment, the control status register can transmit the configuration information of the local initial code to the PRBS generator module through the advanced peripheral bus 120. This configuration allows the user to set or change the initial code so as to generate different PRBS sequences under different test conditions. The local initial code can be any sequence code other than all 0s.

[0049] In one embodiment, the control state register is configured to the corresponding signal line of the local test module 110 through the apb interface. The local state machine in the local checker 112 triggers the jump condition through the change of the signal to jump to the corresponding state and execute the hardware behavior in the state. These parameters may include test mode selection, error detection threshold, bit error rate calculation method, etc. According to these parameters, the local checker can enter different working states or test modes.

[0050] Further, the test mode may include a serial test mode and a parallel test mode. In the serial test mode, the local core particle 100 and the remote core particle 200 send and receive pseudo-random code sequences through any selected signal channel in the parallel interface. The serial mode is usually used for high-bandwidth, high-speed data link testing. In the parallel test mode, the local test code is transmitted through a parallel interface (such as multiple data lines transmitted in parallel). The transmission clock rate in the parallel mode is the same as the clock rate in the serial mode, except that in the parallel mode, all signal channels in the main band are used to send data, while in the serial mode, only one signal channel in the parallel bus of the main band 131 is selected to send data. .

[0051] In one embodiment, the local state machine in the local checker 112 only exists in the local checker 112, and the generation logic in the local generator 111 is relatively simple and does not need the control of the state machine. The local state machine can have multiple working states, such as an idle state (IDLE), an initialization state (INIT), a pending state (TBD), and a test state (TEST).

[0052] In one embodiment, the IDLE state is the initial state or idle state of the local state machine. In this state, the local state machine is in a waiting state and does not perform any test operations. The local state machine can wait for a certain start condition to be met, such as an external start command, a trigger signal, or the setting of a certain configuration parameter. This state can ensure that all modules and parameters are in a ready state before the test officially starts to avoid erroneous operations or invalid data processing.

[0053] In one embodiment, the INIT state is a state for initialization. When entering the INIT state, the local state machine performs a sequence of shift operations. In the INIT state, the shift register in the checker starts to receive data received from the receiving interface of the checker. Each beat will judge the data received in the shift register. The judgment conditions are different according to the different PRBS code types. For example, in the PRBS7 mode, it is necessary to check whether the lower 8 bits are not all zero, and in the PRBS15 mode, it is necessary to check whether the lower 16 bits are all zero. If the check is not all zero, jump to the TBD state. The main purpose of the initialization state is to ensure that the received data is not all zero when PRBS generation begins, because if it is all zero, the expected data is also all zero, and the generating polynomial will fall into a loop and cannot jump out autonomously. The initialization state prepares for the upcoming test, ensures that all registers and counters are set correctly, and configures the system to a known and stable initial state.

[0054] In one embodiment, the TBD state is a temporary state for data verification. In the TBD state, the local state machine performs preliminary verification on the received data. This involves simple error checking or data integrity verification to ensure that there are no immediately visible errors in the received data. The pending state can be used to capture and identify basic transmission errors or data anomalies to prepare for subsequent more rigorous test operations. This helps to quickly filter out obviously problematic data and reduce unnecessary test steps. In the TBD state, the received data is generated by the PRBS generating polynomial to generate the next data expected to be received, and the next data received is compared with the expected data. If the comparison fails, the error counter counts by one. If the comparison passes, the error counter will be reset and automatically jump to the TEST state.

[0055] In one embodiment, the TEST state is the state in which the test operation is actually performed. In the TEST state, the local state machine performs a comparison operation, that is, a bit-by-bit comparison of the received PRBS sequence with the expected PRBS sequence. Based on the comparison results, the state machine updates the error counter (recording the number of bits where errors occurred) and the flag signal (indicating whether the current test state is normal). The test state is the core part of the entire test process. In this state, the system monitors the quality of data transmission in real time, records any detected errors, and evaluates the performance and stability of the transmission link based on these error information.

[0056] In one embodiment, after the above conditions are met, the local state machine can jump from the IDLE state to the INIT state. For example, the RX_en signal is 1, at this time the receiver (RX) is enabled, and the system is ready to receive data. When ptn_sel==1, it can be indicated that a certain specific test mode or sequence mode is selected. When the above two conditions are met at the same time, the local state machine can jump from the IDLE state to the INIT state, indicating that the system is ready to start the initialization operation. The implementation logic of this jump is because the control state register is configured to the corresponding signal in the local test module 110 through the APB interface. After the signal changes, the condition for the state machine to jump is triggered, so the local state machine can jump from the IDLE state to the INIT state. Similarly, the condition for the local state machine to jump from INIT to TBD is to check that the corresponding bit of the shift register is not all zero, and the condition for TBD to jump to the TEST state is that the PRBS expected code generated by the beat data is exactly the same as the actual data sent in the next beat. The above two conditions ensure that the local state machine will enter the initialization state only after the receiver is enabled and a specific test mode is selected, avoiding starting the test under inappropriate conditions.

[0057] In one embodiment, in the INIT state, the local state machine will perform a shift operation on the detection sequence (seq_chk). The first_pass flag determines the direction of the shift: shift to the left when it is 0 and shift to the right when it is 1. When it is detected that the local initial code (sequence tcode_i) is not zero, the state machine will jump to the TBD state. The main task of the initialization state is to pre-process the detection sequence, such as shift operations, to ensure that the sequence is ready for subsequent detection. The first_pass flag is used to indicate that this is the first time through the sequence. Such a design helps to handle different test scenarios. After detecting that tcode_i is not zero, it indicates that the sequence is ready for further verification, thereby triggering a state transition.

[0058] In one embodiment, in the TBD state, the local state machine compares the received local initial code with the expected PRBS sequence. If the XOR calculation result shows that the sequence does not match (it may not be a PRBS code), the error counter err_cnt is incremented by one. If the match is successful, the state machine jumps to the TEST state and clears the error counter. The TBD state is a transition state used to preliminarily verify whether the received sequence conforms to the expected PRBS code format. If the verification fails, the error counter accumulates the number of errors; if successful, it means that the formal test state can be entered.

[0059] In one embodiment, in the TEST state, the state machine continues to compare the PRBS code. If the comparison fails, the error counter err_cnt is incremented by one, and the flag_pass signal is pulled low, indicating that an error is detected. If the comparison is successful, the error counter remains unchanged and the flag_pass signal is pulled high, indicating that the current comparison is successful. If the RX_en signal becomes 0, indicating that the receiver is disabled, the local state machine will clear the error counter and jump back to the IDLE state. The TEST state is the main stage of the actual test, and the local state machine continuously monitors the transmission quality of the data at this stage. By adjusting the flag_pass signal, the system can provide real-time feedback on the pass or fail status of the current test. Once the receiver is disabled, the system immediately stops the test and returns to the idle state to maintain efficient use of resources.

[0060] See also Figure 1 In one embodiment, the physical layer 130 is the training management of the link status between the local chiplet 100 and the remote chiplet 200 and the actual data transmission channel. The physical layer defines the electrical and mechanical characteristics of the transmission signal, such as voltage, current, clock signal, physical interconnection medium (such as metal wire, optical fiber), etc. The physical layer can convert the data of the adaptation layer into actual physical signals and transmit them between chiplets through hardware channels. The physical layer is the lowest layer of data transmission and directly affects the transmission rate, bandwidth and reliability of the physical connection.

[0061] In one embodiment, the physical layer 130 is the base layer of the UCIe protocol and is responsible for handling the physical transmission of signals. It divides the data into a high-frequency, high-rate main band 131 (MB) and a low-frequency, low-rate sideband 132 (SB) to handle large amounts of data and control signals respectively. The high-frequency channel and clock of the main band 131 are used to ensure high-speed transmission and synchronization of large-scale parallel data, while the sideband 132 handles the transmission of low-speed control signals and system coordination.

[0062] In one embodiment, the main band 131 may include 32 parallel transmission channels, 2 redundant transmission channels, 2 differential clock transmission channels, a validity indication channel (Valid lane), a redundant validity indication channel, and a synchronous transmission channel (Track lane). Among them, the 32 parallel transmission channels are the main data transmission channels, responsible for high-speed data transmission between chips. The 2 redundant transmission channels can be used to provide backup to ensure that the integrity and stability of data transmission can be maintained when some transmission channels fail. The 2 differential clock transmission channels can be used to provide high-frequency clock signals to synchronize the data transmission of parallel transmission channels. This differential signal helps to reduce noise interference and ensure the accuracy of the clock signal. The validity indication channel can be used to indicate whether the data is valid. This channel helps the receiving end to identify the validity of the transmitted data and ensure that only valid data is processed. The redundant validity indication channel can be used to back up the validity indication channel. The synchronous transmission channel can be used to ensure the synchronization of parallel data transmission, ensure the time verification pass of each data channel, and avoid data misalignment due to delay differences.

[0063] In one embodiment, when testing the physical layer, 37 transmission channels, including 32 parallel transmission channels, 2 redundant transmission channels, a validity indication channel, a redundant validity indication channel, and a synchronous transmission channel, may be tested. The transmission channels may include a transmission channel and a receiving channel that communicate with each other. For the local chiplet 100, it may be connected to the receiving channel of the remote chiplet 200 through the transmission channel. For the remote chiplet 200, it may be connected to the receiving channel of the local chiplet 100 through the transmission channel.

[0064] In one embodiment, the sideband 132 may include a clock transmission channel, a transmission channel, and a redundant transmission channel. The clock transmission channel provides a low-frequency clock signal, which is different from the high-frequency clock of the main band. This clock lane is used for lower-speed data transmission. The transmission channel and the redundant transmission channel are used to transmit control data and status information. The redundant channel provides backup to ensure that the transmission of control data and status information will not be interrupted when a channel failure occurs.

[0065] See also Figure 1 In one embodiment, the structure of the local chip 100 and the remote chip 200 can be the same. In this case, the remote chip 200 can include a chip body, a remote test module, an advanced peripheral bus, and a physical layer. In the remote loopback and normal communication modes, the local chip 100 can be used to test the remote chip 200. In this case, the local chip 100 can be used as a test device, and the remote chip 200 can be used as a device to be tested. The remote chip 200 can be used to test the local chip 100. In this case, the local chip 100 can be used as a device to be tested, and the remote chip 200 can be used as a test device.

[0066] In one embodiment, the local chiplet 100 tests the remote chiplet 200. At this time, the control status register of the local chiplet 100 can be used to configure the local initial code and send the local initial code to the local generator 111 through the advanced peripheral bus 120.

[0067] See also Figure 3 In one embodiment, a first shift register 1111 (sft[6:0]) may be configured in the local generator 111. The first shift register 1111 may be used to cache the local initial code, and the individual bits of the local initial code are represented as S0, ..., S6 in sequence, and these bits are arranged in sequence in the shift register. Among them, the control status register may configure the 7-bit initial code of PRBS7 to the first shift register 1111SFT[6:0] through the APB interface. This initial code may be any sequence code that is not all 0. The requirement of not all 0 is to ensure that the generation of the PRBS sequence does not fall into an infinite loop state of all 0. The function of the first shift register 1111 is to temporarily store the local initial code. In subsequent operations, the system may read or process the data stored in it bit by bit through the first shift register 1111.

[0068] In one embodiment, the generating polynomial of PRBS7 is X^7+X^6+1, where ^ represents an XOR symbol. By performing an XOR operation on the values ​​of S6 and S5 in the shift register according to the polynomial, the result F7 is calculated. Since it is necessary to output an 8-bit PRBS7 test code at one time, the calculation of the PRBS7 sequence must be completed 8 times in one clock cycle. In order to complete these operations in parallel in one clock cycle, the local generator 111 will perform multiple XOR calculations at the same time, for example, S5 and S4 can generate F6 by performing an XOR operation, S4 and S3 can generate F5 by performing an XOR operation, S3 and S2 can generate F4 by performing an XOR operation, S2 and S1 can generate F3 by performing an XOR operation, S1 and S0 can generate F2 by performing an XOR operation, S0 and F7 can generate F1 by performing an XOR operation, and F7 and F6 can generate F0 by performing an XOR operation. At this time, a first intermediate test code can be generated, and each bit of the first intermediate test code can be expressed as F0, ..., F7, where Fn+1 = Sn^Sn-1, F1 = S6^F7, F0 = F7^F6, n = 1, ..., 6.

[0069] In one embodiment, after generating the first intermediate test code, the local generator 111 can generate the local test code (prbs7_o[7:0]) according to the data in the first shift register 1111 and the lowest bit of the first intermediate test code. At this time, the respective bits of the local test code are represented as S0, ..., S6, F7. At the same time, the local generator 111 needs to cache some bits in the first intermediate test code into the first shift register 1111 to update the data in the first shift register 1111.

[0070] Specifically, the local generator 111 can cache the bits except the lowest bit in the first intermediate test code into the first shift register 1111 in sequence, for example, cache F0, F1, F2, F3, F4, F5, and F6 into the first shift register 1111 in sequence, F0 can update S0, F1 can update S1, F2 can update S2, F3 can update S3, F4 can update S4, F5 can update S5, and F6 can update S6.

[0071] In one embodiment, for different test modes, the local generator 111 needs to generate different numbers of local test codes within one clock cycle to test the transmission channel. For example, for the test in the serial test mode, the local generator 111 can generate 1 local test code within 1 clock cycle, generate N test codes within N clock cycles according to the number of the transmission channels, and transmit different local test codes through the corresponding transmission channels in sequence according to the order of the transmission channels. For another example, for the parallel test mode, the local generator 111 can generate 37 local test codes within 1 clock cycle, and send the group of test codes in parallel to the corresponding transmission channel for transmission, and the number of a group of test codes is consistent with the number of transmission channels. Among them, the local test code can be sent to the local checker 112 through the local multiplexer to realize the test in the local loopback mode. The local test code can be sent to the remote core particle 200 through the transmission channel to realize the test of the remote loopback and normal communication mode.

[0072] In one embodiment, after the local generator 111 sends the local test code to the corresponding transmission channel for transmission, the local multiplexer 113 or the remote multiplexer can receive the corresponding local detection code through the corresponding receiving channel.

[0073] In one embodiment, for the serial test mode, after generating a local test code, the local generator 111 can send the local test code to the remote multiplexer of the remote core particle through a certain transmission channel to be tested, and the remote checker 210 of the remote core particle can receive the corresponding local detection code through the remote multiplexer. At this time, the remote checker 210 can generate a local check code according to the local detection code. The remote checker 210 can check the local detection code with the corresponding local check code. When the remote checker 210 confirms that the local detection code transmitted through a certain transmission channel to be tested fails to check the corresponding local check code, it indicates that a transmission failure occurs in the transmission channel, and records the transmission channel where the error occurs and the total number of errors. When the remote checker 210 confirms that the local detection code of the transmission channel passes the check with the corresponding local check code, it indicates that the transmission channel passes the test.

[0074] See also Figure 4In one embodiment, a third shift register (seg_chk[31:0]) may be configured in the remote checker 210. The third shift register may be used to store 32-bit binary data. The third shift register may be used to cache the local detection code. Subsequently, the remote checker 210 may generate a corresponding second intermediate detection code according to the data in the third shift register, and each bit of the second intermediate detection code is represented as K0, K1, K2, K3, K4, K5, K6, K7, where Kn+1=Sn^Sn-1, K1=S6^K7, K0=K7^K6.

[0075] In one embodiment, after generating the second intermediate detection code, the remote checker 210 can generate a local check code according to the data in the third shift register and the lowest bit of the second intermediate detection code. At this time, each bit of the local check code is represented as S0, ..., S6, K7. At the same time, the remote checker 210 needs to cache some bits in the second intermediate detection code into the third shift register to update the data in the third shift register.

[0076] Specifically, the remote checker 210 can cache the bits except the lowest bit in the second intermediate detection code into the third shift register in sequence, for example, cache K0, K1, K2, K3, K4, K5, and K6 into the third shift register in sequence, K0 can update S0, K1 can update S1, K2 can update S2, K3 can update S3, K4 can update S4, K5 can update S5, and K6 can update S6.

[0077] In one embodiment, in the above serial test mode, only one clock test is completed between the local generator 111 and the remote checker 210. Subsequently, the local generator 111 can continuously generate the local test code according to the data cached in the first shift register 1111, and after each new local test code is generated, the other bits of the latest first intermediate test code except the lowest bit are sequentially cached in the first shift register 1111 to update the data in the first shift register 1111. At the same time, after each local test code is generated, it needs to be sent to the remote checker 210 through different transmission channels in the order of the transmission channels for inspection. The remote checker 210 can continuously generate the local check code according to the data cached in the third shift register, and after each local check code is generated, the latest second intermediate detection code is sequentially cached in the third shift register to update the data in the third shift register. After the local generator 111 sends a local test code to the remote checker 210, the remote checker 210 can complete a test according to the local detection code. After the remote checker 210 completes the test, the local generator 111 may send the next local test code to the remote checker 210 to continue the test.

[0078] In one embodiment, for the parallel test mode, after generating a local test code, the local generator 111 can continue to generate local test codes according to the data cached in the first shift register 1111 until the number of local test codes generated in one clock cycle reaches 37. At this time, these 37 local test codes can be represented as a group of local test codes. The local generator 111 can transmit this group of local test codes to the remote checker 210 through the corresponding transmission channels according to the order of the transmission channels.

[0079] In one embodiment, after the remote checker 210 receives the group of local detection codes, it can first read the first local detection code. Then, the remote checker 210 can cache the first local detection code in the third shift register. Then, the remote checker 210 can generate the corresponding second intermediate detection code according to the data cached in the third shift register, and generate the local check code according to the data in the third shift register and the lowest bit of the second intermediate detection code. At this time, the remote checker 210 can generate the first local check code.

[0080] In one embodiment, the remote checker 210 can also cache some bits of the first second intermediate detection code generated into the third shift register, and then generate a second local check code according to the data cached in the third shift register. The remote checker 210 can also be used to continuously generate local check codes according to the data in the third shift register, and after each local check code is generated, the latest second intermediate detection code is sequentially cached into the third shift register to update the data in the third shift register. And so on, until 37 local check codes are generated within 1 clock cycle.

[0081] In one embodiment, the remote checker 210 can check the 37 local detection codes within one clock cycle with the corresponding 37 local check codes. When the remote checker 210 confirms that the local detection code of a certain transmission channel fails to check the corresponding local check code, it records the transmission channel where the error occurs and the total number of errors. When the remote checker 210 confirms that the local detection codes of all transmission channels pass the check with the corresponding local check codes, it indicates that the test is passed.

[0082] In one embodiment, in the above parallel test mode, only one clock test is completed between the local generator 111 and the remote checker 210. The local generator 111 can continuously generate the local test code according to the data cached in the first shift register 1111, and after each set of new local test codes is generated, the bits other than the lowest bit in the latest first intermediate test code are sequentially cached in the first shift register 1111 to update the data in the first shift register 1111. At the same time, after each set of local test codes is generated, it needs to be sent to the remote checker 210 for inspection. The remote checker 210 can continuously generate the local check code according to the data cached in the third shift register, and after each local check code is generated, the latest second intermediate detection code is sequentially cached in the third shift register to update the data in the third shift register. After the local generator 111 sends a set of local detection codes to the remote checker 210, the remote checker 210 can complete a test according to the set of local detection codes. After the remote checker 210 completes the test, the local generator 111 may send the next set of local detection codes to the remote checker 210 to continue the test.

[0083] In one embodiment, the remote chiplet 200 tests the local chiplet 100. At this time, the control status register of the remote chiplet 200 can be used to configure the remote initialization code and send the remote initialization code to the remote generator 220 through the advanced peripheral bus.

[0084] See also Figure 5In one embodiment, a fourth shift register may be configured in the remote generator 220. The fourth shift register may be used to cache the remote initial code. Each bit of the remote initial code is arranged in sequence in the shift register.

[0085] In one embodiment, the remote generator 220 can generate a third intermediate test code according to the remote initial code, and the calculation process is the same as the process of the local generator 111 generating the first intermediate test code according to the local initial code. After generating the third intermediate test code, the remote generator 220 can generate a remote test code according to the data in the fourth shift register and the lowest bit of the third intermediate test code. At the same time, the remote generator 220 needs to cache some bits in the third intermediate test code into the fourth shift register to update the data in the fourth shift register. Among them, the caching process of the third intermediate test code is similar to the caching process of the first intermediate test code.

[0086] In one embodiment, for the serial test mode, after generating a remote test code, the remote generator 220 can send the remote test code to the local multiplexer 113 of the local chip 100 through a certain transmission channel to be tested, and the local checker 112 of the local chip can receive the remote detection code through the local multiplexer 113. At this time, the local checker can generate a remote verification code based on the remote detection code. The local checker 112 can verify the remote detection code with the corresponding remote verification code. When the local checker 112 confirms that the remote detection code transmitted through a certain transmission channel to be tested fails to verify the corresponding remote verification code, it indicates that there is a problem with the transmission channel, and records the transmission channel with the error and the total number of errors. When the local checker 112 confirms that the remote detection code of the transmission channel passes the verification with the corresponding remote verification code, it indicates that the transmission channel passes the test.

[0087] See also Figure 6 In one embodiment, a second shift register may be configured in the local checker 112. The second shift register may be used to store 32-bit binary data. The second shift register may be used to cache the remote detection code. Subsequently, the local checker 112 may generate a corresponding fourth intermediate detection code according to the data in the second shift register. The generation process of the fourth intermediate detection code may be similar to the generation process of the second intermediate detection code.

[0088] In one embodiment, after generating the fourth intermediate detection code, the local checker 112 can generate a remote check code according to the data in the second shift register and the lowest bit of the fourth intermediate detection code. At the same time, the local checker 112 needs to cache some bits in the fourth intermediate detection code into the second shift register to update the data in the second shift register. The generation process of the remote check code is similar to the generation process of the local check code. The caching process of the fourth intermediate detection code is similar to the caching process of the second intermediate detection code.

[0089] In one embodiment, in the above serial test mode, only one clock test is completed between the remote generator 220 and the local checker 112. In order to improve the accuracy of the test result, the remote generator 220 can continuously generate the remote test code according to the data cached in the fourth shift register, and after each new remote test code is generated, the other bits of the latest third intermediate test code except the lowest bit are sequentially cached in the fourth shift register to update the data in the fourth shift register. At the same time, after each remote test code is generated, it needs to be sent to the local checker 112 for inspection. The local checker 112 can continuously generate the remote check code according to the data cached in the second shift register, and after each remote check code is generated, the latest fourth intermediate detection code is sequentially cached in the second shift register to update the data in the second shift register. Among them, after the remote generator 220 sends a remote detection code to the local checker 112, the local checker 112 can complete a test according to the remote detection code. After the local checker 112 completes the test, the remote generator 220 may send the next remote test code to the local checker 112 to continue the test.

[0090] In one embodiment, for the parallel test mode, after generating a remote test code, the remote generator 220 can continue to generate remote test codes according to the data buffered in the fourth shift register until the number of remote test codes generated in one clock cycle reaches 37. At this time, these 37 remote test codes can be represented as a group of remote test codes. The remote generator 220 can transmit this group of remote test codes to the local checker 112 through the corresponding transmission channels according to the order of the transmission channels.

[0091] In one embodiment, after receiving the group of remote detection codes, the local checker 112 may first read the first remote detection code. Subsequently, the local checker 112 may cache the first remote detection code in the second shift register. Subsequently, the local checker 112 may generate a corresponding fourth intermediate detection code according to the data cached in the second shift register, and generate a remote check code according to the data in the second shift register and the lowest bit of the fourth intermediate detection code. At this time, the local checker 112 may generate the first remote check code.

[0092] In one embodiment, the local checker 112 can also cache some bits of the first fourth intermediate detection code generated in the second shift register, and then generate a second remote check code according to the data cached in the second shift register. The local checker 112 can also be used to continuously generate remote check codes according to the data in the second shift register, and after each remote check code is generated, the latest fourth intermediate detection code is sequentially cached in the second shift register to update the data in the second shift register. And so on, until 37 remote check codes are generated in one clock cycle.

[0093] In one embodiment, the local checker 112 can check the 37 remote detection codes in one clock cycle with the corresponding 37 remote verification codes. When the local checker 112 confirms that the remote detection code of a certain transmission channel fails to verify the corresponding remote verification code, it records the transmission channel where the error occurs and the total number of errors. When the local checker 112 confirms that the remote detection codes of all transmission channels pass the verification with the corresponding remote verification codes, it indicates that the test is passed.

[0094] In one embodiment, in the above parallel test mode, only one clock test is completed between the remote generator 220 and the local checker 112. In order to improve the accuracy of the test result, the remote generator 220 can continuously generate the remote test code according to the data cached in the fourth shift register, and after each new set of remote test codes is generated, the other bits of the latest first intermediate test code except the lowest bit are sequentially cached in the fourth shift register to update the data in the fourth shift register. At the same time, after each set of remote test codes is generated, it needs to be sent to the local checker 112 for inspection. The local checker 112 can continuously generate the remote check code according to the data cached in the second shift register, and after each remote check code is generated, the latest fourth intermediate test code is sequentially cached in the second shift register to update the data in the second shift register. After the remote generator 220 sends a set of remote test codes to the local checker 112, the local checker 112 can complete a test according to the set of remote detection codes. After the local checker 112 completes the test, the remote generator 220 may send the next set of remote test codes to the local checker 112 to continue the test.

[0095] In one embodiment, in the local loopback mode, the local chip 100 or the remote chip 200 can test itself. Take the local chip 100 as an example for explanation. The local test code generated by the local generator 111 can be directly sent to the local checker 112. The local checker 112 can generate a corresponding local check code based on the local detection code. The local checker 112 can check the local detection code with the corresponding local check code, and when the check fails, record the total number of errors. When the check passes, it means that there is no problem with the internal communication of the local chip 100, and the remote loopback and normal communication mode tests can be performed at this time. Among them, in the local loopback mode, the remote loopback and normal communication mode, the local test code generated by the local generator 111 can have the same process, the process of the local checker 112 generating the corresponding local check code according to the local detection code can be the same, and the verification process of the local checker 112 can also be the same. In local loopback mode, remote loopback mode and normal communication mode, serial test mode and parallel test mode can be tested.

[0096] It can be seen that in the above scheme, by introducing multi-channel parallel test mode, flexible test pattern configuration, transmission delay calculation and other functions, the applicability and functionality of the existing PRBS test circuit are greatly improved. It not only solves the limitations of single-channel testing, but also enhances the testing capability for multi-channel transmission, which is particularly suitable for complex, high-speed modern communication systems. It has significantly improved data transmission quality control, delay optimization and overall test efficiency.

[0097] The present invention also discloses a method for testing a core particle, which can be applied to the core particles mentioned above. The core particles can be divided into a local core particle 100 and a remote core particle 200. The local core particle 100 can include a core particle body, a physical layer, a local generator, a local multiplexer, and a local checker. The testing method includes:

[0098] The local generator generates and sends a test code to a transmission channel for transmission; wherein one test code is transmitted through one transmission channel, and the number of the test codes is the same as the number of the transmission channels;

[0099] The local multiplexer receives the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels;

[0100] The local checker generates a corresponding check code according to the received detection code, and verifies the corresponding detection code through the check code; if the verification is successful, the transmission channel corresponding to the detection code is unobstructed; otherwise, the transmission channel corresponding to the detection code has a transmission failure.

[0101] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A core particle, characterized in that: include: Core particle body; The local test module is arranged in the core particle body, and the local test module includes: A local generator, used to generate and send a test code to a transmission channel for transmission; wherein one test code is transmitted through one transmission channel, and the number of test codes is the same as the number of transmission channels; A local multiplexer, used for receiving detection codes through receiving channels; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; The local checker is used to generate a corresponding verification code according to the received detection code, and verify the corresponding detection code through the verification code. If the verification is successful, the transmission channel corresponding to the detection code is unobstructed, otherwise, the transmission channel corresponding to the detection code has a transmission failure.

2. The core particle according to claim 1, characterized in that In the serial test mode, the local generator is used to generate and send a test code within one clock cycle, and according to the number N of the sending channels, N test codes are generated within N clock cycles, and different test codes are transmitted in sequence through the corresponding sending channels according to the order of the sending channels.

3. The core particle according to claim 1, characterized in that In the parallel test mode, the local generator is used to generate a group of test codes in a single clock cycle, and send the group of test codes in parallel to the corresponding transmission channels for transmission; wherein the number of the test codes in a group is consistent with the number of the transmission channels.

4. The core particle according to claim 1, characterized in that The local generator is provided with a first shift register, the first shift register is used to buffer the initial code, and each bit of the initial code is represented as S0, ..., S6 in sequence; The local generator is used to process the data in the first shift register to generate a first intermediate test code, wherein each bit of the first intermediate test code is represented by F0, ..., F7; wherein Fn+1=Sn^Sn-1, F1=S6^F7, F0=F7^F6, n=1, ..., 6; The local generator is further configured to generate a test code according to the data in the first shift register and the lowest bit of the first intermediate test code, wherein each bit of the test code is represented as S0, ..., S6, F7.

5. The core particle according to claim 4, characterized in that The local generator is further used to sequentially cache the bits except the lowest bit in the first intermediate test code into the first shift register to update the data in the first shift register.

6. The core particle according to claim 5, characterized in that The local generator is also used to continuously generate test codes according to the data in the first shift register, and after each test code is generated, the other bits except the lowest bit in the latest first intermediate test code are sequentially cached into the first shift register to update the data in the first shift register.

7. The core particle according to claim 1, characterized in that The local checker is provided with a second shift register, and the second shift register is used to cache the detected code; The local checker generates a corresponding second intermediate test code according to the data in the second shift register, and each bit of the second intermediate test code is represented by K0, ..., K7; wherein Kn+1=Sn^Sn-1, K1=S6^K7, K0=K7^K6, n=1, ..., 6, S0, ..., S6 are bits of the initial code; The remote checker is also used to generate a check code based on the other bits except the lowest bit in the data in the second shift register and the lowest bit of the second intermediate test code, and each bit of the check code or remote check code is represented as S0, ..., S6, K7.

8. The core particle according to claim 7, characterized in that The remote checker is further used to sequentially cache the second intermediate test codes into the second shift register to update the data in the second shift register.

9. The core particle according to claim 8, characterized in that The local checker is further used to continuously generate the check code according to the data in the second shift register, and after each check code is generated, sequentially cache the latest second intermediate test code into the second shift register to update the data in the second shift register.

10. A method for testing a core particle, characterized in that: Applied to a core particle, the core particle is the core particle according to any one of claims 1 to 9, the core particle comprises a core particle body, a local generator, a local multiplexer and a local checker, and the testing method comprises: The local generator generates and sends a test code to a transmission channel for transmission; wherein one test code is transmitted through one transmission channel, and the number of test codes is the same as the number of transmission channels; The local multiplexer receives the detection code through the receiving channel; wherein one detection code is received through one receiving channel, and the number of the detection codes is consistent with the number of the receiving channels; The local checker generates a corresponding verification code based on the received detection code, and verifies the corresponding detection code through the verification code; if the verification is successful, the transmission channel corresponding to the detection code is unobstructed; otherwise, the transmission channel corresponding to the detection code has a transmission failure.

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