Circuit breaker power module layout optimization method and system based on multi-chip current sharing

Abstract

The invention proposes a circuit breaker power module layout optimization method and system based on multi-chip current sharing, and relates to the technical field of power electronics, and the method comprises the steps: collecting parasitic parameters of a circuit breaker power module, and constructing a first switch transient circuit model according to the parasitic parameters; constructing a conduction transient process circuit based on the first switch transient circuit model and the conduction transient characteristics; performing current equalization on the conducted transient process circuit according to the common-source inductance compensation function so as to perform state updating on the conducted transient process circuit, and obtaining a second switch transient circuit model corresponding to the conducted transient process circuit after state updating; extracting a parasitic inductance parameter in the second switch transient circuit model by adopting an ANSYS Q3D simulation tool, and performing multiple iterative optimization on the copper layer shape and the copper layer size of each power tube in the second switch transient circuit model through finite element simulation according to the common-source inductance compensation function and the parasitic inductance parameter; and obtaining an optimized layout scheme of the circuit breaker power module. According to the invention, the problem of local overload caused by non-uniform current distribution can be avoided, and the current sharing degree of the device under the condition that multiple chips are connected in parallel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a circuit breaker power module layout optimization method and system based on multi-chip current sharing. Background Art

[0002] In recent years, with the rapid development of power electronics technology, the requirements for power devices are getting higher and higher. Compared with traditional Si MOSFET, SiCMOSFET has many advantages such as higher switching speed, lower on-state loss and higher blocking voltage, which can improve system efficiency, reduce equipment size and thus increase equipment power density. However, due to the current process level and cost limitations under specific requirements, the current capacity of a single SiC MOSFET is limited and cannot meet the requirements of high-power occasions. It is often necessary to use multiple SiC MOSFETs in parallel. This parallel application solution is widely used in fields such as motor control and inverters.

[0003] The Chinese patent with the announcement number CN113392552B discloses a method for optimizing the current sharing of multiple parallel switch devices based on finite element simulation. The multiple parallel switch devices include: a driving module, a first switch tube device, a second switch tube device, ..., and an nth switch tube device. The length of the routing between the driving module and the switch device is manually set, and the circuit board is designed by the AltiumDesigner software according to the principle of structural symmetry between the first switch tube device, the second switch tube device, ..., and the nth switch tube device; the optimized target parasitic inductance value is determined; the required error is set; the width of the routing between the initial driving module and the switch device is calculated in combination with the target parasitic inductance value, and the width of the routing between the driving module and the switch device is optimized through multiple iterations of finite element simulation. However, the method provided in the above application will aggravate the magnetic coupling between multiple current loops, and is not easy to package and integrate the power module and use it in parallel later, resulting in a decrease in the current sharing degree of the device. Therefore, it is very necessary to provide a circuit breaker power module layout optimization method and system based on multi-chip current sharing to improve the device current sharing degree in the case of multi-chip parallel connection. Summary of the invention

[0004] In view of this, the present invention proposes a circuit breaker power module layout optimization method and system based on multi-chip current sharing. By optimizing the current balance of the conduction transient process circuit, current sharing among multiple power devices is achieved, local overload problems caused by uneven current distribution are avoided, and the current sharing of devices in the case of multi-chip parallel connection is improved.

[0005] The present invention provides a circuit breaker power module layout optimization method based on multi-chip current sharing, the method comprising:

[0006] Collecting parasitic parameters of the circuit breaker power module, and constructing a first switch transient circuit model according to the parasitic parameters;

[0007] Based on the first switch transient circuit model and the conduction transient characteristics, construct a conduction transient process circuit;

[0008] Performing current balancing on the conduction transient process circuit according to the common source inductance compensation function to update the state of the conduction transient process circuit, and obtaining a second switch transient circuit model corresponding to the conduction transient process circuit after the state update;

[0009] The parasitic inductance parameters in the second switch transient circuit model are extracted by using the ANSYS Q3D simulation tool. According to the common source inductance compensation function and the parasitic inductance parameters, the copper layer shape and copper layer size of each power tube in the second switch transient circuit model are iteratively optimized multiple times through finite element simulation to obtain the optimized layout scheme of the circuit breaker power module.

[0010] On the basis of the above technical solution, preferably, the parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and positive lead terminals of each power tube in the circuit breaker power module, the parasitic inductance between the source and negative lead terminals of each power tube, and the coupling inductance between two parallel power tubes.

[0011] On the basis of the above technical solution, preferably, the conduction transient process circuit includes a circuit driving unit, a plurality of parallel switch units, a balanced voltage stabilizing unit and a power supply, wherein:

[0012] The first common ends of the multiple parallel switch units are respectively electrically connected to the first end of the circuit driving unit, one end of the balanced voltage stabilizing unit and the positive pole of the power supply, the second common ends of the multiple parallel switch units are respectively electrically connected to the second end of the circuit driving unit, the other end of the balanced voltage stabilizing unit and the negative pole of the power supply, and the third common ends of the multiple parallel switch units are electrically connected to the third end of the circuit driving unit.

[0013] More preferably, the parallel switch unit includes a first MOS tube, a second MOS tube, a first parasitic inductor, a second parasitic inductor and a common source inductor, wherein:

[0014] The gate of the first MOS tube is electrically connected to the first end of the circuit driving unit and the remaining parallel switch units respectively, the drain of the first MOS tube is electrically connected to one end of the first parasitic inductor, the other end of the first parasitic inductor is electrically connected to the remaining parallel switch units respectively, the source of the first MOS tube is electrically connected to one end of the common source inductor, the common end of the common source inductor and the second parasitic inductor is electrically connected to the third end of the circuit driving unit and the remaining parallel switch units respectively, the other end of the second parasitic inductor is electrically connected to the source of the second MOS tube, the gate of the second MOS tube is electrically connected to the second end of the circuit driving unit and the remaining parallel switch units respectively, and the drain of the first MOS tube is electrically connected to the remaining parallel switch units and one end of the balanced voltage stabilizing unit respectively.

[0015] More preferably, the common source inductance compensation function is expressed as:

[0016] L Loop =L D +L com +L S

[0017]

[0018] Among them, L LOOP Represents the loop inductance of the parallel switch unit, L D It represents the parasitic inductance from the drain of the MOS tube to the positive lead-out terminal of the DC power supply, L S It represents the parasitic inductance from the source of the MOS tube to the negative lead-out terminal of the DC power supply, L com Represents the common source inductance value in the parallel switch unit, ΔI 1-2 represents the branch-to-branch circulating current between the first parallel switch unit and the second parallel switch unit in frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in frequency domain form, I d2 represents the drain current of the second parallel switch unit in frequency domain form, ΔI d1-2 It represents the difference of drain current between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL Loop1-2 It represents the loop inductance difference between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL com It represents the difference in common source inductance between the first parallel switch unit and the nth parallel switch unit in frequency domain form, ΔL Loop The loop inductance difference between the first parallel switch unit and the nth parallel switch unit in frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, Lcom1 Represents the common source inductance value in the first parallel switch unit.

[0019] More preferably, the extracting the parasitic inductance parameters in the second switch transient circuit model using the ANSYS Q3D simulation tool specifically includes:

[0020] Importing the second switch transient circuit model into the ANSYS Q3D simulation tool, and performing material setting on the second switch transient circuit model to obtain a transition switch transient circuit model;

[0021] Performing mesh division operations on the transition switch transient circuit model in sequence, and setting excitations correspondingly to the current inflow end and the current outflow end of each mesh in the transition switch transient circuit model;

[0022] A simulation operation is performed on the transition switch transient circuit model to obtain an inductance matrix corresponding to the transition switch transient circuit model and parasitic inductance parameters in the transition switch transient circuit model.

[0023] More preferably, each grid in the transition switch transient circuit model includes a plurality of current inflow ends and one current outflow end, and the current inflow end and the current outflow end are edges or faces in the transition switch transient circuit model.

[0024] Further preferably, the balancing voltage-stabilizing unit includes a first voltage-stabilizing diode, a second voltage-stabilizing diode and a load inductor, the anode of the first voltage-stabilizing diode is electrically connected to the first common end of the plurality of parallel switch units and one end of the load inductor, the cathode of the first voltage-stabilizing diode is electrically connected to the cathode of the second voltage-stabilizing diode, the anode of the second voltage-stabilizing diode is electrically connected to the second common end of the plurality of parallel switch units and the negative electrode of the power supply, and the other end of the load inductor is electrically connected to the positive electrode of the power supply.

[0025] In a second aspect of the present application, a circuit breaker power module layout optimization system based on multi-chip current sharing is provided, wherein the circuit breaker power module layout optimization system comprises a circuit construction module, a current balancing module and a layout optimization module, wherein:

[0026] The circuit construction module is used to collect parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a turn-on transient process circuit based on the first switch transient circuit model and the turn-on transient characteristics;

[0027] The current balancing module is used to perform current balancing on the conduction transient process circuit according to the common source inductance compensation function, so as to update the state of the conduction transient process circuit and obtain a second switch transient circuit model corresponding to the conduction transient process circuit after the state update;

[0028] The layout optimization module is used to extract parasitic inductance parameters in the second switch transient circuit model using the ANSYS Q3D simulation tool, and according to the common source inductance compensation function and the parasitic inductance parameters, perform multiple iterative optimizations on the copper layer shape and copper layer size of each power tube in the second switch transient circuit model through finite element simulation to obtain an optimized layout solution for the circuit breaker power module.

[0029] In a third aspect of the present application, a computer device is provided, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of the circuit breaker power module layout optimization method based on multi-chip current sharing.

[0030] The circuit breaker power module layout optimization method and system based on multi-chip current sharing provided by the present invention have the following beneficial effects compared with the prior art:

[0031] (1) By establishing a detailed switching transient circuit model and combining it with the turn-on transient characteristics, a more accurate turn-on transient process circuit model is constructed, which can better reflect the voltage and current changes in the actual switching process, and help to more accurately predict and control the switching performance. At the same time, by optimizing the current balancing of the turn-on transient process circuit, the current equalization among multiple power devices is achieved, avoiding the local overload problem caused by uneven current distribution, and improving the device current equalization in the case of multiple chips in parallel, effectively avoiding the decrease in the current carrying capacity of the power module and irreversible device damage caused by uneven current, so as to meet the requirements of the power module's switching capacity and usage stability in solid-state circuit breaker applications.

[0032] (2) By meshing and setting excitation for the transient circuit model of the transition switch, the actual current distribution can be simulated more accurately, thereby obtaining more accurate inductance matrix and parasitic inductance parameters. At the same time, ANSYS Q3D simulation can more comprehensively consider the influence of factors such as circuit topology and material properties on parasitic parameters, thereby improving the accuracy of parameter extraction. This helps to more accurately predict and control electromagnetic interference and thermal stress problems during the switching transient process, and improve the electromagnetic compatibility and reliability of the optimized layout solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic flow chart of a circuit breaker power module layout optimization method based on multi-chip current sharing provided by the present invention;

[0035] Figure 2 A schematic diagram of the structure of the conduction transient process circuit provided by the present invention;

[0036] Figure 3 A simulation waveform diagram of a second switch transient circuit model provided by the present invention;

[0037] Figure 4 A schematic diagram of the framework of the circuit breaker power module layout optimization system provided by the present invention.

[0038] Explanation of the accompanying drawings: 1. Circuit driving unit; 2. Parallel switch unit; 3. Balanced voltage stabilizing unit; 4. Power supply; 5. New energy equipment system maintenance decision system; 51. Information collection module; 52. Fault calculation module; 53. Decision optimization module. DETAILED DESCRIPTION

[0039] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The present invention discloses a circuit breaker power module layout optimization method based on multi-chip current sharing, referring to Figure 1 The method includes steps S1 to S4.

[0041] Step S1, collecting parasitic parameters of a circuit breaker power module, and constructing a first switch transient circuit model according to the parasitic parameters.

[0042] In this embodiment, in order to simplify the analysis process, only the parasitic inductance caused by the package in the circuit breaker power module is considered. The parasitic inductance caused by the package usually includes the upper copper of the DBC, the bonding wire, the lead terminal, etc. The four-terminal measurement method can be used to calculate the equivalent inductance by measuring the voltage drop and current between the upper copper traces of the DBC, or the inductance between the upper copper traces of the DBC can be directly measured using an LCR tester. The equivalent inductance can be calculated by measuring the voltage drop and current of the bonding wire segment from the MOSFET to the DBC, or a special test probe for the bonding wire can be used for direct measurement. The equivalent inductance is calculated by measuring the voltage drop and current of the trace segment from the DBC to the external lead terminal, or the inductance of the lead terminal segment can be directly measured using an LCR tester.

[0043] In this embodiment, the parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and positive lead terminals of each power tube in the circuit breaker power module, the parasitic inductance between the source and negative lead terminals of each power tube, and the coupling inductance between two parallel power tubes.

[0044] Furthermore, according to the actual structure of the power module, a topological structure diagram including key components such as MOSFET / power tube, PCB / DBC, and lead terminals is drawn. On the topological structure diagram, the parasitic inductance, capacitance and other parameters existing in key parts such as between MOSFET / power tube, between PCB / DBC, and PCB / DBC routing are identified. According to the topological structure diagram, a transient circuit model describing the first switch is constructed, and the switching characteristics of the MOSFET / power tube itself are modeled as an ideal switch, and various parasitic inductance and capacitance obtained by measurement or simulation are added around it, while considering the parasitic parameters of components such as PCB / DBC and lead terminals, and reasonably organizing them into an equivalent circuit.

[0045] Step S2: constructing a turn-on transient process circuit based on the first switch transient circuit model and the turn-on transient characteristics.

[0046] In this step, the characteristic curve of the circuit breaker power device during the conduction process is obtained, including the relationship between the change of voltage, current, etc. with time. Combined with the first switch transient circuit model and the obtained conduction transient characteristics, an equivalent circuit describing the changes of current, voltage, etc. of the entire power module during the conduction process is established, that is, the conduction transient process circuit.

[0047] In circuit modeling, the parasitic inductance of a MOSFET package is divided into L D , L com and L S To simplify the representation, the parasitic parameters corresponding to the two MOSFETs in the parallel switch unit are combined. DIt represents the parasitic inductance from the drain of the MOSFET chip to the positive lead terminal of the DC power supply, L S It represents the parasitic inductance from the chip source to the negative lead terminal of the DC power supply, L com That is, common source inductance, which represents the coupled inductance between the gate loop and the power loop, including both the shared inductance of the overlapping paths between the two loops and the mutual inductance caused by the coupling effect between the loops.

[0048] In this embodiment, the conduction transient process circuit includes a circuit driving unit 1, a plurality of parallel switch units 2, a balanced voltage stabilizing unit 3 and a power supply 4, wherein the first common ends of the plurality of parallel switch units 2 are respectively electrically connected to the first end of the circuit driving unit 1, one end of the balanced voltage stabilizing unit 3 and the positive pole of the power supply 4, the second common ends of the plurality of parallel switch units 2 are respectively electrically connected to the second end of the circuit driving unit 1, the other end of the balanced voltage stabilizing unit 3 and the negative pole of the power supply 4, and the third common ends of the plurality of parallel switch units 2 are electrically connected to the third end of the circuit driving unit 1.

[0049] Further, the parallel switch unit 2 includes a first MOS tube, a second MOS tube, a first parasitic inductor, a second parasitic inductor and a common source inductor, wherein the gate of the first MOS tube is electrically connected to the first end of the circuit driving unit 1 and the remaining parallel switch units 2 respectively, the drain of the first MOS tube is electrically connected to one end of the first parasitic inductor, the other end of the first parasitic inductor is electrically connected to the remaining parallel switch units 2 respectively, the source of the first MOS tube is electrically connected to one end of the common source inductor, the common end of the common source inductor and the second parasitic inductor is electrically connected to the third end of the circuit driving unit 1 and the remaining parallel switch units 2 respectively, the other end of the second parasitic inductor is electrically connected to the source of the second MOS tube, the gate of the second MOS tube is electrically connected to the second end of the circuit driving unit 1 and the remaining parallel switch units 2 respectively, and the drain of the first MOS tube is electrically connected to the remaining parallel switch units 2 and one end of the balanced voltage stabilizing unit 3 respectively.

[0050] The balancing voltage-stabilizing unit 3 includes a first voltage-stabilizing diode, a second voltage-stabilizing diode and a load inductor, the positive electrode of the first voltage-stabilizing diode is electrically connected to the first common end of the multiple parallel switch units 2 and one end of the load inductor, the negative electrode of the first voltage-stabilizing diode is electrically connected to the negative electrode of the second voltage-stabilizing diode, the positive electrode of the second voltage-stabilizing diode is electrically connected to the second common end of the multiple parallel switch units 2 and the negative electrode of the power supply 4, and the other end of the load inductor is electrically connected to the positive electrode of the power supply 4.

[0051] In one example, if Figure 2 As shown, the conduction transient process circuit includes a circuit driving unit, a first parallel switch unit, a second parallel switch unit, ..., an nth parallel switch unit, a balanced voltage stabilizing unit and a power supply, wherein:

[0052] The first parallel switch unit includes a MOS tube SW 11 、MOS tube SW 21 , parasitic inductance L D1 , parasitic inductance L S1 And the common source inductance L com1 The second parallel switch unit includes a MOS tube SW 12 、MOS tube SW 22 , parasitic inductance L D2 , parasitic inductance L S2 And the common source inductance L com2 The nth parallel switch unit includes a MOS tube SW 1n 、MOS tube SW 2n , parasitic inductance L Dn , parasitic inductance L Sn And the common source inductance L comn The balanced voltage stabilizing unit includes a voltage stabilizing diode D1, a voltage stabilizing diode D2 and a load inductor L load .

[0053] MOS tube SW 11 The gate of MOS tube SW 12 The gate, ... and MOS tube SW 1n The gates of the MOS tube SW are electrically connected to the first end of the circuit driving unit. 11 The drain of the D1 Respectively with the inductor L D2 One end of the inductor L Dn One end of the load inductance L load One end of the inductor L is electrically connected to the positive electrode of the voltage zener diode D1. D2 The other end is connected to the MOS tube SW 12 The drain is electrically connected to the inductor L Dn The other end is connected to the MOS tube SW 1n The drain of the MOS tube SW is electrically connected to 11 The source and common source inductance L com1 One end of the MOS tube SW is electrically connected 12 The source and common source inductance L com2 One end of the MOS tube SW is electrically connected 1n The source and common source inductance L comn One end is electrically connected to the common source inductor L com1 With parasitic inductance L S1 The common end and common source inductance L com2 With parasitic inductance L S2 The common end, ... and the common source inductance L comn With parasitic inductance LSn The common end of the circuit is electrically connected to the third end of the circuit driving unit, and the parasitic inductance L S1 The other end is connected to the MOS tube SW 21 The source is electrically connected to the parasitic inductance L S2 The other end is connected to the MOS tube SW 22 The source is electrically connected to the parasitic inductance L Sn The other end is connected to the MOS tube SW 2n The source of the MOS tube SW is electrically connected to 21 The gate of MOS tube SW 22 The gate, ... and MOS tube SW 2n The gates of the MOS tube SW are electrically connected to the second end of the circuit driving unit. 21 The drain of MOS tube SW 22 The drain, ... and MOS tube SW 2n The drain of the voltage regulator diode D2 is electrically connected to the positive electrode of the voltage regulator diode D2 and the common terminal of the negative electrode of the power supply, the negative electrode of the voltage regulator diode D1 is electrically connected to the negative electrode of the voltage regulator diode D2, and the load inductance L load The other end is electrically connected to the positive pole of the power supply.

[0054] Step S3, current balancing is performed on the turn-on transient process circuit according to the common source inductance compensation function to update the state of the turn-on transient process circuit and obtain a second switch transient circuit model corresponding to the turn-on transient process circuit after the state update.

[0055] In this embodiment, the expression of the common source inductance compensation function is:

[0056] L Loop =L D +L com +L S

[0057]

[0058] Among them, L LOOP Represents the loop inductance of the parallel switch unit, L D It represents the parasitic inductance from the drain of the MOS tube to the positive lead-out terminal of the DC power supply, L S It represents the parasitic inductance from the source of the MOS tube to the negative lead-out terminal of the DC power supply, L com Represents the common source inductance value in the parallel switch unit, ΔI 1-2 represents the branch-to-branch circulating current between the first parallel switch unit and the second parallel switch unit in frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in frequency domain form, I d2represents the drain current of the second parallel switch unit in frequency domain form, ΔI d1-2 It represents the difference of drain current between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL Loop1-2 It represents the loop inductance difference between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL com It represents the difference in common source inductance between the first parallel switch unit and the nth parallel switch unit in frequency domain form, ΔL Loop The loop inductance difference between the first parallel switch unit and the nth parallel switch unit in frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, L com1 Represents the common source inductance value in the first parallel switch unit.

[0059] It is understandable that since the transient processes of switch turn-on and turn-off are mirror images of each other, only the turn-on process is analyzed here. At the beginning of the turn-on process, the device channel current is determined by the gate-source voltage V gs During this transient process, the drain current through each switch is i d .

[0060] i d =g m (V gs -V th )

[0061] Since SiC MOSFET switches with similar electrical parameters were used in the device electrical parameter pre-screening process, it is assumed that the transconductance between the chips here is m and threshold voltage V th The difference in inductance of the power circuit between any two parallel switch units is ΔL. Loop , the common source inductance difference is ΔL com , if the power loop inductance difference between the first parallel switch unit and the second parallel switch unit is ΔL Loop1-2 , the common source inductance difference is ΔL com1-2 , which can be expressed as ΔL Loop1-2 =L Loop1 -L Loop2 and ΔL com1-2 =L com1 -L com2 .

[0062] The difference in package layout between the first parallel switch unit and the second parallel switch unit causes unbalanced parasitic inductance. For example, the power ring of the parallel switch unit where the chip is located near the DC power terminal is smaller, so the parasitic inductance of the power ring is smaller. The voltage drop between the parallel switch units will be uneven, resulting in a circulating current ΔI between the branches.1-2 , taking the first parallel switch unit and the second parallel switch unit as an example, for the convenience of representation, in the frequency domain form, ΔI 1-2 The calculation formula is as follows, where s is the Laplace operator:

[0063]

[0064] Common source inductance L com Acting as negative feedback between the power loop and the gate voltage, when When it is higher, the gate-source voltage of the device will be pulled down by the voltage drop across the common-source inductor.

[0065]

[0066] Considering the negative feedback compensation effect of the common source inductance, the ΔI 1-2 In terms of ΔI d The calculation method of ΔI will be updated so that 1-2 It is possible to be eliminated (without introducing L com When ΔI d =0), and after simplification, the conditions required to eliminate the circulating current between branches are further obtained:

[0067]

[0068] This formula describes the proportional relationship between the parasitic inductance of the power loop of the two branches and the common source inductance that needs to be satisfied when the current between the branches is balanced. By reasonably allocating the common source inductance, when the common source inductance unbalance ratio between the parallel switches and the power loop unbalance ratio are opposite to each other, the dynamic current caused by the unbalanced parasitic parameters can be compensated by the common source inductance. For example, for the power loop inductance L Loop The smaller the switch, the higher the common source inductance L should be designed. com Since the balance between the two is in proportional form, even if a chip is located in the branch L Loop With L com The absolute value difference between the two values ​​is quite large, and the unbalanced current can be balanced by adjusting the proportional relationship, which brings more adjustment space to the packaging layout of the power module.

[0069] Step S4, using the ANSYS Q3D simulation tool to extract the parasitic inductance parameters in the second switch transient circuit model, and according to the common source inductance compensation function and the parasitic inductance parameters, performing multiple iterations of optimization on the copper layer shape and copper layer size of each power tube in the second switch transient circuit model through finite element simulation to obtain an optimized layout solution for the circuit breaker power module.

[0070] ANSYS Q3D is an efficient electromagnetic field simulation tool mainly used for analyzing and optimizing electromagnetic design. It can be associated with large-scale modeling tools such as SolidWorks, and supports coupling analysis of electromagnetic fields with other physical fields (such as thermal fields). Therefore, it is suitable for modeling and solving high-frequency electromagnetic problems in three-dimensional scenes and multi-physical field coupling analysis. ANSYS Q3D provides a wealth of geometric modeling tools that can quickly build complex three-dimensional electromagnetic structure models. When solving parasitic parameters, the mesh division can be automatically optimized to improve the solution accuracy and efficiency, and the mesh can be flexibly set when dealing with complex geometric shapes and material interfaces. In this design, SolidWorks is used to model the internal package of the solid-state circuit breaker power module, and the 3D model is imported into Q3D for parasitic parameter extraction.

[0071] This step also includes steps S41 to S43.

[0072] Step S41 : importing the second switch transient circuit model into the ANSYS Q3D simulation tool, and performing material settings on the second switch transient circuit model to obtain a transition switch transient circuit model.

[0073] In this step, the circuit breaker power module contains 12 SiCMOSFET chips in parallel, which are arranged symmetrically from top to bottom, with 6 chips on one side and 3 on each side. The DBC is divided into 3 layers, of which the thickness of the upper copper and the lower copper is 0.3mm, and the thickness of the middle ceramic is 0.32mm. The DBC ceramic substrate is 64.5mm long and 28mm wide; the upper copper is 62.5mm long and 26mm wide (including 0.5mm fillet). The package drain D pin is equivalent to a rectangular sheet attached to the upper copper layer in the model, symmetrically placed on the right side, the source S pin is placed on the left side, and the gate G pin is placed at the end of the concave area on the lower right side. Since only the parasitic inductance in the package needs to be extracted, we only need to retain the upper copper, chip and bonding wire in the model. The module substrate layer, solder layer, lower copper and ceramic substrate modeling are not retained when the model is imported.

[0074] After importing the simplified second switch transient circuit model into Q3D, the material of the second switch transient circuit model is set. In Material, the upper copper is set to copper. Since the SiC chip does not participate in the extraction of parasitic parameters, it is set to vacuum, and the bonding wire is set to aluminum.

[0075] Step S42, meshing the transition switch transient circuit model in sequence, and setting excitations correspondingly to the current inflow end and the current outflow end of each mesh in the transition switch transient circuit model.

[0076] In this step, after setting the material, the second switch transient circuit model is automatically meshed, and at the same time, it is checked whether there is an over-defined or under-defined state at the junction of different partitions. The over-defined and under-defined states specifically refer to the fact that the material at the junction is defined multiple times or lacks definition. The final meshing should ensure that the area where parasitic parameters need to be extracted remains continuous and uninterrupted.

[0077] In this embodiment, each grid in the transition switch transient circuit model includes multiple current inflow terminals and one current outflow terminal, and the current inflow terminal and the current outflow terminal are edges or faces in the transition switch transient circuit model. The source and sink in the net are set with reference to the current injection direction in the actual application scenario. The source refers to the current inflow terminal, and the sink is the outflow terminal. There can be multiple sources and only one sink in the same net. In actual situations, when there are multiple outflow terminals in one net, it is necessary to set the excitation in reverse in Q3D and adjust it in the corresponding inductance matrix result. The selection of source and sink should be the face or edge of the model.

[0078] After completing the excitation setting, add the frequency sweep parameters in the simulation analysis. The frequency sweep used in this solution is three-stage. The first and third stages use linear frequency sweep points, and the second stage uses logarithmic frequency sweep points. The corresponding frequency sweep parameter settings are shown in Table 1.

[0079] Table 1

[0080]

[0081] Step S43: performing simulation operation on the transition switch transient circuit model to obtain an inductance matrix corresponding to the transition switch transient circuit model and parasitic inductance parameters in the transition switch transient circuit model.

[0082] In this step, the correctness of the transient circuit model of the transition switch is verified before simulation. The inductance matrix is ​​checked in the simulation results. The inductance matrix is ​​an r-order square matrix, where r is the number of nets in the grid, the main diagonal is the self-inductance of the net in this section, and the rest is the mutual inductance between nets. You can also perform a matrixreduce operation on the model before simulation to connect different nets according to the actual flow conditions, which can reduce the number of nets and shorten the simulation time. The result selects a frequency range of 100MHz-1GHz. It has been verified that the parasitic inductance has a small variation range in this frequency range and can be used as a reference.

[0083] In the circuit breaker power module, the parasitic inductance of the bonding wire on a chip in the circuit breaker power module is extracted, and then the parasitic inductance of the model near the source S end net is extracted twice. Define the end of the bonding wire on the chip as source, define the source outflow end of the power loop as sink for the first time, extract the power loop, and redefine the gate loop source pin as sink for the second time to extract part of the common source inductance L com '. At this time, the common source inductance L com =L wire +L com '. Since the power loop source pin and the gate source pin are in the same copper layer area, according to relevant literature, the extraction method can include the influence of the mutual inductance between the gate ring and the power ring on the common source inductance value.

[0084] Furthermore, in the power module packaging design, an initial first version of the design scheme is first provided, and the first version of the layout scheme is optimized and improved with the help of common source inductance compensation theory.

[0085] The main defect of the first version of the design is that the upper copper layer in the area corresponding to the lower right gate loop has a special shape, which destroys the symmetry of the copper layer of the branch where the upper and lower chips are located, increases the imbalance of parasitic parameters, and is not conducive to the current balance of parallel chips. At the same time, because the original plan places the gate loop in the concave and narrow area on the lower right side, the narrow copper layer further increases the parasitic inductance and thermal resistance.

[0086] For the six chips on the lower side, the concave design of the gate loop causes the copper layer widths of the three chip branches on the right side to be different near the S pole, which is quite irregular and makes it difficult to adjust the parasitic inductance value by changing the copper layer length. According to the parasitic parameter results of ANSYS Q3D, the common source inductance L of chip 1 from the right is com Very small (1-2nh), while the L of the left end chip com Relatively large (about 30nh), compared to the total inductance L of the power circuit Loop The difference in the changing trends is huge. Although it meets the trend law obtained from the common source inductance compensation theory, that is, the greater the parasitic inductance of the power loop where the chip is located, the smaller the common source inductance, but it obviously cannot satisfy the equation relationship.

[0087] The optimized layout solution first adjusted the irregular gate area, placed the gate pin on the center line of the power module, and adjusted the upper copper size of the branch where the upper and lower chips are located to be consistent. At the same time, considering that the connection between the left and right copper layers requires adding a bonding wire or an "I"-shaped thin copper sheet in the middle, the parasitic inductance in this area is relatively large. Since only the common source area of ​​the left chip (from the end of the bonding wire to the gate source pin) needs to pass through the middle connection area, this increases the difference in the common source parasitic inductance of the left and right chips. The common source inductance L of the left chip is com Still larger.

[0088] In one example, the method used is to adjust the shape and size of the copper layer corresponding to the power loop and the gate loop within a reasonable package layout. By adjusting the shape and size of the copper layer to control the parasitic inductance, the equation conditions are satisfied as much as possible. Considering the actual situation, for power module packages with a large number of parallel chips, it is difficult to fully satisfy the common source inductance compensation theoretical relationship due to the constraints of the chip arrangement spacing and substrate size, and the implementation cost is high. It has been verified that if the original and Under the condition that the difference between the two values ​​is large, a better flow uniformity can be achieved by narrowing the difference between the two values.

[0089] Therefore, the optimization scheme only narrows the copper layer in the common source area on the right side of the chip, increasing the basic L com1 The value of L between the six chips on the same side is reduced. com Because the power circuit does not pass through the copper layer in the right area of ​​the chip, adjusting this area has little effect on the chip power circuit. The value of remains basically unchanged, we can Reduce when the change is small The value of parasitic parameters is compared with the original and new versions. Can be considered unchanged, The new version is This balances the gap between the two to a considerable extent, weakens the circulating current between branches caused by the asymmetric parasitic parameters of the chip, and improves the current sharing between parallel branches.

[0090] like Figure 3 The simulation waveforms shown in the figure extract the parasitic parameters of the original and new package designs respectively, and build the circuit schematic in Ltspice according to the parallel chip transient circuit model. Chip model L75NT021ZJ, 750V / 21mΩ, DC power supply 400V, load inductance L Load =250-300nh, gate internal resistance R g =12Ω, the double pulse test is carried out, the number of chips in parallel is 6, the high-side switch in the half-bridge is turned off, and the low-side is turned on. The improvement of the chip current sharing by the new layout design scheme is judged according to the balance degree of the device current waveform in the simulation results.

[0091] This solution builds a more accurate turn-on transient process circuit model by establishing a detailed switching transient circuit model and combining it with the turn-on transient characteristics. It can better reflect the voltage and current changes in the actual switching process, which helps to more accurately predict and control the switching performance. At the same time, by optimizing the current balancing of the turn-on transient process circuit, current equalization among multiple power devices is achieved, avoiding local overload problems caused by uneven current distribution, and improving the device current equalization in the case of multiple chips in parallel, effectively avoiding the reduction of power module current-carrying capacity and irreversible device damage caused by uneven current, so as to meet the requirements of power module switching capacity and usage stability in solid-state circuit breaker applications.

[0092] Based on the above method, the embodiment of the present application discloses a new energy equipment system maintenance decision system based on a fault coupling model, referring to Figure 4 The circuit breaker power module layout optimization system 5 includes a circuit construction module 51, a current balancing module 52 and a layout optimization module 53, wherein:

[0093] The circuit construction module 51 is used to collect parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a turn-on transient process circuit based on the first switch transient circuit model and the turn-on transient characteristics;

[0094] The current balancing module 52 is used to balance the current of the turn-on transient process circuit according to the common source inductance compensation function, so as to update the state of the turn-on transient process circuit and obtain a second switch transient circuit model corresponding to the turn-on transient process circuit after the state update;

[0095] The layout optimization module 53 is used to extract the parasitic inductance parameters in the second switch transient circuit model using the ANSYS Q3D simulation tool, and perform multiple iterations of optimization on the copper layer shape and copper layer size of each power tube in the second switch transient circuit model through finite element simulation according to the common source inductance compensation function and the parasitic inductance parameters, so as to obtain an optimized layout solution for the circuit breaker power module.

[0096] In one example, the parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and positive lead terminals of each power tube in the circuit breaker power module, the parasitic inductance between the source and negative lead terminals of each power tube, and the coupling inductance between two parallel power tubes.

[0097] In one example, the conduction transient process circuit includes a circuit driving unit, a plurality of parallel switch units, a balanced voltage stabilizing unit, and a power supply, wherein:

[0098] The first common ends of the plurality of parallel switch units are respectively electrically connected to the first end of the circuit driving unit and one end of the balanced voltage stabilizing unit, and the second common ends of the plurality of parallel switch units are respectively electrically connected to the second end of the circuit driving unit and the other end of the balanced voltage stabilizing unit.

[0099] In one example, the parallel switch unit includes a first MOS tube, a second MOS tube, a first parasitic inductor, a second parasitic inductor and a common source inductor, wherein:

[0100] The gate of the first MOS tube is electrically connected to the first end of the circuit driving unit and the other parallel switch units respectively, the drain of the first MOS tube is electrically connected to one end of the first parasitic inductor, the other end of the first parasitic inductor is electrically connected to the other parallel switch units respectively, the source of the first MOS tube is electrically connected to one end of the common source inductor, the common end of the common source inductor and the second parasitic inductor is electrically connected to the third end of the circuit driving unit and the other parallel switch units respectively, the other end of the second parasitic inductor is electrically connected to the source of the second MOS tube, the gate of the second MOS tube is electrically connected to the second end of the circuit driving unit and the other parallel switch units respectively, and the drain of the first MOS tube is electrically connected to the other parallel switch units and one end of the balanced voltage stabilizing unit respectively.

[0101] In one example, the expression of the common source inductance compensation function is:

[0102] L Loop =L D +L com +L S

[0103]

[0104] Among them, L LOOP Represents the loop inductance of the parallel switch unit, L D It represents the parasitic inductance from the drain of the MOS tube to the positive lead-out terminal of the DC power supply, L S It represents the parasitic inductance from the source of the MOS tube to the negative lead-out terminal of the DC power supply, L com Represents the common source inductance value in the parallel switch unit, ΔI 1-2 represents the branch-to-branch circulating current between the first parallel switch unit and the second parallel switch unit in frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in frequency domain form, I d2 represents the drain current of the second parallel switch unit in frequency domain form, ΔI d1-2 It represents the difference of drain current between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL Loop1-2It represents the loop inductance difference between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL com It represents the difference in common source inductance between the first parallel switch unit and the nth parallel switch unit in frequency domain form, ΔL Loop The loop inductance difference between the first parallel switch unit and the nth parallel switch unit in frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, L com1 Represents the common source inductance value in the first parallel switch unit.

[0105] In one example, the layout optimization module 53 is used to import the second switch transient circuit model into the ANSYS Q3D simulation tool, set the material of the second switch transient circuit model to obtain the transition switch transient circuit model; perform meshing operations on the transition switch transient circuit model in turn, and set excitations corresponding to the current inflow end and the current outflow end of each grid in the transition switch transient circuit model; and perform simulation operations on the transition switch transient circuit model to obtain the inductance matrix corresponding to the transition switch transient circuit model and the parasitic inductance parameters in the transition switch transient circuit model.

[0106] In one example, each grid in the transition switch transient circuit model includes a plurality of current inflow terminals and a current outflow terminal, and the current inflow terminal and the current outflow terminal are edges or faces in the transition switch transient circuit model.

[0107] In one example, the balancing voltage-stabilizing unit includes a first voltage-stabilizing diode, a second voltage-stabilizing diode, and a load inductor, the positive electrode of the first voltage-stabilizing diode is electrically connected to the first common end of multiple parallel switch units and one end of the load inductor, the negative electrode of the first voltage-stabilizing diode is electrically connected to the negative electrode of the second voltage-stabilizing diode, the positive electrode of the second voltage-stabilizing diode is electrically connected to the second common end of the multiple parallel switch units and the negative electrode of the power supply, and the other end of the load inductor is electrically connected to the positive electrode of the power supply.

[0108] Based on the above method, an embodiment of the present application discloses a computer device, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of a circuit breaker power module layout optimization method based on multi-chip current sharing.

[0109] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit breaker power module layout optimization method based on multi-chip current sharing, characterized in that: The method comprises: Collecting parasitic parameters of the circuit breaker power module, and constructing a first switch transient circuit model according to the parasitic parameters; Based on the first switch transient circuit model and the conduction transient characteristics, construct a conduction transient process circuit; Performing current balancing on the conduction transient process circuit according to the common source inductance compensation function to update the state of the conduction transient process circuit, and obtaining a second switch transient circuit model corresponding to the conduction transient process circuit after the state update; The parasitic inductance parameters in the second switch transient circuit model are extracted by using the ANSYS Q3D simulation tool. According to the common source inductance compensation function and the parasitic inductance parameters, the copper layer shape and copper layer size of each power tube in the second switch transient circuit model are iteratively optimized multiple times through finite element simulation to obtain the optimized layout scheme of the circuit breaker power module.

2. The method according to claim 1, characterized in that The parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and positive lead terminals of each power tube in the circuit breaker power module, the parasitic inductance between the source and negative lead terminals of each power tube, and the coupling inductance between two parallel power tubes.

3. The method according to claim 1, characterized in that The conduction transient process circuit comprises a circuit driving unit (1), a plurality of parallel switch units (2), a balanced voltage stabilizing unit (3) and a power supply (4), wherein: The first common ends of the plurality of parallel switch units (2) are respectively electrically connected to the first end of the circuit drive unit (1), one end of the balanced voltage stabilizing unit (3) and the positive electrode of the power supply (4); the second common ends of the plurality of parallel switch units (2) are respectively electrically connected to the second end of the circuit drive unit (1), the other end of the balanced voltage stabilizing unit (3) and the negative electrode of the power supply (4); and the third common ends of the plurality of parallel switch units (2) are electrically connected to the third end of the circuit drive unit (1).

4. The method according to claim 3, characterized in that The parallel switch unit (2) comprises a first MOS tube, a second MOS tube, a first parasitic inductor, a second parasitic inductor and a common source inductor, wherein: The gate of the first MOS tube is electrically connected to the first end of the circuit driving unit (1) and the remaining parallel switch units (2), the drain of the first MOS tube is electrically connected to one end of the first parasitic inductor, the other end of the first parasitic inductor is electrically connected to the remaining parallel switch units (2), the source of the first MOS tube is electrically connected to one end of the common source inductor, the common end of the common source inductor and the second parasitic inductor is electrically connected to the third end of the circuit driving unit (1) and the remaining parallel switch units (2), the other end of the second parasitic inductor is electrically connected to the source of the second MOS tube, the gate of the second MOS tube is electrically connected to the second end of the circuit driving unit (1) and the remaining parallel switch units (2), and the drain of the first MOS tube is electrically connected to the remaining parallel switch units (2) and one end of the balanced voltage stabilizing unit (3).

5. The method according to claim 4, characterized in that The expression of the common source inductance compensation function is: L Loop =L D +L com +L S Among them, L LOOP Represents the loop inductance of the parallel switch unit, L D It represents the parasitic inductance from the drain of the MOS tube to the positive lead-out terminal of the DC power supply, L S It represents the parasitic inductance from the source of the MOS tube to the negative lead-out terminal of the DC power supply, L com Represents the common source inductance value in the parallel switch unit, ΔI 1-2 represents the branch-to-branch circulating current between the first parallel switch unit and the second parallel switch unit in frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in frequency domain form, I d2 represents the drain current of the second parallel switch unit in frequency domain form, ΔI d1-2 It represents the difference of drain current between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL Loop1-2 It represents the loop inductance difference between the first parallel switch unit and the second parallel switch unit in frequency domain form, ΔL com It represents the difference in common source inductance between the first parallel switch unit and the nth parallel switch unit in frequency domain form, ΔL Loop The loop inductance difference between the first parallel switch unit and the nth parallel switch unit in frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, L com1 Represents the common source inductance value in the first parallel switch unit.

6. The method according to claim 1, characterized in that The method of extracting the parasitic inductance parameters in the second switch transient circuit model using the ANSYS Q3D simulation tool specifically includes: Importing the second switch transient circuit model into the ANSYS Q3D simulation tool, and performing material setting on the second switch transient circuit model to obtain a transition switch transient circuit model; Performing mesh division operations on the transition switch transient circuit model in sequence, and setting excitations correspondingly to the current inflow end and the current outflow end of each mesh in the transition switch transient circuit model; A simulation operation is performed on the transition switch transient circuit model to obtain an inductance matrix corresponding to the transition switch transient circuit model and parasitic inductance parameters in the transition switch transient circuit model.

7. The method according to claim 6, characterized in that Each grid in the transition switch transient circuit model includes a plurality of current inflow ends and a current outflow end, and the current inflow end and the current outflow end are edges or faces in the transition switch transient circuit model.

8. The method according to claim 3, characterized in that The balancing voltage-stabilizing unit (3) comprises a first voltage-stabilizing diode, a second voltage-stabilizing diode and a load inductor, wherein the anode of the first voltage-stabilizing diode is electrically connected to the first common end of the plurality of parallel switch units and one end of the load inductor, the cathode of the first voltage-stabilizing diode is electrically connected to the cathode of the second voltage-stabilizing diode, the anode of the second voltage-stabilizing diode is electrically connected to the second common end of the plurality of parallel switch units and the negative electrode of the power supply, and the other end of the load inductor is electrically connected to the positive electrode of the power supply.

9. A circuit breaker power module layout optimization system based on multi-chip current sharing, characterized in that: The circuit breaker power module layout optimization system (5) comprises a circuit construction module (51), a current balancing module (52) and a layout optimization module (53), wherein: The circuit construction module (51) is used to collect parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a conduction transient process circuit based on the first switch transient circuit model and the conduction transient characteristics; The current balancing module (52) is used to perform current balancing on the conduction transient process circuit according to the common source inductance compensation function, so as to update the state of the conduction transient process circuit and obtain a second switch transient circuit model corresponding to the conduction transient process circuit after the state update; The layout optimization module (53) is used to extract parasitic inductance parameters in the second switch transient circuit model using an ANSYS Q3D simulation tool, and to perform multiple iterations of optimization on the copper layer shape and copper layer size of each power tube in the second switch transient circuit model through finite element simulation according to the common source inductance compensation function and the parasitic inductance parameters, so as to obtain an optimized layout solution for the circuit breaker power module.

10. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the circuit breaker power module layout optimization method based on multi-chip current sharing as described in any one of claims 1 to 8.

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