Precise circuit packaging substrate and manufacturing method thereof

Abstract

The invention provides a precise circuit packaging substrate and a manufacturing method thereof, and the method comprises the following steps: providing a substrate which comprises a core plate and a conductive metal layer at least disposed on the first surface of the core plate; forming a grain boundary buffer material layer on the surface, far away from the core plate, of the conductive metal layer, and pretreating the grain boundary buffer material layer to obtain a grain boundary buffer layer; providing an electroplating shielding layer, and forming a base circuit layer on the surface, away from the substrate, of the grain boundary buffer layer based on the electroplating shielding layer; at least one layer of wiring structure is formed on the surface, away from the substrate, of the base circuit layer, the wiring structure comprises a dielectric layer covering the exposed surface of the base circuit layer, a metal connecting layer penetrating through the dielectric layer and a conductive circuit layer located on the surface, away from the base circuit layer, of the dielectric layer, and the metal connecting layer is electrically connected with the base circuit layer and the conductive circuit layer. According to the precise circuit packaging substrate and the manufacturing method thereof, the problem of circuit separation in the process of manufacturing the precise circuit packaging substrate is avoided, and the yield of the packaging substrate is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a precision circuit packaging substrate and a manufacturing method thereof. Background Art

[0002] In order to meet the development of electronic products towards miniaturization, lightness, high performance and high reliability, PCB circuit design has gradually become more refined. The use of ETS (embedded trace substrate, referred to as ETS) process can meet the packaging needs of fine pitch (Pitch), and realize more refined circuit production based on the modified semi-additive process (mSAP) process. The substrate can be thinner and the surface is smoother, meeting the needs of light and thin consumer electronics. The reliability of the package is also better. At present, the commonly used lamination pre-treatment methods of mSAP process include browning, super coarsening and low micro-etching type treatment methods. Browning is the most mature and widely used process with the best product reliability. Most of the current low micro-etching lamination pre-treatments also require low-micro browning of the copper surface first, but due to the characteristics of the browning solution itself, it will bite too much at the copper grain boundary position, resulting in a significantly greater amount of bite at the copper grain boundary position than at the copper grain position. This leads to the limitation of the browning process on fine lines. After browning, the fine lines will float and drift, causing the line to break and open. In addition, the conventional semi-additive process (SAP) also requires pre-lamination treatment during the circuit manufacturing process, which may cause fine circuits to break and open after treatment.

[0003] Moreover, in the traditional actual production, among the three mainstream treatment methods of browning, super-roughening and low micro-etching, most of the low micro-etching treatments still need to be browned with a lower micro-etching amount in advance, and then the browned surface is specially treated to improve the bonding strength. Therefore, the current mainstream pre-lamination treatment is still mainly browning and super-roughening. Browning mainly attacks the grain boundary, and has less damage to the appearance of the circuit itself than super-roughening. Therefore, if browning can solve the problem of cracks separating fine circuits from base copper, browning will be able to prepare fine circuits normally, such as Figure 1 As shown in the figure, it is a schematic diagram of the structure after the base circuit layer is formed, including 01 substrate, 011 core board, 0111 substrate, 0112 dissociation layer, 012 conductive metal layer, 013 first surface, 014 second surface, 02 base circuit layer, and the base copper and circuit are separated after the browning or low micro-etching amount lamination pre-treatment containing the browning process. This problem will cause the circuit to float, shift or even break; it will also cause the dielectric layer to flow into the cracks during lamination, and subsequent flash etching cannot be performed. From this, it can be seen that the current conventional browning ETS process is not suitable for the production of fine circuits, especially the production of circuits with a line width of less than 10um.

[0004] In view of this, there is an urgent need for a method for manufacturing a precision circuit substrate that can effectively improve the problem of circuit separation and breakage during the fine circuit manufacturing process. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a precision circuit substrate and a method for manufacturing the same, so as to solve the problem of circuit separation and breakage during the fine circuit manufacturing process in the prior art.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a precision circuit substrate and a method for manufacturing the same, comprising the following steps:

[0007] Providing a substrate, the substrate comprising a core board and a conductive metal layer at least disposed on a first surface of the core board;

[0008] forming a grain boundary buffer material layer on a surface of the conductive metal layer away from the core plate, and pre-treating the grain boundary buffer material layer to obtain the grain boundary buffer layer;

[0009] Providing an electroplating shielding layer, and forming a base circuit layer on a surface of the grain boundary buffer layer away from the substrate based on the electroplating shielding layer;

[0010] At least one wiring structure is formed on the surface of the base wiring layer away from the substrate, and the wiring structure includes a dielectric layer covering the exposed surface of the base wiring layer, a metal connection layer penetrating the dielectric layer, and a conductive wiring layer located on the surface of the dielectric layer away from the base wiring layer, and the metal connection layer electrically connects the base wiring layer and the conductive wiring layer.

[0011] Optionally, a method of forming the grain boundary buffer material layer includes electroplating, sputtering, evaporation, and atomic layer deposition.

[0012] Optionally, forming the grain boundary buffer layer includes the following steps: forming a patterned first shielding layer on the surface of the grain boundary buffer material layer, and based on the patterned first shielding layer, sequentially performing plasma treatment and micro-etching treatment on the exposed surface of the grain boundary buffer material layer to obtain the grain boundary buffer layer.

[0013] Optionally, the surface roughness of the electroplating shielding layer is less than 200 μm.

[0014] Optionally, when the base circuit layer is formed based on the electroplating shielding layer, the current percentage used ranges from 30% to 90%.

[0015] Optionally, a multi-layer stacked wiring structure is formed in the packaging substrate, and in two adjacent wiring structures, the metal connection layer in the wiring structure away from the base wiring layer is electrically connected to the conductive wiring layer in the wiring structure close to the base wiring layer.

[0016] Optionally, the method of forming the wiring structure includes a modified semi-additive process.

[0017] Optionally, the wiring structure is formed by a modified semi-additive method, including the following steps: forming the dielectric layer covering the exposed surface of the base wiring layer, and forming a laminated metal layer on the surface of the dielectric layer, forming a through hole that penetrates the laminated metal layer and the dielectric layer and exposes the base wiring layer on the bottom surface, forming the metal connection layer electrically connected to the base wiring layer in the through hole, forming a patterned second shielding layer on the surface of the dielectric layer, forming a conductive wiring material layer on the surfaces of the dielectric layer and the metal connection layer based on the patterned second shielding layer, removing the second shielding layer and the core board in turn, forming an opening in the conductive wiring material layer after removing the second shielding layer, removing the laminated metal layer at the bottom of the opening to expose the dielectric layer, so as to obtain the conductive wiring layer.

[0018] Optionally, while removing the laminated metal layer at the bottom of the opening, the step also includes removing the conductive metal layer and the grain boundary buffer layer located on the surface of the base wiring layer away from the wiring structure.

[0019] Optionally, the method of forming the wiring structure includes a semi-additive process.

[0020] Optionally, the wiring structure is formed by a semi-additive method, including the following steps: forming the dielectric layer covering the exposed surface of the base wiring layer, forming a through hole that penetrates the dielectric layer and exposes the base wiring layer at the bottom, forming the metal connection layer electrically connected to the base wiring layer inside the through hole, and forming a buffer metal layer on the surface of the dielectric layer, forming a patterned third shielding layer on the surface of the buffer metal layer, forming the conductive wiring material layer on the surfaces of the dielectric layer and the metal connection layer based on the patterned third shielding layer, removing the third shielding layer and forming an opening in the conductive wiring material layer after removing the third shielding layer, and removing the buffer metal layer at the bottom of the opening to obtain the conductive wiring layer.

[0021] Optionally, after removing the buffer metal layer at the bottom of the opening, the method further includes the step of sequentially removing the core board and the conductive metal layer and the grain boundary buffer layer located on the surface of the base circuit layer away from the wiring structure.

[0022] The present invention also provides a precision circuit packaging substrate, wherein the packaging substrate is manufactured by using any one of the manufacturing methods for the precision circuit packaging substrate described above.

[0023] As described above, the precision circuit substrate and the manufacturing method thereof of the present invention have the following beneficial effects: by forming the grain boundary buffer layer having a lattice close to that of the base circuit layer on the surface of the conductive metal layer, the formed base circuit layer is obtained by continuing to grow on the original grains of the grain boundary buffer layer, and the roughening process can be effectively carried out while avoiding the problem of separation of the base circuit layer and the conductive metal layer after the roughening treatment, and also avoiding the problem of cracks during the roughening treatment, thereby realizing the production of a packaging substrate with fine circuits, improving the yield of the packaging substrate, and greatly reducing the cost and production capacity loss caused by equipment upgrades; in the process of forming the grain boundary buffer layer, the exposed surface of the grain boundary buffer material layer is plasma treated, thereby cleaning the surface of the grain boundary buffer material layer and reducing the influence of foreign matter, so that a cleaner surface can be obtained before forming the base circuit layer; the exposed surface of the grain boundary buffer material layer is micro-etched The treatment can further coarsen the surface of the grain boundary buffer material layer, which is beneficial to the tooth bonding ability between the surface of the grain boundary buffer layer and the surface of the base circuit layer, and can also further remove foreign matter on the surface of the grain boundary buffer material layer, thereby further improving the peeling resistance of the fine circuit. The method of forming the grain boundary buffer layer on the surface of the conductive metal layer is suitable for the production of fine circuits of various different packaging substrates, improves the compatibility with different processing processes, and is beneficial to the promotion and application of the production process of more types of fine packaging substrates. In addition, in the process of forming the base circuit layer and the conductive circuit layer, according to the corresponding process parameters, the corresponding electroplating shielding layer is provided, and the electroplating deposition rate at different positions in the electroplating process is regulated, thereby improving the uniformity of the formed base circuit layer and the conductive circuit layer. By providing the corresponding electroplating shielding layer, the production of different fine circuits is realized, and the yield of the packaging substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure after the base circuit layer is formed in the prior art.

[0025] Figure 2 Shown is a schematic diagram of the manufacturing process of the precision circuit packaging substrate of the present invention.

[0026] Figure 3 Shown is a schematic structural diagram of a base in the method for manufacturing a precision circuit packaging substrate of the present invention.

[0027] Figure 4It is a schematic diagram of the structure after the grain boundary buffer material layer is formed in the method for manufacturing the precision circuit packaging substrate of the present invention.

[0028] Figure 5 It is a schematic structural diagram showing the method for manufacturing a precision circuit packaging substrate of the present invention after exposing the first shielding material layer.

[0029] Figure 6 It is a schematic diagram of the structure after the grain boundary buffer layer is formed in the method for manufacturing the precision circuit packaging substrate of the present invention.

[0030] Figure 7 It is a schematic structural diagram showing the method for manufacturing a precision circuit packaging substrate of the present invention after forming a base circuit layer.

[0031] Figure 8 It is a schematic structural diagram showing the method for manufacturing a precision circuit packaging substrate of the present invention after removing the first shielding layer.

[0032] Fig. 9 It is a schematic diagram showing the structure after forming a laminated metal layer in the method for manufacturing a precision circuit packaging substrate of the present invention.

[0033] Fig.10 It is a schematic structural diagram showing the method for manufacturing a precision circuit packaging substrate of the present invention after forming a conductive circuit layer at the bottom layer.

[0034] Fig.11 It is a schematic structural diagram showing the method for manufacturing a precision circuit packaging substrate of the present invention after forming a wiring structure located at the top layer.

[0035] Fig.12 Shown is a structural schematic diagram of the method for manufacturing a precision circuit packaging substrate of the present invention, in which the core board is removed.

[0036] Fig.13 It is a schematic diagram showing the structure of the method for manufacturing a precision circuit packaging substrate of the present invention after removing the core board.

[0037] Fig.14 It is a schematic diagram showing the structure of the method for manufacturing a precision circuit packaging substrate of the present invention after removing the conductive metal layer and the grain boundary buffer layer.

[0038] Fig.15 Shown is a schematic structural diagram of the method for manufacturing a precision circuit packaging substrate of the present invention after forming a solder resist layer.

[0039] Component number description

[0040] 01 Base

[0041] 011 Core board

[0042] 0111 base plate

[0043] 0112 Dissociation layer

[0044] 012 Conductive metal layer

[0045] 013 First Surface

[0046] 014 Second Surface

[0047] 02 Base circuit layer

[0048] 1 Base

[0049] 11 Core board

[0050] 111 substrate

[0051] 112 Dissociation layer

[0052] 12 Conductive metal layer

[0053] 13 First Surface

[0054] 14 Second Surface

[0055] 2 Grain boundary buffer layer

[0056] 21 Grain boundary buffer material layer

[0057] 3 Base circuit layer

[0058] 4 Wiring structure

[0059] 41 Dielectric layer

[0060] 42 Metal connection layer

[0061] 43 Conductive circuit layer

[0062] 431 Conductive circuit material layer

[0063] 431a Opening

[0064] 5 First shielding layer

[0065] 51 first shielding material layer

[0066] 6 Laminated metal layers

[0067] 7 Through Holes

[0068] 8 Solder mask DETAILED DESCRIPTION

[0069] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0070] See also Figures 2 to 15 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0071] Embodiment 1

[0072] Figure 2 FIG. 1 is a schematic diagram of a manufacturing process of a precision circuit packaging substrate. This embodiment provides a method for manufacturing a precision circuit packaging substrate, comprising the following steps:

[0073] S1: providing a substrate, the substrate comprising a core board and a conductive metal layer at least disposed on a first surface of the core board;

[0074] S2: forming a grain boundary buffer material layer on a surface of the conductive metal layer away from the core plate, and pretreating the grain boundary buffer material layer to obtain the grain boundary buffer layer;

[0075] S3: providing an electroplating shielding layer, and forming a base circuit layer on a surface of the grain boundary buffer layer away from the substrate based on the electroplating shielding layer;

[0076] S4: forming at least one wiring structure on the surface of the base wiring layer away from the substrate, wherein the wiring structure includes a dielectric layer covering the exposed surface of the base wiring layer, a metal connection layer penetrating the dielectric layer, and a conductive wiring layer located on the surface of the dielectric layer away from the base wiring layer, wherein the metal connection layer electrically connects the base wiring layer and the conductive wiring layer.

[0077] For details, please refer to Figure 3 , perform step S1 to provide a substrate 1 , wherein the substrate 1 includes a core board 11 and a conductive metal layer 12 disposed at least on a first surface 13 of the core board 11 .

[0078] Specifically, Figure 3 , which is a schematic structural diagram of the substrate 1 , the core plate 11 includes a base plate 111 and a dissociation layer 112 disposed on the upper and lower surfaces of the base plate 111 .

[0079] Specifically, the material of the substrate 111 includes at least one of an inorganic material and an organic high molecular polymer material, and may also be other suitable materials.

[0080] Specifically, under the condition that the performance of the packaging substrate is met, the thickness and shape of the substrate 111 can be selected according to actual needs, and there is no limitation here.

[0081] Specifically, the substrate 111 effectively avoids the problems of warping and board jamming generated during the manufacturing process of the packaging substrate, and avoids the problem of low yield caused by deformation and board jamming of the substrate 111.

[0082] Specifically, the material of the dissociation layer 112 includes one of polyethylene terephthalate, polyethylene and OPP oriented polypropylene, and may also be other suitable adhesive materials.

[0083] Specifically, under the condition that the performance of the packaging substrate is met, the thickness and shape of the dissociation layer 112 can be selected according to actual needs, and there is no limitation here.

[0084] Specifically, the dissociation layer 112 has adhesive and easy-to-peel properties, so as to facilitate the removal of the core plate 11 .

[0085] Specifically, under the condition that the performance of the package substrate is met, the thickness and shape of the conductive metal layer 12 can be selected according to actual needs, and no limitation is made here. In this embodiment, the thickness of the conductive metal layer 12 ranges from 3 μm to 5 μm.

[0086] Specifically, the material of the conductive metal layer 12 includes copper or other suitable conductive materials.

[0087] Specifically, the base 1 is obtained by cutting raw materials and performing positioning drilling and edge sealing hole processing.

[0088] For details, please refer to Figure 4-Figure 15 , execute steps S2-S4, form a grain boundary buffer material layer 21 on the surface of the conductive metal layer 12 away from the core board 11, and pretreat the grain boundary buffer material layer 21 to obtain the grain boundary buffer layer 2; provide a plating shielding layer (not shown), and form a base wiring layer 3 on the surface of the grain boundary buffer layer 2 away from the substrate 1 based on the plating shielding layer; form at least one wiring structure 4 on the surface of the base wiring layer 3 away from the substrate 1, the wiring structure 4 includes a dielectric layer 41 covering the exposed surface of the base wiring layer 3, a metal connection layer 42 penetrating the dielectric layer 41, and a conductive wiring layer 43 located on the surface of the dielectric layer 41 away from the base wiring layer 3, and the metal connection layer 42 electrically connects the base wiring layer 3 and the conductive wiring layer 43.

[0089] As an example, Figure 4 , which is a schematic diagram of the structure after the grain boundary buffer material layer 21 is formed. The method of forming the grain boundary buffer material layer 21 includes electroplating or other suitable methods.

[0090] As an example, forming the grain boundary buffer layer 2 includes the following steps: forming a patterned first shielding layer 5 on the surface of the grain boundary buffer material layer 21, and based on the patterned first shielding layer 5, sequentially performing plasma treatment and micro-etching treatment on the exposed surface of the grain boundary buffer material layer 21 to obtain the grain boundary buffer layer 2, that is, pre-treating the grain boundary buffer material layer 21 includes sequentially performing plasma treatment and micro-etching treatment on the exposed surface of the grain boundary buffer material layer 21.

[0091] Specifically, Figure 5 As shown, it is a schematic diagram of the structure after the first shielding material layer 51 is exposed. The formation of the patterned first shielding layer 5 includes the following steps: forming the first shielding material layer 51 on the surface of the grain boundary buffer material layer 21, and sequentially exposing and developing the first shielding material layer 51 to obtain the patterned first shielding layer 5.

[0092] Specifically, before forming the first shielding material layer 51 on the surface of the grain boundary buffer material layer 21 , the process further includes performing a pre-filming treatment on the surface of the grain boundary buffer material layer 21 .

[0093] Specifically, the surface of the grain boundary buffer material layer 21 is subjected to a pre-film lamination treatment to enhance the bonding force between the first shielding material layer 51 and the surface of the grain boundary buffer material layer 21 .

[0094] Specifically, the exposed surface of the grain boundary buffer material layer 21 is plasma treated to clean the surface of the grain boundary buffer material layer 21 and reduce the influence of foreign matter, so that a cleaner surface can be obtained before forming the base circuit layer 3; the exposed surface of the grain boundary buffer material layer 21 is micro-etched to further coarsen the surface of the grain boundary buffer material layer 21, which is beneficial to enhance the tooth bonding ability between the surface of the grain boundary buffer layer 2 and the surface of the base circuit layer 3, and can also further remove foreign matter on the surface of the grain boundary buffer material layer 21, thereby further improving the peeling resistance of the fine circuit.

[0095] Specifically, the thickness of the formed grain boundary buffer material layer 21 is in the range of 2 μm to 4 μm.

[0096] Specifically, Figure 6 , which is a schematic diagram of the structure after the grain boundary buffer layer 2 is formed, the thickness of the grain boundary buffer material layer 21 removed by microetching is in the range of 0.3 μm to 0.8 μm. In this embodiment, the thickness of the grain boundary buffer material layer 21 removed by microetching is in the range of 0.5 μm.

[0097] Specifically, the material of the grain boundary buffer layer 2 includes copper, zinc, cobalt, palladium, chromium, nickel or other suitable conductive materials.

[0098] Specifically, Figure 7-Figure 8As shown, it is a schematic diagram of the structure after forming the base wiring layer 3 and a schematic diagram of the structure after removing the first shielding layer 5. The formation of the base wiring layer 3 includes the following steps: based on the patterned first shielding layer 5 and the electroplating shielding layer, a base wiring material layer 31 is formed on the surface of the grain boundary buffer layer 2 and the surface of the base wiring material layer 31 is roughened, and the patterned first shielding layer 5 is removed to obtain the base wiring layer 3.

[0099] Specifically, the method of forming the base wiring material layer 31 includes electroplating or other suitable methods.

[0100] Specifically, the electroplated shielding layer is manufactured based on the circuit pattern of the base circuit layer 3 and the process parameters required for forming the base circuit material layer 31 by electroplating. The shape of the openings on the electroplated shielding layer can be selected according to actual conditions.

[0101] Specifically, the method of forming the electroplating shielding layer includes 3D printing, metal micro-engraving technology, electroplating technology, mechanical milling and laser milling or other suitable methods.

[0102] As an example, the surface roughness of the electroplated shielding layer is less than 200 μm.

[0103] Specifically, the edge of the electroplated shielding layer needs to be kept smooth to avoid abnormal discharge problems when the base circuit material layer 31 is formed by electroplating.

[0104] As an example, when the base circuit layer 3 is formed based on the electroplating shielding layer, the current percentage range is 30% to 90%. That is, when the base circuit layer 3 is formed by electroplating, the current percentage at different positions can be controlled according to different liquid level differences, and the optimal percentage range is 30% to 90%.

[0105] Specifically, when the base circuit material layer 31 is formed by electroplating, the electroplated shielding layer is spaced apart from the substrate 1 by a preset distance.

[0106] Specifically, the base wiring material layer 31 is formed by electroplating, and the current percentage range at different positions is controlled according to different liquid level differences, thereby further controlling the electroplating deposition rate at different positions during the electroplating process, ensuring the uniformity of the formed base wiring material layer 31, providing a good base for the subsequent formation of a multi-layer wiring structure 4, and realizing the production of fine circuits.

[0107] Specifically, the method of roughening the surface of the base circuit material layer 31 includes browning, super roughening, low micro-etching or other suitable roughening methods.

[0108] As an example, a method of forming the wiring structure 4 includes a modified semi-additive method.

[0109] As an example, Figure 9-10As shown, they are schematic diagrams of the structure after forming the laminated metal layer 6 and the schematic diagram of the structure after forming the conductive circuit layer 43 located at the bottom. The improved semi-additive method for forming the wiring structure 4 includes the following steps: forming a dielectric layer 41 covering the exposed surface of the base circuit layer 3 and the grain boundary buffer layer 2, and forming the laminated metal layer 6 on the surface of the dielectric layer 41, forming a through hole 7 penetrating the laminated metal layer 6 and the dielectric layer 41 and exposing the base circuit layer 3 on the bottom surface, forming a metal connection layer 42 electrically connected to the base circuit layer 3 in the through hole 7, forming a patterned second shielding layer (not shown) on the surface of the dielectric layer 41, forming a conductive circuit material layer 431 on the surface of the dielectric layer 41 and the metal connection layer 42 based on the patterned second shielding layer, removing the second shielding layer and the core board 11 in sequence, and forming an opening 431a in the conductive circuit material layer 431 after removing the second shielding layer, removing the laminated metal layer 6 at the bottom of the opening 431a to expose the dielectric layer 41, so as to obtain the conductive circuit layer 43.

[0110] As an example, while removing the laminated metal layer 6 at the bottom of the opening 431 a , the step of removing the conductive metal layer 12 and the grain boundary buffer layer 2 located on the surface of the base wiring layer 3 away from the wiring structure 4 is also included.

[0111] Specifically, the thickness of the formed laminated metal layer 6 is in the range of 1 μm to 4 μm. It should be noted that the thickness of the formed laminated metal layer 6 can be selected according to the thickness of the grain boundary buffer layer 2 and the conductive metal layer 12. Since the thickness of the formed laminated metal layer 6 can be selected according to the thickness of the grain boundary buffer layer 2 and the conductive metal layer 12, the thickness of the laminated metal layer 6 can be kept consistent with the sum of the thickness of the grain boundary buffer layer 2 and the conductive metal layer 12, and the removal of the laminated metal layer 6, the grain boundary buffer layer 2 and the conductive metal layer 12 at the bottom of the opening 31 can be performed simultaneously.

[0112] Specifically, the method of removing the laminated metal layer 6 at the bottom of the opening 431 a includes flash etching or other suitable methods.

[0113] Specifically, the material of the laminated metal layer 6 includes copper or other suitable conductive materials.

[0114] Specifically, the method of forming the laminated metal layer 6 includes electroplating or other suitable methods.

[0115] Specifically, the method of forming the through hole 7 includes laser drilling or other suitable methods.

[0116] Specifically, the dielectric layer 41 also covers the surface of the grain boundary buffer layer 2 exposed in the gap in the base wiring layer 3 .

[0117] Specifically, the method of forming the metal connection layer 42 includes chemical vapor deposition or other suitable methods.

[0118] Specifically, after the metal connection layer 42 is formed and before the patterned second shielding layer 8 is formed, flash plating may be performed according to actual conditions to ensure that the conductive circuit material layer 431 meets the etching requirements.

[0119] Specifically, forming the patterned second shielding layer 8 includes the following steps: forming a second shielding material layer on the surfaces of the dielectric layer 41 and the metal connection layer 42 and sequentially exposing and developing the second shielding material layer to obtain the patterned second shielding layer 8 .

[0120] Specifically, the method of forming the conductive circuit layer 43 includes electroplating or other suitable methods.

[0121] Specifically, when the conductive circuit layer 43 is formed by electroplating, it also includes preparing and providing a corresponding electroplating shielding layer based on the circuit pattern of the conductive circuit layer 43 and the process parameters required for forming the conductive circuit layer 43 by electroplating.

[0122] Specifically, when the conductive circuit layer 43 is formed by electroplating, the method for forming the electroplating shielding layer, the shape of the surface openings, and the current percentage range at different positions can be selected according to actual conditions and are not limited here.

[0123] Specifically, by using the electroplating shielding layer in the process of forming the conductive circuit layer 43, the uniformity of the formed conductive circuit layer 43 is further ensured, thereby improving the yield rate of the packaging substrate.

[0124] As an example, Fig.11 , which is a schematic diagram of a structure after forming a wiring structure 4 located at the top layer, a multi-layer wiring structure 4 is formed in the package substrate, and in two adjacent wiring structures 4, the metal connection layer 42 in the wiring structure 4 far from the base wiring layer 3 is electrically connected to the conductive wiring layer 43 in the wiring structure 4 close to the base wiring layer 3. In this embodiment, a two-layer wiring structure 4 is formed.

[0125] Specifically, when a multi-layer wiring structure 4 is formed, the method for forming the multi-layer wiring structure 4 may refer to the above-mentioned method for forming the wiring structure 4, which will not be described in detail herein.

[0126] Specifically, Figure 12-13 As shown, they are respectively a schematic diagram of the structure without the core plate 11 and a schematic diagram of the structure after the core plate 11 is removed. The method of removing the core plate 11 includes mechanical separation or other suitable separation methods.

[0127] Specifically, Fig.14 , which is a schematic diagram of the structure after the conductive metal layer 12 and the grain boundary buffer layer 2 are removed. The method for removing the conductive metal layer 12 and the grain boundary buffer layer 2 includes flash etching or other suitable methods.

[0128] Specifically, after forming the wiring structure 4, a step of performing defect detection on the packaging substrate structure is also included.

[0129] Specifically, the method for performing defect detection on the package substrate structure after forming the wiring structure 4 includes one of automatic optical detection, 3D scanner scanning, laser confocal microscope scanning and white light interferometer detection.

[0130] Specifically, defect detection on the packaging substrate structure after the wiring structure 4 is formed can further ensure the yield of the formed packaging substrate, and defect detection can also further verify that forming a grain boundary buffer material layer 21 on the surface of the conductive metal layer 12 and pre-treating the grain boundary buffer material layer 21 to obtain a grain boundary buffer layer 2 can effectively improve the yield of the packaging substrate.

[0131] Specifically, after defect detection of the package substrate structure is performed, the step of forming a solder resist layer 8 on the surface of the base circuit layer 3 away from the wiring structure 4 is also included.

[0132] Specifically, Fig.15 , which is a schematic diagram of the structure after the solder resist layer 8 is formed, and the solder resist layer 8 includes green oil or other suitable solder resists.

[0133] Specifically, a grain boundary buffer layer 2 having a lattice close to that of the base wiring layer 3 is formed on the surface of the conductive metal layer 12, and the base wiring layer 3 is formed by continuing to grow on the original grains of the grain boundary buffer layer 2, thereby avoiding the problem of separation of the conductive metal layer 12 from the base wiring layer 3 due to the roughening treatment in the process of forming the base wiring layer 3, and also avoiding the problem of cracks in the roughening process, thereby realizing the production of a packaging substrate with fine circuits, improving the yield of the packaging substrate, and greatly reducing the cost and production capacity loss caused by equipment upgrades.

[0134] Specifically, a conductive metal layer 12, a grain boundary buffer layer 2, a base wiring layer 3 and at least one wiring structure 4 can also be formed on the second surface 14 of the core board 11, wherein the second surface 14 is arranged opposite to the first surface 13, and the conductive metal layer 12, the grain boundary buffer layer 2, the base wiring layer 3 and the wiring structure 4 are formed on the second surface 14 of the core board 11. The steps of forming the conductive metal layer 12, the grain boundary buffer layer 2, the base wiring layer 3 and the wiring structure 4 on the first surface 13 of the core board 11 can be referred to the above-mentioned steps of forming the conductive metal layer 12, the grain boundary buffer layer 2, the base wiring layer 3 and the wiring structure 4 on the first surface 13 of the core board 11, which will not be repeated here.

[0135] The method for manufacturing a fine circuit packaging substrate of the present embodiment forms a grain boundary buffer layer 2 on the surface of the conductive metal layer 12, which is close to the lattice of the base circuit layer 3. The formed base circuit layer 3 is obtained by continuing to grow on the original grains of the grain boundary buffer layer 2, thereby avoiding the problem of separation of the conductive metal layer 12 and the base circuit layer 3 caused by the roughening treatment in the process of forming the base circuit layer 3, and also avoiding the problem of cracks in the roughening process, thereby realizing the manufacture of a packaging substrate with fine circuits, improving the yield of the packaging substrate, and greatly reducing the cost and production capacity loss caused by the upgrading of equipment; in the process of forming the grain boundary buffer layer 2, the exposed surface of the grain boundary buffer material layer 21 is plasma treated, thereby cleaning the surface of the grain boundary buffer material layer 21 and reducing the influence of foreign matter, so that the formation The base circuit layer 3 can have a cleaner surface; micro-etching the exposed surface of the grain boundary buffer material layer 21 can further coarsen the surface of the grain boundary buffer material layer 21, which is beneficial to the tooth bonding ability between the surface of the grain boundary buffer layer 2 and the surface of the base circuit layer 3, and can also further remove foreign matter on the surface of the grain boundary buffer material layer 21, thereby further improving the anti-peel strength of the fine circuit. In addition, in the process of forming the base circuit layer 3 and the conductive circuit layer 43, a corresponding electroplating shielding layer is provided according to the corresponding process parameters, and the electroplating deposition rate at different positions during the electroplating process is regulated, thereby improving the uniformity of the formed base circuit layer 3 and the conductive circuit layer 43, and through the production of the corresponding electroplating shielding layer, the production of different fine circuits is realized, and the yield of the packaging substrate is improved.

[0136] Embodiment 2

[0137] The present embodiment provides a precision circuit packaging substrate. The precision circuit packaging substrate of the present embodiment is manufactured by the manufacturing method of the precision circuit packaging substrate described in the first embodiment.

[0138] Specifically, the precision circuit packaging substrate includes a stacked base circuit layer 3, at least one wiring structure 4 and a solder resist layer 8, wherein the wiring structure 4 includes a dielectric layer 41 covering the exposed surface of the base circuit layer 3, a metal connection layer 42 penetrating the dielectric layer 41, and a conductive circuit layer 43 located on the surface of the dielectric layer 41 away from the base circuit layer 3, the metal connection layer 42 electrically connects the base circuit layer 41 and the conductive circuit layer 43; the solder resist layer 8 is respectively located on the surface of the conductive metal layer 12 and the conductive circuit layer 43.

[0139] Specifically, a laminated metal layer 6 is further provided between the dielectric layer 41 and the conductive circuit layer 43 .

[0140] Specifically, the thickness of the laminated metal layer 6 is equal to the sum of the thicknesses of the grain boundary buffer layer 2 and the conductive metal layer 12 .

[0141] The precision circuit packaging substrate of this embodiment is manufactured by adopting the manufacturing method of the precision circuit packaging substrate described in the first embodiment, which realizes more precise circuit manufacturing and has a good packaging substrate yield.

[0142] Embodiment 3

[0143] This embodiment provides another method for manufacturing a precision circuit packaging substrate. The method for manufacturing a precision circuit packaging substrate in this embodiment is different from the method for manufacturing a precision circuit packaging substrate described in the first embodiment in that a method for forming the wiring structure 4 includes a semi-additive method.

[0144] As an example, when the wiring structure 4 is formed by the semi-additive method, the formation of the wiring structure 4 includes the following steps: forming a dielectric layer 41 covering the exposed surface of the base wiring layer 3, forming a through hole 7 that penetrates the dielectric layer 41 and exposes the base wiring layer 3 at the bottom, forming a metal connection layer 42 electrically connected to the base wiring layer 3 inside the through hole 7, and forming a buffer metal layer (not shown) on the surface of the dielectric layer 43, forming a patterned third shielding layer (not shown) on the surface of the buffer layer, forming a conductive wiring material layer 431 on the surface of the buffer metal layer based on the patterned third shielding layer, removing the third shielding layer and forming an opening 431a in the conductive wiring material layer 431 after removing the third shielding layer, and removing the buffer metal layer at the bottom of the opening 431a to obtain the conductive wiring layer 43.

[0145] Specifically, the method of forming the conductive circuit layer 43 includes electroplating or other suitable methods.

[0146] Specifically, when the conductive circuit layer 43 is formed by electroplating, it also includes preparing and providing a corresponding electroplating shielding layer based on the circuit pattern of the conductive circuit layer 43 and the process parameters required for forming the conductive circuit layer 43 by electroplating.

[0147] Specifically, when the conductive circuit layer 43 is formed by electroplating, the method for forming the electroplating shielding layer, the shape of the surface openings, and the current percentage range at different positions can be selected according to actual conditions and are not limited here.

[0148] Specifically, by using the electroplating shielding layer in the process of forming the conductive circuit layer 43, the uniformity of the formed conductive circuit layer 43 is further ensured, thereby improving the yield rate of the packaging substrate.

[0149] Specifically, the buffer metal layer at the bottom of the opening 431 a is removed based on the formed patterned fourth shielding layer (not shown).

[0150] As an example, after removing the buffer metal layer at the bottom of the opening 431a, the steps of sequentially removing the core board 11 and the conductive metal layer 12 and the grain boundary buffer layer 2 located on the surface of the base wiring layer 3 away from the wiring structure 4 are also included. It should be noted that the present embodiment adopts a semi-additive method to form the wiring structure 4, and the thickness of the formed buffer metal layer is less than the sum of the thicknesses of the conductive metal layer 12 and the grain boundary buffer layer 2. Therefore, the buffer metal layer at the bottom of the opening 431a, the conductive metal layer 12, and the grain boundary buffer layer 2 need to be removed in sequence.

[0151] Specifically, a grain boundary buffer layer 2 having a lattice close to that of the base wiring layer 3 is formed on the surface of the conductive metal layer 12, and the base wiring layer 3 is formed by continuing to grow on the original grains of the grain boundary buffer layer 2, thereby avoiding the problem of separation of the conductive metal layer 12 from the base wiring layer 3 due to the roughening treatment in the process of forming the base wiring layer 3, and also avoiding the problem of cracks in the roughening process, thereby realizing the production of a packaging substrate with fine circuits, improving the yield of the packaging substrate, and greatly reducing the cost and production capacity loss caused by equipment upgrades.

[0152] The method for manufacturing the precision circuit packaging substrate of the present embodiment forms a grain boundary buffer layer 2 on the surface of the conductive metal layer 12, which is close to the lattice of the base circuit layer 3. The formed base circuit layer 3 is obtained by continuing to grow on the original grains of the grain boundary buffer layer 2, thereby avoiding the problem of separation of the conductive metal layer 12 and the base circuit layer 3 caused by the roughening treatment in the process of forming the base circuit layer 3, and also avoiding the problem of cracks in the roughening process, thereby realizing the production of packaging substrates with fine circuits, improving the yield of packaging substrates, and greatly reducing the cost and production capacity loss caused by equipment upgrades. In addition, the grain boundary buffer layer 2 formed on the surface of the conductive metal layer 12 is suitable for the production of fine circuits of a variety of different packaging substrates, thereby improving the compatibility with different processing processes, which is conducive to the promotion and application of the production process of more types of refined packaging substrates.

[0153] Embodiment 4

[0154] The present embodiment provides a precision circuit packaging substrate. The precision circuit packaging substrate of the present embodiment is manufactured by the manufacturing method of the precision circuit packaging substrate described in the third embodiment.

[0155] Specifically, the precision circuit packaging substrate includes a stacked base circuit layer 3, at least one wiring structure 4 and a solder resist layer 10, wherein the wiring structure 4 includes a dielectric layer 41 covering the exposed surface of the base circuit layer 3, a metal connection layer 42 penetrating the dielectric layer 41, and a conductive circuit layer 43 located on the surface of the dielectric layer 41 away from the base circuit layer 3, the metal connection layer 42 electrically connects the base circuit layer 41 and the conductive circuit layer 43; the solder resist layer 8 is respectively located on the surface of the conductive metal layer 12 and the conductive circuit layer 43.

[0156] Specifically, a buffer metal layer is further provided between the dielectric layer 41 and the conductive circuit layer 43 .

[0157] Specifically, the thickness of the buffer metal layer is less than the sum of the thicknesses of the grain boundary buffer layer 2 and the conductive metal layer 12 .

[0158] The precision circuit packaging substrate of this embodiment is manufactured by adopting the manufacturing method of the precision circuit packaging substrate described in the third embodiment, which realizes more precise circuit manufacturing and has a good packaging substrate yield.

[0159] In summary, the precision circuit packaging substrate and its manufacturing method of the present invention form a grain boundary buffer layer on the surface of the conductive metal layer with a lattice close to that of the base circuit layer. The formed base circuit layer is obtained by continuing to grow on the original grains of the grain boundary buffer layer. While being able to effectively carry out the roughening process, the problem of separation of the base circuit layer and the conductive metal layer after the roughening process is avoided, and the problem of cracks during the roughening process is avoided, thereby realizing the production of packaging substrates with fine circuits, improving the yield of packaging substrates, and greatly reducing the cost and production capacity loss caused by equipment upgrades; in the process of forming the grain boundary buffer layer, the exposed surface of the grain boundary buffer material layer is plasma treated, thereby cleaning the surface of the grain boundary buffer material layer and reducing the influence of foreign matter, so that a cleaner surface can be obtained before forming the base circuit layer; the exposed surface of the grain boundary buffer material layer is micro-etched, which can Further coarsening the surface of the grain boundary buffer material layer is beneficial to the bonding ability between the surface of the grain boundary buffer layer and the surface of the base circuit layer, and can also further remove foreign matter on the surface of the grain boundary buffer material layer, thereby further improving the peeling resistance of the fine circuit. The method of forming a grain boundary buffer layer on the surface of the conductive metal layer is suitable for the production of fine circuits of various different packaging substrates, improving the compatibility with different processing processes, and is conducive to the promotion and application of the production process of more types of fine packaging substrates. In addition, in the process of forming the base circuit layer and the conductive circuit layer, according to the corresponding process parameters, a corresponding electroplating shielding layer is provided, and the electroplating deposition rate at different positions in the electroplating process is regulated, thereby improving the uniformity of the formed base circuit layer and the conductive circuit layer. By making the corresponding electroplating shielding layer, the production of different fine circuits is realized, and the yield of the packaging substrate is improved. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0160] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a fine circuit packaging substrate, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a core board and a conductive metal layer at least disposed on a first surface of the core board; forming a grain boundary buffer material layer on a surface of the conductive metal layer away from the core plate, and pre-treating the grain boundary buffer material layer to obtain the grain boundary buffer layer; Providing an electroplating shielding layer, and forming a base circuit layer on a surface of the grain boundary buffer layer away from the substrate based on the electroplating shielding layer; At least one wiring structure is formed on the surface of the base wiring layer away from the substrate, and the wiring structure includes a dielectric layer covering the exposed surface of the base wiring layer, a metal connection layer penetrating the dielectric layer, and a conductive wiring layer located on the surface of the dielectric layer away from the base wiring layer, and the metal connection layer electrically connects the base wiring layer and the conductive wiring layer.

2. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: Methods for forming the grain boundary buffer material layer include electroplating, sputtering, evaporation, and atomic layer deposition.

3. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: Forming the grain boundary buffer layer includes the following steps: forming a patterned first shielding layer on the surface of the grain boundary buffer material layer, and based on the patterned first shielding layer, sequentially performing plasma treatment and micro-etching treatment on the exposed surface of the grain boundary buffer material layer to obtain the grain boundary buffer layer.

4. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: The surface roughness of the electroplating shielding layer is less than 200 μm.

5. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: When the base circuit layer is formed based on the electroplating shielding layer, the current percentage range used is 30% to 90%.

6. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: A multi-layered wiring structure is formed in the packaging substrate, and in two adjacent wiring structures, the metal connection layer in the wiring structure away from the base wiring layer is electrically connected to the conductive wiring layer in the wiring structure close to the base wiring layer.

7. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: The method of forming the wiring structure includes a modified semi-additive process.

8. The method for manufacturing a fine circuit packaging substrate according to claim 7, characterized in that: The wiring structure is formed by a modified semi-additive method, and the following steps are included: forming the dielectric layer covering the exposed surface of the base wiring layer, and forming a laminated metal layer on the surface of the dielectric layer, forming a through hole that penetrates the laminated metal layer and the dielectric layer and exposes the base wiring layer on the bottom surface, forming the metal connection layer electrically connected to the base wiring layer in the through hole, forming a patterned second shielding layer on the surface of the dielectric layer, forming a conductive wiring material layer on the surfaces of the dielectric layer and the metal connection layer based on the patterned second shielding layer, removing the second shielding layer and the core board in turn, forming an opening in the conductive wiring material layer after removing the second shielding layer, removing the laminated metal layer at the bottom of the opening to expose the dielectric layer, and obtaining the conductive wiring layer.

9. The method for manufacturing a fine circuit packaging substrate according to claim 8, characterized in that: While removing the laminated metal layer at the bottom of the opening, the method also includes removing the conductive metal layer and the grain boundary buffer layer located on the surface of the base wiring layer away from the wiring structure.

10. The method for manufacturing a fine circuit packaging substrate according to claim 1, characterized in that: A method of forming the wiring structure includes a semi-additive method.

11. The method for manufacturing a fine circuit packaging substrate according to claim 10, characterized in that: The wiring structure is formed by a semi-additive method, and the following steps are included: forming the dielectric layer covering the exposed surface of the base wiring layer, forming a through hole penetrating the dielectric layer and exposing the base wiring layer at the bottom, forming the metal connection layer electrically connected to the base wiring layer inside the through hole, and forming a buffer metal layer on the surface of the dielectric layer, forming a patterned third shielding layer on the surface of the buffer metal layer, forming the conductive wiring material layer on the surfaces of the dielectric layer and the metal connection layer based on the patterned third shielding layer, removing the third shielding layer, and forming an opening in the conductive wiring material layer after removing the third shielding layer, and removing the buffer metal layer at the bottom of the opening to obtain the conductive wiring layer.

12. The method for manufacturing a fine circuit packaging substrate according to claim 11, characterized in that: After removing the buffer metal layer at the bottom of the opening, the method further includes the steps of sequentially removing the core board and the conductive metal layer and the grain boundary buffer layer located on the surface of the base circuit layer away from the wiring structure.

13. A precision circuit packaging substrate, characterized in that: The packaging substrate is manufactured by using the manufacturing method of the precision circuit packaging substrate as claimed in any one of claims 1 to 12.

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