Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which comprises a device layer, an embedded power rail and a silicon through hole, and the silicon through hole is connected with the device layer through the embedded power rail; the power supply network layer is arranged on the substrate, the power supply network layer comprises at least one layer of first power supply array and at least one layer of second power supply array, and the first power supply array is connected with the embedded power supply rail through a silicon through hole; and the capacitor structure is arranged between the first power supply array and the second power supply array and is respectively connected with the first power supply array and the second power supply array through a lower electrode and an upper electrode of the capacitor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In traditional chip manufacturing and 2.5D or 3D advanced packaging, signal lines and power lines are generally wired on the front side of the wafer, and are stacked and connected vertically to form a semiconductor device with active electronic components of a multi-layer metal interconnection structure of an integrated circuit. This method has both a signal interconnection network and a power supply network formed by signal lines in the front area of ​​the chip, making it difficult to further reduce the volume of the entire packaging structure. Based on this, a chip structure with a back side power supply network (BSPDN) is proposed to overcome the defects of the front side power supply structure, but some new problems are introduced. For example, due to the limitation of the power conduction path, the voltage drop effect causes high chip energy consumption. Based on the back side power supply technology, how to further optimize the chip structure and shorten the power conduction path to improve device performance has become an urgent problem to be solved. Summary of the invention

[0003] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, including:

[0004] A substrate, comprising a device layer, an embedded power rail and a through silicon via, wherein the through silicon via is connected to the device layer through the embedded power rail;

[0005] A power network layer, arranged on the substrate, the power network layer comprising at least one first power array and at least one second power array, the first power array being connected to the embedded power rail through the through silicon via;

[0006] The capacitor structure is disposed between the first power array and the second power array, and is connected to the first power array and the second power array respectively through a lower electrode and an upper electrode of the capacitor structure.

[0007] In some embodiments, the first power array extends along a first direction, the second power array extends along a second direction, the first direction intersects with the second direction in a direction parallel to the substrate, and projections of the first power array and the second power array in a direction perpendicular to the substrate have overlapping portions.

[0008] In some embodiments, the first power array and the second power array each include at least two power lines and at least two ground lines, the at least two power lines and at least two ground lines of the first power array are parallel to each other and staggered along the second direction, and the at least two power lines and at least two ground lines of the second power array are parallel to each other and staggered along the first direction.

[0009] In some embodiments, the overlapping portion of the projections of the first power array and the second power array in a direction perpendicular to the substrate includes at least one first area and at least one second area, the first area being the overlapping portion of the projections of the power lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate and the overlapping portion of the projections of the ground lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate; the second area being the overlapping portion of the projections of the ground lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate and the overlapping portion of the projections of the power lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate.

[0010] In some embodiments, a contact plug is further provided between the first power array and the second power array. The contact plug is provided in the first region and is used to connect the power line of the first power array with the power line of the second power array or to connect the ground line of the first power array with the ground line of the second power array.

[0011] In some embodiments, the capacitor structure is disposed in the second region, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

[0012] In some embodiments, the number of the power lines and the ground lines of the first power array is the same, and the number of the power lines and the ground lines of the second power array is the same.

[0013] In some embodiments, the spacing between adjacent power line rows and ground line rows is in a range of 0.1-1.5 μm.

[0014] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for preparing a semiconductor structure, comprising:

[0015] Providing a substrate, wherein a device layer, an embedded power rail and a through silicon via are formed in the substrate, wherein the through silicon via is connected to the device layer through the embedded power rail;

[0016] The power network layer and the capacitor structure are formed on the substrate, the power network layer includes at least one first power array and at least one second power array, the first power array is connected to the buried power rail through the through silicon via, the capacitor structure is formed between the first power array and the second power array, and is connected to the first power array and the second power array through the lower electrode and the upper electrode of the capacitor structure respectively.

[0017] In some embodiments, the step of forming the power network layer and the capacitor structure on the substrate includes:

[0018] The substrate has a first surface and a second surface, an isolation layer is formed on the first surface of the substrate, and the first power array is formed in the patterned isolation layer, the first power array extends along a first direction, and the first power array includes at least two power lines and at least two ground lines; an insulating layer is deposited on the isolation layer and the first power array, and the insulating layer is patterned, and the patterned insulating layer exposes part of the power lines and the ground lines of the first power array; the capacitor structure, the contact plug and the second power array are sequentially formed in the patterned insulating layer, the second power array extends along a second direction, and the second power array includes at least two power lines and at least two ground lines, the first direction intersects with the second direction in a direction parallel to the substrate, the projections of the first power array and the second power array in a direction perpendicular to the substrate partially overlap, and the contact plug and the capacitor structure are connected between the first power array and the second power array.

[0019] In some embodiments, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

[0020] In some embodiments, the contact plug is used to connect the power line of the first power array with the power line of the second power array, or to connect the ground line of the first power array with the ground line of the second power array.

[0021] In some embodiments, the insulating layer includes a first barrier layer, a first insulating layer, a second barrier layer and a second insulating layer, and the capacitor structure, the contact plug and the second power array are formed in sequence in the patterned insulating layer, including: depositing the first barrier layer and the first insulating layer, patterning the first barrier layer and the first insulating layer to form a first groove, the first groove exposing a portion of the power line or the ground line of the first power array; depositing the lower electrode, the dielectric layer, the barrier layer and the upper electrode in the first groove in sequence, the lower electrode, the dielectric layer, the barrier layer and the upper electrode constitute the capacitor structure, and the lower electrode is connected to the power line or the ground line of the first power array; depositing the second barrier layer and the second insulating layer, patterning the first barrier layer, the first insulating layer, the second barrier layer and the second insulating layer to form a second groove, the second groove exposing a portion of the power line or the ground line of the first power array and the upper electrode of the capacitor structure; depositing a conductive material layer in the second groove to form the contact plug and the second power array.

[0022] In some embodiments, the device layer, the embedded power rail and the through silicon via are formed in the substrate, including: forming the through silicon via in the substrate, the through silicon via passing through the first surface and the second surface of the substrate; and sequentially forming the embedded power rail and the device layer on the second surface of the substrate.

[0023] In some embodiments, after forming the device layer in the substrate, the method further includes forming a signal interconnection layer on the device layer.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0025] The disclosed embodiment integrates the capacitor structure into the power supply network, thereby improving the voltage stabilization effect without adding an additional capacitor structure, thereby reducing the size of the chip; on the other hand, since the power network can be directly connected to the capacitor structure internally, the power supply path is shortened, thereby reducing the transmission resistance and further enhancing the stability and reliability of the power network. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A top view of a power network layer provided in accordance with an embodiment of the present disclosure.

[0028] Figure 2 An embodiment of the present disclosure provides an edge Figure 1 A cross-sectional view of a portion of the semiconductor structure along the AA' direction.

[0029] Figure 3 A flowchart of a semiconductor manufacturing method provided in one embodiment of the present disclosure.

[0030] Figure 4 Another flow chart of a semiconductor manufacturing method provided in accordance with an embodiment of the present disclosure.

[0031] Figure 5 Another flow chart of a semiconductor manufacturing method provided by an embodiment of the present disclosure.

[0032] Figures 6 to 13 The corresponding edges of each step of a semiconductor manufacturing method provided in one embodiment of the present disclosure are Figure 1 A cross-sectional view of a portion of the semiconductor structure along the AA' direction. DETAILED DESCRIPTION

[0033] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0034] Backside Power Delivery Network (BSPDN) is a chip design method that aims to solve the RC (parasitic resistance and parasitic capacitance) bottleneck and wiring congestion problems caused by the sharing of interconnection resources between signal lines and power lines in traditional front-side wiring by moving the power lines to the back of the wafer. This approach not only eliminates the need for power supply tracks on the front side, but also allows for more economical strategies in interconnect scaling, thereby saving costs. However, the introduction of BSPDN also brings some new challenges, the most notable of which is the voltage drop effect caused by the limitation of the power conduction path, which increases the energy consumption of the chip and affects the overall performance.

[0035] In order to solve the above technical problems, an embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by the embodiment of the present disclosure will be described below in conjunction with the accompanying drawings.

[0036] Figure 1 A top view of a power network layer provided in accordance with an embodiment of the present disclosure; Figure 2 An embodiment of the present disclosure provides an edge Figure 1 A cross-sectional view of a portion of the semiconductor structure along the AA' direction in FIG. 1 is shown in FIG. 1 . The semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings.

[0037] refer to Figure 1 and Figure 2 The semiconductor structure 10 includes: a substrate 101, the substrate 101 includes a device layer 103, a buried power rail BPR and a through silicon via 102, the through silicon via 102 is connected to the device layer 104 through the buried power rail 103; a power network layer 104, arranged on the substrate 101, the power network layer 104 includes at least one layer of a first power array 1041 and at least one layer of a second power array 1042, the first power array 1041 is connected to the buried power rail BPR through the through silicon via 102; a capacitor structure 108, arranged between the first power array 1041 and the second power array 1042, and connected to the first power array 1041 and the second power array 1042 through a lower electrode 1081 and an upper electrode 1084 of the capacitor structure 108 respectively.

[0038] In some embodiments, the material of the substrate 101 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. The substrate 101 may also include a device layer 103 for forming chip devices, and the device layer 103 may include active devices such as transistors or diodes, or passive devices such as capacitors, inductors, resistors, etc. A signal interconnect layer SL may also be provided below the device layer 103 to connect the device layer 103 to an external control signal or an input / output signal. A buried power rail BPR may also be provided in the substrate 101 as an interconnect line to which a power supply voltage or a ground voltage is applied.

[0039] In some embodiments, reference Figure 1 and Figure 2 , the first power array 1041 extends along a first direction Y, the second power array extends along a second direction X, the first direction Y intersects with the second direction X in a direction parallel to the substrate 101, and the projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 have overlapping parts, wherein the intersection of the first direction Y and the second direction X in a direction parallel to the substrate 101 may be a vertical intersection or may be set to intersect at other angles as required, which is not limited here. Exemplarily, the power network layer 104 may include at least one first power array 1041 and at least one second power array 1042, and the planes where the different power arrays are located are parallel to the substrate 101 and are located in different layers. In this embodiment, the second power array 1042 may be arranged above the first power array 1041, and the projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 have an intersecting part.

[0040] In some embodiments, reference Figure 1 and Figure 2, the first power array 1041 and the second power array 1042 each include at least two power lines Vdd and at least two ground lines Vss, the at least two power lines Vdd and at least two ground lines Vss of the first power array 1041 are parallel to each other and staggered along the second direction X, and the at least two power lines Vdd and at least two ground lines Vss of the second power array 1042 are parallel to each other and staggered along the first direction Y. Exemplarily, in a direction parallel to the substrate 101, the first power array 1041 includes multiple power lines Vdd and multiple ground lines V ss, wherein each power line Vdd and each ground line Vss are arranged alternately along the second direction X, and the second power array 1042 also includes multiple power lines Vdd and multiple ground lines Vss, wherein each power line Vdd and each ground line Vss are arranged alternately along the first direction Y, that is, the multiple power lines Vdd and the multiple ground lines Vss in the first power array 1041 and the multiple power lines Vdd and the multiple ground lines Vss in the second power array 1042 are perpendicular to each other, and there is an overlapping part in the projection in the direction perpendicular to the substrate 101. The power lines Vdd and ground lines Vss in the first power array 1041 and the power lines Vdd and ground lines Vss in the second power array 1042 are arranged in layers, and the power lines Vdd and ground lines Vss in each layer are staggered to reduce the voltage drop and signal interference between the power lines Vdd and the ground lines Vss, thereby improving the performance and reliability of the circuit, wherein the first power array 1041 is arranged in an isolation layer 105, the material of the isolation layer 105 can be silicon oxide (SiO2), which is used to isolate adjacent power lines Vdd and ground lines Vss.

[0041] In some embodiments, the shapes of the power line Vdd and the ground line Vss can be set to rectangle, square, circle, polygon, serpentine, star or other shapes as needed, which are not limited here. Exemplarily, the power line Vdd and the ground line Vss are designed to be rectangular or square to provide a large area of ​​low impedance path, which helps to reduce voltage drop and electromagnetic interference. They can also be designed to be serpentine as required. The serpentine line can increase the length of the line by changing the direction of the line, which helps to match the length of the signal line and improve signal integrity.

[0042] In some embodiments, continue to refer to Figure 1 and Figure 2, the overlapping part of the projection of the first power array 1041 and the second power array 1042 in the direction perpendicular to the substrate 101 includes at least one first region I and at least one second region II, wherein the first region I is the overlapping part of the projection of the power line Vdd of the first power array 1041 and the power line Vdd of the second power array 1042 in the direction perpendicular to the substrate 101, and the overlapping part of the projection of the ground line Vss of the first power array 1041 and the ground line Vss of the second power array 1042 in the direction perpendicular to the substrate 101; the second region II is the overlapping part of the projection of the ground line Vss of the first power array 1041 and the power line Vdd of the second power array 1042 in the direction perpendicular to the substrate 101, and the overlapping part of the projection of the power line Vdd of the first power array 1041 and the ground line Vss of the second power array 1042 in the direction perpendicular to the substrate 101. Exemplarily, with reference to Figure 1 The first region I and the second region II are arranged alternately along the first direction Y and the second direction X, that is, the first region I and the second region II are arranged adjacent to each other in the first direction Y and the second direction X, and the areas of the first region I and the second region II along the direction parallel to the substrate 101 can be the same or different.

[0043] In some embodiments, reference Figure 1 and Figure 2 A contact plug CT is also provided between the first power array 1041 and the second power array 1042. The contact plug CT is provided in the first area I and is used to connect the power line Vdd of the first power array 1041 with the power line Vdd of the second power array 1042, or to connect the ground line Vss of the first power array 1041 with the ground line Vss of the second power array 1042.

[0044] In some embodiments, the shape of the contact plug CT can be set to a rectangle, square, circle, polygon, star or other shapes as required, which is not limited here. The number of contact plugs CT can also be set to an integer as required, for example, 1, 2, 3...10, which is not limited here. The material of the contact plug CT includes but is not limited to one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn) or their alloys.

[0045] In some embodiments, reference Figure 1 and Figure 2, the capacitor structure 108 is arranged in the second area II, the lower electrode 1081 of the capacitor structure 108 is connected to the power line Vdd of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the ground line Vss of the second power array 1042; or, the lower electrode 1081 of the capacitor structure 108 is connected to the ground line Vss of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the power line Vdd of the second power array 1042. Exemplarily, the second power array 1042, the capacitor structure 108 and the contact plug CT are all arranged in the insulating layer 106, wherein the insulating layer 106 includes a first barrier layer 1061, a first insulating layer 1062, a second barrier layer 1063 and a second insulating layer 1064, which are used to isolate and support the second power array 1042, the capacitor structure 108 and the contact plug CT, wherein the material of the first barrier layer 1061 and the second barrier layer 1063 may include silicon nitride (SiN), and the material of the first insulating layer 1062 and the second insulating layer 1063 may include silicon oxide (SiO2). The capacitor structure 108 includes a lower electrode 1081, a dielectric layer 1082, a barrier layer 1083, and an upper electrode 1084, wherein the materials of the lower electrode 1081 and the upper electrode 1084 of the capacitor structure 108 may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and molybdenum (Mo), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN)) The material of the dielectric layer 1082 may include metal oxides (for example, one or more of HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and TiO2, and may have a single-layer structure or a multi-layer structure, and the barrier layer 1083 may include metal nitrides, for example, one or more of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) and tungsten nitride (WN)).

[0046] By integrating the capacitor structure 108 into the power supply network layer 104, the voltage stabilization effect can be improved without adding an additional capacitor structure, thereby reducing the volume of the semiconductor structure; on the other hand, since the power supply network 104 can be directly connected to the capacitor structure 108 internally, the power supply path is shortened, thereby reducing the transmission resistance and further enhancing the stability and reliability of the power supply network.

[0047] In some embodiments, reference Figure 1 and Figure 2The number of power lines Vdd and ground lines Vss in the first power array 1041 is the same, and the number of power lines Vdd and ground lines Vss in the second power array 1042 is the same, so as to maintain the balance of the circuit and ensure that the current distribution between the power lines Vdd and the ground lines Vss is uniform, thereby reducing voltage drop and signal interference, which is conducive to maintaining the stability and reliability of the circuit.

[0048] In some embodiments, reference Figure 1 and Figure 2 The spacing W between adjacent power lines Vdd and ground lines Vss ranges from 0.1 μm to 1.5 μm, which is beneficial for reducing the size of the circuit and avoiding crosstalk between the power lines Vdd and the ground lines Vss, so as to achieve the best performance and cost balance of the semiconductor structure 10.

[0049] Accordingly, another embodiment of the present disclosure provides a method for preparing a semiconductor structure. Figure 3 A flowchart of a semiconductor manufacturing method provided in one embodiment of the present disclosure; Figure 4 Another flow chart of a semiconductor manufacturing method provided in one embodiment of the present disclosure; Figure 5 Another flow chart of a semiconductor manufacturing method provided in one embodiment of the present disclosure; Figures 6 to 13 The corresponding edges of each step of a semiconductor manufacturing method provided in one embodiment of the present disclosure are Figure 1 The cross-sectional view of a part of the semiconductor structure in the AA' direction in FIG.

[0050] refer to Figure 3 , an embodiment of the present disclosure provides a method for preparing a semiconductor structure 10, comprising:

[0051] S100 provides a substrate 101 , in which a device layer 103 , a buried power rail BPR and a through silicon via 102 are formed. The through silicon via 102 is connected to the device layer 103 through the buried power rail BPR.

[0052] In some embodiments, reference Figure 6-Figure 7, a device layer 103, a buried power rail BPR and a through silicon via 102 are formed in the substrate 101, including: forming a through silicon via 102 in the substrate 101, the through silicon via 102 penetrating the first surface S1 and the second surface S2 of the substrate 101; sequentially forming a buried power rail BPR and a device layer 103 on the second surface S2 of the substrate 101. Exemplarily, the material of the substrate 101 can be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V compounds such as gallium arsenide. A patterned substrate 101 is provided, and a conductive material is deposited in the substrate 101 to form a through silicon via 102, wherein the through silicon via 102 penetrates the first surface S1 and the second surface S2 of the substrate 101; a buried power rail BPR and a device layer 103 are continuously formed on the substrate with the through silicon via 102 formed thereon. In other embodiments, the device layer 103 and the buried power rail BPR may be formed first and then the through silicon via 102 is formed. The formation sequence is not limited herein. Active devices such as transistors or diodes, or passive devices such as capacitors, inductors, resistors, etc. may be formed in the device layer 103; the buried power rail BPR may also be formed in the substrate 101 as an interconnection line to which a power supply voltage or a ground voltage is applied. Specifically, after the device in the device layer 103 is formed, an opening may be formed by patterning the device layer 103, and a conductive material may be deposited in the opening, and the formation may be performed after chemical mechanical polishing.

[0053] In some embodiments, reference Figure 7 After the device layer 103 is formed in the substrate 101, a signal interconnection layer SL is formed on the device layer 103 to connect the device layer 103 with an external control signal or an input / output signal. The preparation of the signal interconnection layer SL can be completed by a Damascene process to form a signal interconnection layer SL having multiple layers of metal and multiple layers of dielectric materials. The material of the signal interconnection layer SL may include one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn) or their alloys.

[0054] S200 forms a power network layer 104 and a capacitor structure 108 on a substrate 101. The power network layer 104 includes at least one first power array 1041 and at least one second power array 1042. The first power array 1041 is connected to a buried power rail BPR through a through silicon via 102. The capacitor structure 108 is formed between the first power array 1041 and the second power array 1042, and is connected to the first power array 1041 and the second power array 1042 respectively through a lower electrode 1081 and an upper electrode 1084 of the capacitor structure 108.

[0055] In some embodiments, reference Figure 2-Figure 4 as well as Figure 8-Figure 13 The step of forming a power network layer 104 and a capacitor structure 108 on the substrate 101 includes:

[0056] S210 The substrate 101 has a first surface S1 and a second surface S2. An isolation layer 105 is deposited on the first surface S1 of the substrate 101. A first power array 1041 is deposited in the patterned isolation layer 105. The first power array 1041 extends along a first direction Y, and the first power array 1041 includes at least two power lines Vdd and at least two ground lines Vss. The process of depositing the isolation layer 105 includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electrochemical deposition (ECD), and the material of the isolation layer 105 may be silicon oxide (SiO2). The formation process of the first power array 1041 includes but is not limited to CVD, PVD, ALD and ECD, and the material of the first power array 1041 may include one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn) or their alloys.

[0057] S220 : depositing an insulating layer 106 on the isolation layer 105 and the first power array 1041 , and patterning the insulating layer 106 . The patterned insulating layer 106 exposes a portion of the power line Vdd and the ground line Vss of the first power array 1041 .

[0058] S230 A capacitor structure 108, a contact plug CT and a second power array 1042 are sequentially formed in the patterned insulating layer 106. The second power array 1042 extends along a second direction X, and the second power array 1041 includes at least two power lines Vdd and at least two ground lines Vss. The first direction Y intersects with the second direction X in a direction parallel to the substrate 101. The first direction Y and the second direction X may intersect at a perpendicular angle in a direction parallel to the substrate 101 or may intersect at other angles as required, which is not limited herein. The projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 partially overlap, the contact plug CT and the capacitor structure 108 are connected between the first power array 1041 and the second power array 1042, the power network layer 104 can be composed of at least one first power array 1041 and at least one second power array 1042, the planes where the different power arrays are located are parallel to the substrate 101 and are located in different layers, the second power array 1042 can be arranged above the first power array 1041, and the projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 have an intersecting part.

[0059] In some embodiments, reference Figure 2-Figure 5 as well as Figure 8-Figure 13 The insulating layer 106 includes a first barrier layer 1061, a first insulating layer 1062, a second barrier layer 1063 and a second insulating layer 1064. A capacitor structure 108, a contact plug CT and a second power array 1042 are sequentially formed in the patterned insulating layer 106, including:

[0060] S2310 A first barrier layer 1061 and a first insulating layer 1062 are deposited and patterned to form a first trench 107 . The first trench 107 exposes a portion of the power line Vdd or the ground line Vss of the first power array 1041 .

[0061] S2320 A lower electrode 1081, a dielectric layer 1082, a blocking layer 1083 and an upper electrode 1084 are sequentially deposited in the first groove 107. The lower electrode 1081, the dielectric layer 1082, the blocking layer 1083 and the upper electrode 1084 constitute a capacitor structure 108. The lower electrode 1081 is connected to the power line Vdd or the ground line Vss of the first power array 1041.

[0062] S2330 deposits a second barrier layer 1063 and a second insulating layer 1064, and patterns the first barrier layer 1061, the first insulating layer 1062, the second barrier layer 1063 and the second insulating layer 1064 to form a second groove 109, wherein the second groove 109 exposes a portion of the power line Vdd or the ground line Vss of the first power array 1041 and the upper electrode 1084 of the capacitor structure 108.

[0063] S2340 deposits a conductive material layer in the second trench 109 to form a contact plug CT and a second power array 1042; illustratively, the process of depositing the first barrier layer 1061, the first insulating layer 1062, the second barrier layer 1063 and the second insulating layer 1064 includes but is not limited to CVD, PVD, and ALD, and the process of depositing the lower electrode 1081, the dielectric layer 1082, the barrier layer 1083 and the upper electrode 1084 includes but is not limited to CVD, PVD, ALD and ECD, and the patterning process can be dry etching or photomask etching, wherein the material of the first insulating layer 1062 and the second insulating layer 1063 can include silicon oxide (SiO2), and the material of the first barrier layer 1061 and the second barrier layer 1063 can include silicon nitride (SiN); the material of the lower electrode 1081 and the upper electrode 1084 of the capacitor structure 108 can include cobalt The material of the dielectric layer 1082 may include one or more metal oxides (for example, one or more of HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and TiO2, and may have a single-layer structure or a multi-layer structure, and the barrier layer 1083 may include metal nitrides, for example, one or more of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) and tungsten nitride (WN)).

[0064] In some embodiments, the lower electrode 1081 of the capacitor structure 108 is connected to the power line Vdd of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the ground line Vss of the second power array 1042; or, the lower electrode 1081 of the capacitor structure 108 is connected to the ground line Vss of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the power line Vdd of the second power array 1042.

[0065] In some embodiments, the contact plug CT is used to connect a power line Vdd of the first power array 1041 with a power line Vdd of the second power array 1042 , or to connect a ground line Vss of the first power array 1041 with a ground line Vss of the second power array 1042 .

[0066] In some embodiments, the semiconductor structure 10 may include a memory device, for example, the memory device may be a non-volatile memory device, such as at least one of a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), and a resistive random access memory (RRAM). For example, the flash memory includes a NAND flash memory or a V-NAND flash memory. In some embodiments, the memory device includes a volatile memory device, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Among them, the memory semiconductor chip includes a semiconductor device, and the semiconductor device includes a plurality of individual devices of various types. The plurality of individual devices include various microelectronic devices, such as a metal oxide semiconductor field effect transistor (MOSFET) including a CMOS transistor, a system large-scale integrated circuit (LSI), an active device, or a passive device.

[0067] In summary, the embodiment of the present disclosure improves the voltage stabilization effect by integrating the capacitor structure into the power supply network without adding an additional capacitor structure, thereby reducing the size of the chip; on the other hand, since the power network can be directly connected to the capacitor structure internally, the power supply path is shortened, thereby reducing the transmission resistance and further enhancing the stability and reliability of the power network.

[0068] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a device layer, an embedded power rail and a through silicon via, wherein the through silicon via is connected to the device layer through the embedded power rail; A power network layer, arranged on the substrate, the power network layer comprising at least one first power array and at least one second power array, the first power array being connected to the embedded power rail through the through silicon via; The capacitor structure is disposed between the first power array and the second power array, and is connected to the first power array and the second power array respectively through a lower electrode and an upper electrode of the capacitor structure.

2. The semiconductor structure according to claim 1, characterized in that: The first power array extends along a first direction, the second power array extends along a second direction, the first direction intersects with the second direction in a direction parallel to the substrate, and projections of the first power array and the second power array in a direction perpendicular to the substrate have overlapping portions.

3. The semiconductor structure according to claim 2, characterized in that: The first power array and the second power array each include at least two power lines and at least two ground lines. The at least two power lines and at least two ground lines of the first power array are parallel to each other and staggered along the second direction. The at least two power lines and at least two ground lines of the second power array are parallel to each other and staggered along the first direction.

4. The semiconductor structure according to claim 3, characterized in that: The overlapping portion of the projections of the first power array and the second power array in a direction perpendicular to the substrate includes at least one first area and at least one second area, wherein the first area is the overlapping portion of the projections of the power lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate and the overlapping portion of the projections of the ground lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate; The second area is the overlapping portion of the projections of the ground line of the first power array and the power line of the second power array in a direction perpendicular to the substrate and the overlapping portion of the projections of the power line of the first power array and the ground line of the second power array in a direction perpendicular to the substrate.

5. The semiconductor structure according to claim 4, characterized in that: A contact plug is also provided between the first power array and the second power array. The contact plug is provided in the first area and is used to connect the power line of the first power array with the power line of the second power array or to connect the ground line of the first power array with the ground line of the second power array.

6. The semiconductor structure according to claim 4, characterized in that: The capacitor structure is arranged in the second area, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

7. The semiconductor structure according to claim 3, characterized in that: The number of the power lines and the ground lines of the first power array is the same, and the number of the power lines and the ground lines of the second power array is the same.

8. The semiconductor structure according to claim 7, characterized in that: The distance between adjacent power lines and ground lines ranges from 0.1 to 1.5 μm.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a device layer, an embedded power rail and a through silicon via are formed in the substrate, wherein the through silicon via is connected to the device layer through the embedded power rail; The power network layer and the capacitor structure are formed on the substrate, the power network layer includes at least one first power array and at least one second power array, the first power array is connected to the buried power rail through the through silicon via, the capacitor structure is formed between the first power array and the second power array, and is connected to the first power array and the second power array through the lower electrode and the upper electrode of the capacitor structure respectively.

10. The preparation method according to claim 9, characterized in that: The step of forming the power network layer and the capacitor structure on the substrate comprises: The substrate has a first surface and a second surface, an isolation layer is formed on the first surface of the substrate, and the first power array is formed in the patterned isolation layer, the first power array extends along a first direction, and the first power array includes at least two power lines and at least two ground lines; Depositing an insulating layer on the isolation layer and the first power array, and patterning the insulating layer, wherein the patterned insulating layer exposes a portion of the power lines and the ground lines of the first power array; The capacitor structure, the contact plug and the second power array are sequentially formed in the patterned insulating layer, the second power array extends along the second direction, and the second power array includes at least two power lines and at least two ground lines, the first direction intersects with the second direction in a direction parallel to the substrate, the projections of the first power array and the second power array in a direction perpendicular to the substrate overlap, and the contact plug and the capacitor structure are connected between the first power array and the second power array.

11. The preparation method according to claim 10, characterized in that: The lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

12. The preparation method according to claim 10, characterized in that: The contact plug is used to connect the power line of the first power array with the power line of the second power array, or to connect the ground line of the first power array with the ground line of the second power array.

13. The preparation method according to claim 10, characterized in that: The insulating layer includes a first barrier layer, a first insulating layer, a second barrier layer and a second insulating layer, and the capacitor structure, the contact plug and the second power array are sequentially formed in the patterned insulating layer, including: Depositing the first barrier layer and the first insulating layer, patterning the first barrier layer and the first insulating layer to form a first groove, wherein the first groove exposes a portion of the power line or the ground line of the first power array; sequentially depositing the lower electrode, the dielectric layer, the barrier layer and the upper electrode in the first groove, wherein the lower electrode, the dielectric layer, the barrier layer and the upper electrode constitute the capacitor structure, and the lower electrode is connected to the power line or the ground line of the first power array; Depositing to form the second barrier layer and the second insulating layer, and patterning the first barrier layer, the first insulating layer, the second barrier layer and the second insulating layer to form a second groove, wherein the second groove exposes a portion of the power line or the ground line of the first power array and the upper electrode of the capacitor structure; A conductive material layer is deposited in the second trench to form the contact plug and the second power array.

14. The preparation method according to claim 10, characterized in that: The device layer, the buried power rail and the through silicon via are formed in the substrate, comprising: forming the through silicon via in the substrate, the through silicon via penetrating the first surface and the second surface of the substrate; The buried power rail and the device layer are sequentially formed on the second surface of the substrate.

15. The preparation method according to claim 14, characterized in that: After the device layer is formed in the substrate, the method further includes forming a signal interconnection layer on the device layer.

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