RISC-V instruction acceleration method, system and device and storage medium

Abstract

The invention relates to the technical field of computers, and particularly provides an RISC-V instruction acceleration method, system and device and a storage medium, and the method comprises the following steps: specifying an acceleration special register from general registers; configuring a parallel processing architecture, wherein the parallel processing architecture comprises a first instruction execution path and a second instruction execution path; and confirming that a source register of a target instruction comprises the special acceleration register, and concurrently executing the target instruction by utilizing the parallel processing architecture. According to the method, the execution efficiency of the RISC-V instruction is improved by specifying the special acceleration register and configuring the parallel architecture.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and specifically relates to a RISC-V instruction acceleration method, system, device and storage medium. Background Art

[0002] As the fifth generation of reduced instruction set architecture, RISC-V instruction set has become the best choice for many enterprises and research institutes to conduct in-depth research due to its open source, modular and highly scalable design. It can be fundamentally optimized in terms of low power consumption, high performance, high reliability and other aspects according to actual needs.

[0003] The existing methods for accelerating instructions usually include increasing the number of pipeline stages, increasing the issue width, improving the cache hit rate, improving the branch prediction accuracy, etc. These methods have high hardware complexity and are difficult to implement, which often leads to a longer R&D cycle and may also reduce energy efficiency. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a RISC-V instruction acceleration method, system, device and storage medium to solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a RISC-V instruction acceleration method, comprising: Specify acceleration special registers from general registers; configuring a parallel processing architecture, the parallel processing architecture comprising a first instruction execution path and a second instruction execution path; Confirm that the source register of the target instruction includes the acceleration dedicated register, and use the parallel processing architecture to concurrently execute the target instruction.

[0006] In an optional implementation, specifying an acceleration dedicated register from a general register includes: Set x31 of general-purpose registers x0 to x31 to an acceleration special register.

[0007] In an optional embodiment, a parallel processing architecture is configured, wherein the parallel processing architecture includes a first instruction execution path and a second instruction execution path, including: Configure a first logic operation unit, a second logic operation unit, a first decoding unit, and a second decoding unit; Dividing the general registers other than the acceleration special registers into a first general register group and a second general register group; The first decoding unit and the first logic operation unit are recorded as the first instruction execution path, and the first general register group is used by the first logic operation unit; the second decoding unit and the second logic operation unit are recorded as the second instruction execution path, and the second general register group is used by the second logic operation unit.

[0008] In an optional embodiment, the method further comprises: Setting addressing parameters in the state control register, the addressing parameters including the starting address, stride and addressing times of the addressing; The address of the data required to execute the target instruction is calculated according to the addressing parameter, so as to load the required data into the acceleration dedicated register based on the address.

[0009] In an optional implementation, confirming that the source register of the target instruction includes the acceleration dedicated register, and concurrently executing the target instruction using the parallel processing architecture includes: caching the target instruction into a pre-allocated instruction buffer; Close the instruction buffer, where the instruction buffer no longer caches new instructions; Enables dual-issue capability to execute instructions concurrently.

[0010] In an optional embodiment, enabling a dual-issue function to concurrently execute instructions includes: Read instructions from memory or the instruction buffer; Allocating registers to the first logic operation unit and the second logic operation unit for parallel processing instructions based on a preset register usage rule; The data required by the instruction is obtained from the memory and stored in the source register of the instruction.

[0011] In an optional implementation, the register usage rule includes: When the first logic operation unit and the second logic operation unit execute the same instruction, if the first logic operation unit uses any register in the first general register group as a source register when executing the instruction, the second logic operation unit uses a register in the second general register group as a source register when executing the instruction in parallel; If the source registers of two consecutive instructions are the same, the source register is set as a shared register, and the shared register allows the first logic operation unit and the second logic operation unit to access; When the first logic operation unit and the second logic operation unit execute different instructions, the first logic operation unit executes instructions that require access to memory, and selects the source register and target register of the instruction from the first general register group; the second logic operation unit executes instructions in the instruction buffer, and selects the target register of the instruction from the second general register group, and the source register of the instruction is the acceleration-specific register.

[0012] In a second aspect, the present invention provides a RISC-V instruction acceleration system, comprising: An acceleration configuration module, used to specify acceleration-specific registers from general registers; A parallel configuration module, configured to configure a parallel processing architecture, wherein the parallel processing architecture includes a first instruction execution path and a second instruction execution path; The execution control module is used to confirm that the source register of the target instruction includes the acceleration dedicated register, and to concurrently execute the target instruction using the parallel processing architecture.

[0013] In a third aspect, a device is provided, including: A memory, used for storing a RISC-V instruction acceleration program; A processor is used to implement the steps of the RISC-V instruction acceleration method provided in the first aspect when executing the RISC-V instruction acceleration program.

[0014] In a fourth aspect, a computer-readable storage medium is provided, on which a RISC-V instruction acceleration program is stored. When the RISC-V instruction acceleration program is executed by a processor, the steps of the RISC-V instruction acceleration method provided in the first aspect are implemented.

[0015] The beneficial effect of the present invention is that the RISC-V instruction acceleration method, system, device and storage medium provided by the present invention improve the execution efficiency of RISC-V instructions by specifying acceleration-specific registers and configuring a parallel architecture.

[0016] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

[0019] Figure 2 is another schematic flow chart of a method according to an embodiment of the present invention.

[0020] Figure 3 It is a schematic architecture diagram of a system according to an embodiment of the present invention.

[0021] Figure 4 A schematic diagram of the structure of a device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0024] The RISC-V instruction acceleration method provided in the embodiment of the present invention is executed by a computer device, and accordingly, the RISC-V instruction acceleration system runs in the computer device.

[0025] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention. Figure 1 The execution subject can be a RISC-V instruction acceleration system. According to different requirements, the order of the steps in the flowchart can be changed, and some can be omitted.

[0026] like Figure 1 As shown, the method includes: S1. Specify an acceleration-specific register from the general registers.

[0027] S2. Configure a parallel processing architecture, wherein the parallel processing architecture includes a first instruction execution path and a second instruction execution path.

[0028] S3. Confirm that the source register of the target instruction includes the acceleration dedicated register, and use the parallel processing architecture to concurrently execute the target instruction.

[0029] In an embodiment of the present invention, based on step S1, a possible embodiment is given below to illustrate its specific implementation scheme in a non-limiting manner.

[0030] Specifically, x31 among the general registers x0 to x31 is set as an acceleration dedicated register (ADR for short).

[0031] In an embodiment of the present invention, based on step S2, a possible embodiment is given below to illustrate its specific implementation scheme in a non-limiting manner.

[0032] Configure the first logic operation unit (ALU1 for short), the second logic operation unit (ALU2 for short), the first decoding unit (DU1 for short), and the second decoding unit (DU2 for short); divide the general registers other than ADR into the first general register group (RF1 for short) and the second general register group (RF2 for short); record DU1 and ALU1 as the first instruction execution path, and RF1 is used for ALU1; record DU2 and ALU2 as the second instruction execution path, and RF2 is used for ALU2.

[0033] In one embodiment of the present invention, based on step S3, a possible embodiment is given below to illustrate its specific implementation scheme in a non-limiting manner. Please refer to Figure 2 .

[0034] S301. Cache the target instruction into a pre-allocated instruction buffer.

[0035] Confirm that the target instruction is an instruction that needs to be accelerated, that is, the source register of the target instruction contains a dedicated acceleration register, and cache the target instruction into an instruction buffer (IB for short). The target instruction can be a single instruction or a series of related instructions.

[0036] The main function of IB is to prefetch and cache instructions to be executed. In scenarios such as loop calculations, instructions are often executed repeatedly. By storing instructions in IB, it is possible to avoid re-fetching instructions from memory each time they are executed, thereby reducing the number of memory accesses, reducing memory bandwidth pressure, and improving the efficiency of instruction execution.

[0037] S302. Close the instruction buffer, where the instruction buffer no longer caches new instructions.

[0038] Storing instructions in IB and closing IB before dual issuance can also ensure the continuity and consistency of instruction execution. No new instructions will be inserted into the execution stream until the instructions in IB are fully executed. This helps maintain the sequential nature of instruction execution and avoids errors or performance degradation that may result from out-of-order execution of instructions.

[0039] In addition, by storing instructions in the IB and turning off the IB, processor resources can be saved to a certain extent. During the period when the IB is turned off, the processor does not need to continuously read instructions from the memory, but can focus on executing the instructions that have been cached in the IB. This helps to reduce the processor's idle time and improve overall performance.

[0040] S303. Enable the dual-issue function to execute instructions concurrently.

[0041] Read instructions from memory or the instruction buffer; Allocating registers to the first logic operation unit and the second logic operation unit for parallel processing instructions based on a preset register usage rule; The data required by the instruction is obtained from the memory and stored in the source register of the instruction.

[0042] The register usage rules include: When the first logic operation unit and the second logic operation unit execute the same instruction, if the first logic operation unit uses any register in the first general register group as a source register when executing the instruction, the second logic operation unit uses a register in the second general register group as a source register when executing the instruction in parallel; If the source registers of two consecutive instructions are the same, the source register is set as a shared register, and the shared register allows the first logic operation unit and the second logic operation unit to access; When the first logic operation unit and the second logic operation unit execute different instructions, the first logic operation unit executes instructions that require access to memory, and selects the source register and target register of the instruction from the first general register group; the second logic operation unit executes instructions in the instruction buffer, and selects the target register of the instruction from the second general register group, and the source register of the instruction is the acceleration-specific register.

[0043] The following is an exemplary instruction execution scenario: (1) Dual-issue means that ALU1 and ALU2 execute the same instruction but with different operands. This means that although the two instructions have the same function, they process different data sets.

[0044] Using dual-issue to execute the same instruction in IB, the specific execution process is as follows: Both DU1 and DU2 decode instruction 1 in IB. The information obtained after DU1 is decoded is source register 1, source register ADR, and target register 2. The information obtained after DU2 is decoded is source register 3, source register ADR, and target register 4, where source register 1 and target register 2 belong to the first general register group RF1, and source register 3 and target register 4 belong to the second general register group RF2.

[0045] ALU1 and ALU2 respectively execute the calculation task of instruction 1 based on the decoded information.

[0046] In order to further improve the efficiency of instruction execution, The addressing parameters are set in the status control register (detection CSR), wherein the addressing parameters include the starting address, stride and addressing times of the addressing; the address of the data required to execute the target instruction is calculated according to the addressing parameters, so as to load the required data into the acceleration dedicated register based on the address.

[0047] ALU1 reads data from ADR and source register 1, performs operations on the read data, and stores the operation results in target register 2; ALU2 reads data from ADR and source register 3, performs operations on the read data, and stores the operation results in target register 4.

[0048] (2) Shared register scenario.

[0049] Step 1: Instruction reading and decoding Instruction fetch: The processor fetches the next instruction from IB, which is decoded by the decoding unit DU1.

[0050] Instruction decoding: The instruction decoded by DU1 is an instruction that needs to use a source register in RF2 (for example, a load instruction to load data from memory into the register).

[0051] Step 2: Register allocation and sharing preparation Register allocation: The processor determines which source register in RF2 (assumed to be RF2[R1]) the instruction will use.

[0052] Shared preparation: Since the following instructions will continue to use this source register, the processor will prepare to allow ALU1 and ALU2 to share this register. A status flag is generated to indicate that the register is currently shared.

[0053] Step 3: The first instruction is executed Execute the load instruction: ALU1 executes the load instruction and loads data from memory into RF2[R1].

[0054] Update State: The processor updates its internal state, marking that RF2[R1] now contains valid data and that the register is shared.

[0055] Step 4: Read and decode the second instruction Instruction fetch: The processor fetches the next instruction from IB, which is decoded by the decode unit DU2.

[0056] Instruction decoding: The instruction decoded by DU2 is an instruction that requires the use of data previously loaded into RF2[R1] (for example, an arithmetic instruction).

[0057] Step 5: Second instruction execution and register sharing Performing arithmetic operations: ALU2 executes arithmetic instructions using the data in RF2[R1] as one of the operands.

[0058] Shared access: Since RF2[R1] is shared, ALU2 can directly access the data in this register without any additional data movement or copying operations.

[0059] Step 6: Instruction completion and result processing Instruction Completion: When both instructions have completed execution, the processor updates its internal state to mark these instructions as completed.

[0060] Result processing: The processor may store the result of the operation in another register, write it back to memory, or perform other subsequent operations, depending on the instruction flow and data flow of the program.

[0061] Through this process example, we can see that in the RISC-V instruction accelerator, when an instruction fetches from memory and uses a source register in RF2, and the next instruction will continue to use the source register, the processor can use internal control signals or status tags to achieve shared use of the source register. This method of sharing registers can improve the flexibility of data processing because it allows two instructions to access the same data set without the need for additional data movement, thereby reducing the overhead of data movement and improving processor performance.

[0062] (3) Handle different types of instruction scenarios.

[0063] Step 1: Instruction reading and decoding Read instruction: The processor reads the next instruction from memory and places it in the instruction queue to be decoded.

[0064] Decoding instructions: DU1 and DU2 simultaneously take instructions from the instruction queue for decoding. Suppose DU1 decodes a load instruction (Load) that requires accessing memory, while DU2 decodes an arithmetic operation instruction (such as addition).

[0065] Step 2: Prepare operands and register allocation ALU1 preparation: Since the Load instruction requires access to memory, ALU1 will wait for the memory access to complete. During this time, it will not perform any operations. However, it has already started preparing the operands, that is, determining which source register (one of the registers in RF1) and destination register to use.

[0066] ALU2 prepares: Meanwhile, ALU2 does not need to wait for memory access. It has read the pre-stored addition instruction from instruction buffer IB and has determined to use two registers in RF2 as source registers. Since ALU2's instruction comes from IB, it can start preparing to execute while ALU1 is still waiting for memory access.

[0067] Step 3: Execute the command ALU1 Execution: Once the memory access is complete, ALU1 will load the data from memory into the specified source register and execute the load instruction. After the load is complete, ALU1 may store the result in the destination register or pass the result to the next instruction as an operand.

[0068] ALU2 Execution: While ALU1 is waiting for memory access, ALU2 has already started executing the addition instruction. It reads the values ​​of the two source registers from RF2, performs the addition operation, and stores the result in the specified destination register.

[0069] Step 4: Instruction completion and result processing ALU1 completes: When the ALU1 load instruction is executed, it updates the processor status (such as register values, memory addresses, etc.) and marks the instruction as completed.

[0070] ALU2 Completed: Similarly, when the ALU2 addition instruction is completed, it also updates the processor status and marks the instruction as completed.

[0071] Through this process example, we can see that when ALU2 executes instructions of a different operation type from ALU1, the processor can use the instruction buffer IB to prepare and execute ALU2's instructions in advance. In this way, even if ALU1 needs to wait for memory access, the processor can still maintain efficient parallel processing capabilities. This design can significantly improve the overall performance of the processor, especially when executing complex programs containing multiple types of instructions.

[0072] When all the currently cached instructions have been executed and new instructions need to be executed, the IB unit will be reopened to prefetch and cache new instructions, and dual issuance will be closed. The timing of reopening the IB unit usually depends on the progress of instruction execution and the cache status of instructions in the IB unit. When the instructions in the IB unit are cleared or are about to be cleared, the processor will send a signal to reopen the IB unit. In addition, in some cases, such as when encountering branch instructions or interrupts, it may also be necessary to reopen the IB unit to obtain a new instruction stream.

[0073] In some embodiments, the RISC-V instruction acceleration system may include multiple functional modules composed of computer program segments. The computer programs of each program segment in the RISC-V instruction acceleration system may be stored in a memory of a computer device and executed by at least one processor to perform (see Figure 1 Description) Function of RISC-V instruction acceleration.

[0074] In this embodiment, the RISC-V instruction acceleration system can be divided into multiple functional modules according to the functions it performs, such as Figure 3 As shown, it mainly includes: Acceleration Dedicated Register (ADR): Set x31 in the general register group to the acceleration dedicated register ADR. When an instruction uses ADR as the source register, the instruction and its subsequent two operations will be executed in parallel, which improves the execution efficiency of the instruction.

[0075] Address Generation Unit (AGU): A new AGU is added to calculate the address of the data that should be loaded into the ADR register based on the starting address and stride. This enables the processor to efficiently process instructions that require continuous access to memory addresses, such as array operations.

[0076] Control Status Register (CSR): A new CSR is added to control the working status of the AGU, including setting the starting address, stride, and addressing count of the addressing. By assigning values ​​to the CSR, the parameters of the AGU can be initialized to control how data is loaded.

[0077] Instruction Buffer (IB): A new IB is added to store instructions. When an instruction uses the ADR register, the instruction is written to the IB.

[0078] Expansion of the decoding unit (DU) and the arithmetic logic unit (ALU): The number of existing DUs and ALUs is increased to 2 (DU1, DU2, ALU1 and ALU2), forming two complete instruction execution paths. This enables the processor to process two instructions at the same time, further improving parallel processing capabilities.

[0079] Division of general registers: The general registers except ADR register are divided into two parts, RF1 and RF2, which are used by ALU1 and ALU2 respectively. This helps to avoid register conflicts and improve the parallelism of instruction execution.

[0080] The shared instruction fetch unit IFU and load storage unit LSU, the IFU is used to read instructions from the memory, and the LSU is used to load data from the memory.

[0081] By assigning values ​​to the CSR register, set the initialization parameters of the AGU and enable the IB.

[0082] When an instruction uses the ADR register, the instruction is written to IB.

[0083] Disable IB and enable dual launch.

[0084] Dual issue can mean that ALU1 and ALU2 execute the same instruction but with different operands, or they can execute instructions of different types (where ALU2's instructions come from IB).

[0085] It is also possible to execute all instructions in IB sequentially and in parallel with instructions fetched from memory.

[0086] In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0087] An acceleration configuration module, used to specify acceleration-specific registers from general registers; A parallel configuration module, configured to configure a parallel processing architecture, wherein the parallel processing architecture includes a first instruction execution path and a second instruction execution path; The execution control module is used to confirm that the source register of the target instruction includes the acceleration dedicated register, and to concurrently execute the target instruction using the parallel processing architecture.

[0088] Optionally, as an embodiment of the present invention, x31 among general registers x0 to x31 is set to ADR.

[0089] Optionally, as an embodiment of the present invention, the parallel configuration module includes: Configure the first logic operation unit (ALU1 for short), the second logic operation unit (ALU2 for short), the first decoding unit (DU1 for short), and the second decoding unit (DU2 for short); divide the general registers other than ADR into the first general register group (RF1 for short) and the second general register group (RF2 for short); record DU1 and ALU1 as the first instruction execution path, and RF1 is used for ALU1; record DU2 and ALU2 as the second instruction execution path, and RF2 is used for ALU2.

[0090] Optionally, as an embodiment of the present invention, the system further includes: Setting addressing parameters in the state control register, the addressing parameters including the starting address, stride and addressing times of the addressing; The addressing unit calculates the address of the data required to execute the target instruction according to the addressing parameter, so as to load the required data into the acceleration dedicated register based on the address.

[0091] Optionally, as an embodiment of the present invention, the execution control module includes: caching the target instruction into a pre-allocated instruction buffer; Close the instruction buffer, where the instruction buffer no longer caches new instructions; Enables dual-issue capability to execute instructions concurrently.

[0092] Optionally, as an embodiment of the present invention, enabling a dual-issue function to concurrently execute instructions includes: Read instructions from memory or the instruction buffer; Allocating registers to the first logic operation unit and the second logic operation unit for parallel processing instructions based on a preset register usage rule; The data required by the instruction is obtained from the memory and stored in the source register of the instruction.

[0093] Optionally, as an embodiment of the present invention, the register usage rule includes: When the first logic operation unit and the second logic operation unit execute the same instruction, if the first logic operation unit uses any register in the first general register group as a source register when executing the instruction, the second logic operation unit uses a register in the second general register group as a source register when executing the instruction in parallel; If the source registers of two consecutive instructions are the same, the source register is set as a shared register, and the shared register allows the first logic operation unit and the second logic operation unit to access; When the first logic operation unit and the second logic operation unit execute different instructions, the first logic operation unit executes instructions that require access to memory, and selects the source register and target register of the instruction from the first general register group; the second logic operation unit executes instructions in the instruction buffer, and selects the target register of the instruction from the second general register group, and the source register of the instruction is the acceleration-specific register.

[0094] Figure 4The RISC-V instruction acceleration method provided for the embodiment of the present application can be applied to the device. It will be appreciated by those skilled in the art that the device structure involved in the embodiment of the present invention does not constitute a limitation on the device, and the device may include more or less components than shown, or combine certain components, or arrange different components. In an embodiment of the present invention, the device includes but is not limited to a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the embodiments of the present application described and / or required herein.

[0095] The device 400 may include: a processor 410, a memory 420 and a communication unit 430. These components communicate via one or more buses. Those skilled in the art will appreciate that the server structure shown in the figure does not limit the present invention, and it may be a bus structure or a star structure, and may include more or fewer components than shown in the figure, or combine certain components, or arrange components differently.

[0096] The memory 420 may be used to store the execution instructions of the processor 410, and the memory 420 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. When the execution instructions in the memory 420 are executed by the processor 410, the device 400 is enabled to perform some or all of the steps in the following method embodiments.

[0097] The processor 410 is the control center of the storage device, and uses various interfaces and lines to connect various parts of the entire electronic device. It runs or executes software programs and / or modules stored in the memory 420, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of a plurality of packaged ICs with the same or different functions. For example, the processor 410 can include only a central processing unit (CPU). In an embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0098] The communication unit 430 is used to establish a communication channel so that the storage device can communicate with other devices, receive user data sent by other devices or send user data to other devices.

[0099] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program may include some or all of the steps in each embodiment provided by the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0100] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes, including several instructions for enabling a computer device (which can be a personal computer, a server, or a second device, a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention.

[0101] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

[0102] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or modules, which can be electrical, mechanical or other forms.

[0103] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0104] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0105] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A RISC-V instruction acceleration method, characterized in that: include: Specify acceleration special registers from general registers; configuring a parallel processing architecture, the parallel processing architecture comprising a first instruction execution path and a second instruction execution path; Confirm that the source register of the target instruction includes the acceleration dedicated register, and use the parallel processing architecture to concurrently execute the target instruction.

2. The method according to claim 1, characterized in that: Specify acceleration-specific registers from general-purpose registers, including: Set x31 of general-purpose registers x0 to x31 to an acceleration special register.

3. The method according to claim 1, characterized in that Configuring a parallel processing architecture, the parallel processing architecture comprising a first instruction execution path and a second instruction execution path, comprising: Configure a first logic operation unit, a second logic operation unit, a first decoding unit, and a second decoding unit; Dividing the general registers other than the acceleration special registers into a first general register group and a second general register group; The first decoding unit and the first logic operation unit are recorded as the first instruction execution path, and the first general register group is used by the first logic operation unit; the second decoding unit and the second logic operation unit are recorded as the second instruction execution path, and the second general register group is used by the second logic operation unit.

4. The method according to claim 1, characterized in that: The method further comprises: Setting addressing parameters in the state control register, the addressing parameters including the starting address, stride and addressing times of the addressing; The address of the data required to execute the target instruction is calculated according to the addressing parameter, so as to load the required data into the acceleration dedicated register based on the address.

5. The method according to claim 2, characterized in that: Confirming that the source register of the target instruction includes the acceleration dedicated register, and concurrently executing the target instruction using the parallel processing architecture, comprises: caching the target instruction into a pre-allocated instruction buffer; Close the instruction buffer, where the instruction buffer no longer caches new instructions; Enables dual-issue capability to execute instructions concurrently.

6. The method according to claim 5, characterized in that Enables dual-issue functionality to execute instructions concurrently, including: Read instructions from memory or the instruction buffer; Allocating registers to the first logic operation unit and the second logic operation unit for parallel processing instructions based on a preset register usage rule; The data required by the instruction is obtained from the memory and stored in the source register of the instruction.

7. The method according to claim 6, characterized in that The register usage rules include: When the first logic operation unit and the second logic operation unit execute the same instruction, if the first logic operation unit uses any register in the first general register group as a source register when executing the instruction, the second logic operation unit uses a register in the second general register group as a source register when executing the instruction in parallel; If the source registers of two consecutive instructions are the same, the source register is set as a shared register, and the shared register allows the first logic operation unit and the second logic operation unit to access; When the first logic operation unit and the second logic operation unit execute different instructions, the first logic operation unit executes instructions that require access to memory, and selects the source register and target register of the instruction from the first general register group; the second logic operation unit executes instructions in the instruction buffer, and selects the target register of the instruction from the second general register group, and the source register of the instruction is the acceleration-specific register.

8. A RISC-V instruction acceleration system, characterized in that: include: An acceleration configuration module, used to specify acceleration-specific registers from general registers; A parallel configuration module, configured to configure a parallel processing architecture, wherein the parallel processing architecture includes a first instruction execution path and a second instruction execution path; The execution control module is used to confirm that the source register of the target instruction includes the acceleration dedicated register, and to concurrently execute the target instruction using the parallel processing architecture.

9. A device, characterized in that: include: A memory, used for storing a RISC-V instruction acceleration program; A processor, used to implement the steps of the RISC-V instruction acceleration method as described in any one of claims 1 to 7 when executing the RISC-V instruction acceleration program.

10. A computer-readable storage medium storing a computer program, characterized in that: The readable storage medium stores a RISC-V instruction acceleration program, which, when executed by a processor, implements the steps of the RISC-V instruction acceleration method according to any one of claims 1 to 7.

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