1553B bus circuit automatic initialization module based on SPI interface

Abstract

The invention discloses an automatic initialization module of a 1553B bus circuit based on an SPI (Serial Peripheral Interface), which belongs to the field of communication circuits and comprises an SPI control logic, a serial-parallel conversion unit, a cache unit, an address data separation unit, a register / memory instruction analysis module, a 1553B circuit initialization logic and a register and memory interface, so that the circuit has an automatic initialization function. After the circuit is powered on or an automatic initialization function is enabled through an external pin, an internal register and a memory automatically finish initialization configuration, and manual operation is not needed. According to the invention, the basic structure of the original 1553B circuit is not changed, and only a part of logic is needed to be added for automatic initialization control and interfaces, so that the correctness and comprehensiveness of the initialization time sequence are ensured, the difficulty of using the 1553B bus circuit by a user is greatly reduced, and the development efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of communication circuits, and in particular to a 1553B bus circuit automatic initialization module based on an SPI interface. Background Art

[0002] MIL-STD-1553B is the abbreviation of "Aircraft Internal Time Division Command / Response Multiplexed Data Bus". As a US military standard, it is widely used in many fields such as ships, aviation, and aerospace due to its many advantages such as high reliability.

[0003] MIL-STD-1553 realizes the information sharing and transmission of various electronic equipment such as sensors, which fundamentally changes the way the United States and its allies fight. Manufacturers represented by the American DDC company have developed a variety of 1553B bus circuits, which are widely used in modern weapons and equipment. However, this type of circuit has a complex structure, requires a large number of registers and memories to be configured when used, and the configuration timing is complicated. When users use it for the first time, they often encounter improper register or memory configuration or configuration timing that does not meet the requirements, resulting in the circuit not working properly or working unstably, which seriously affects the stability of the 1553 system and the progress of product development. Summary of the invention

[0004] The object of the present invention is to provide a 1553B bus circuit automatic initialization module based on SPI interface to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a 1553B bus circuit automatic initialization module based on SPI interface, comprising: SPI control logic, serial-to-parallel conversion unit, cache unit, address data separation unit, register / memory instruction parsing module, 1553B circuit initialization logic and register and memory interface;

[0006] The SPI control logic is connected to an external EEPROM, and the external EEPROM stores preset initialization data;

[0007] The external EEPROM adopts a universal SPI interface, and each configuration data occupies 5 bytes, wherein the first byte is an instruction definition, which is used to distinguish between registers and memories; the second and third bytes are the register or memory address to be initialized, and the fourth and fifth bytes are the register or memory data to be initialized;

[0008] The SPI control logic automatically accesses the external EEPROM through the SPI interface and transmits the data in the EEPROM to the serial-to-parallel conversion unit; after receiving each byte of data, the serial-to-parallel conversion unit stores it in the cache unit until 5 bytes are full;

[0009] The address data separation unit combines the second and third bytes into a 16-bit address value, and combines the fourth and fifth bytes into a 16-bit data value, and transmits them to the 1553B bus initialization logic;

[0010] The register / memory instruction parsing module parses the configuration data to obtain a register or memory corresponding to the configuration data according to the instruction definition;

[0011] The 1553B circuit initialization logic sends 16-bit initialization data and 16-bit initialization address to the register and memory interface according to the set register and memory write timing, writes them into the corresponding register and memory, and completes the initialization configuration;

[0012] After the circuit is initialized, a high-level signal is output through the "initialization completed" external pin. When the high-level signal is detected, 1553B communication is started.

[0013] In one implementation, the length of the instruction is 8 bits, corresponding to the first byte of every 5 bytes of the EEPROM; "11110001" corresponds to register configuration, and "11110011" corresponds to memory configuration.

[0014] In one implementation, the storage capacity of the external EEPROM is 8k×8 bits or more.

[0015] The present invention provides a 1553B bus circuit automatic initialization module based on SPI interface, which has the following beneficial effects:

[0016] (1) The original 1553B bus circuit structure is not changed, thus ensuring the logic compatibility with the previous circuit and saving the cost of logic design and development;

[0017] (2) The universal SPI interface is used as the communication interface with the external EEPROM, which simplifies the development cost and reduces the difficulty of use;

[0018] (3) Since the 1553B bus protocol is a standard bus protocol and is widely used in many fields such as ships, aviation, and aerospace, this invention is also applicable to other types of 1553 circuits and has good reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a functional block diagram of the automatic initialization module of the present invention;

[0020] Figure 2 This is a flowchart of the automatic initialization in the present invention. DETAILED DESCRIPTION

[0021] The following is a further detailed description of a 1553B bus circuit automatic initialization module based on an SPI interface proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] The present invention, based on the original 1553B bus circuit, adopts the method of adding SPI control logic 1, serial-to-parallel conversion unit 2, cache unit 3, address data separation unit 4, register / memory instruction parsing unit 5, 1553B circuit initialization logic 6, register and memory interface 7 to enable the circuit to have automatic initialization function. Figure 1 As shown, Figure 1 The SPI EEPROM (Electrically Erasable Programmable read only memory) is a peripheral circuit, and the register and memory are part of the original 1553B bus circuit structure.

[0023] The SPI interface-based 1553B bus circuit automatic initialization module of the present invention can automatically initialize after the circuit is powered on or initialize through the circuit external pin AUTOEN.

[0024] The circuit for register and memory initialization data uses a general SPI interface EEPROM, whose storage capacity is not limited, but it is recommended to be 8k×8 bits or more to ensure sufficient storage space for initialization data. The register and memory initialization data must be pre-written into the EEPROM according to the specified data format. The detailed data format definition is shown in Table 1.

[0025]

[0026]

[0027] Table 1 Definition of external EEPROM data format in the present invention

[0028] In Table 1, each complete configuration data occupies 5 bytes, of which the first byte is the instruction definition, used to distinguish registers and memories. The second and third bytes are the register or memory address to be initialized, and the fourth and fifth bytes are the register or memory data to be initialized.

[0029] When the circuit completes the power-on process, the SPI control logic will automatically access the external EEPROM through the SPI interface. At this time, regardless of the state of the AUTOEN pin, the data in the EEPROM will be transmitted to the serial-to-parallel conversion unit 2. After receiving each byte of data, the serial-to-parallel conversion unit 2 stores it in the cache unit 3 until 5 bytes are full.

[0030] Then the address data separation unit 4 combines the 2nd and 3rd bytes into a 16-bit address value, and combines the 4th and 5th bytes into a 16-bit data value, and transmits them to the 1553B bus initialization logic 6.

[0031] The register / memory instruction parsing unit 5 parses the configuration data corresponding to the register or memory according to the instruction definition. The instruction length is 8 bits, corresponding to the first byte of every 5 bytes of EEPROM. The instruction definition is shown in Table 2.

[0032] Data bits Bit 7 Position 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 register 1 1 1 1 0 0 0 1 Memory 1 1 1 1 0 0 1 1

[0033] Table 2 Register / memory instruction definitions in the present invention

[0034] "11110001" corresponds to register configuration, and "11110011" corresponds to memory configuration. After parsing, the register / memory control signal will be transmitted to the 1553B bus initialization logic 6.

[0035] The 1553B circuit initialization logic 6 sends the 16-bit initialization address and 16-bit initialization data to the register and memory interface 7 according to the set register and memory write timing. The initialization data is written into the corresponding register and memory address unit under the control signal to complete the initialization configuration.

[0036] After the circuit is initialized, a high-level signal will be output through the "initialization completed" external pin. When the high-level signal is detected, the 1553B communication can be started to realize the 1553B circuit function.

[0037] During the operation of the circuit, the circuit can be initialized at any time through the AUTOEN pin. When a rising edge signal from low to high is detected on the AUTOEN pin, the SPI control logic 1 will automatically start to complete the initialization of the registers and memory inside the circuit.

[0038] The complete workflow of the 1553B bus circuit automatic initialization module is as follows Figure 2 shown.

[0039] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 1553B bus circuit automatic initialization module based on SPI interface, characterized in that: include: SPI control logic, serial-to-parallel conversion unit, cache unit, address-data separation unit, register / memory instruction parsing module, 1553B circuit initialization logic, and register and memory interface; The SPI control logic is connected to an external EEPROM, and the external EEPROM stores preset initialization data; The external EEPROM adopts a universal SPI interface, and each configuration data occupies 5 bytes, wherein the first byte is an instruction definition, which is used to distinguish between registers and memories; the second and third bytes are the register or memory address to be initialized, and the fourth and fifth bytes are the register or memory data to be initialized; The SPI control logic automatically accesses the external EEPROM through the SPI interface and transmits the data in the EEPROM to the serial-to-parallel conversion unit; after receiving each byte of data, the serial-to-parallel conversion unit stores it in the cache unit until 5 bytes are full; The address data separation unit combines the second and third bytes into a 16-bit address value, and combines the fourth and fifth bytes into a 16-bit data value, and transmits them to the 1553B bus initialization logic; The register / memory instruction parsing module parses the configuration data to obtain a register or memory corresponding to the configuration data according to the instruction definition; The 1553B circuit initialization logic sends 16-bit initialization data and 16-bit initialization address to the register and memory interface according to the set register and memory write timing, writes them into the corresponding register and memory, and completes the initialization configuration; After the circuit is initialized, a high-level signal is output through the "initialization completed" external pin. When the high-level signal is detected, 1553B communication is started.

2. The 1553B bus circuit automatic initialization module based on the SPI interface as claimed in claim 1, characterized in that: The length of the instruction is 8 bits, corresponding to the first byte of every 5 bytes of EEPROM; "11110001" corresponds to register configuration, and "11110011" corresponds to memory configuration.

3. The 1553B bus circuit automatic initialization module based on the SPI interface as claimed in claim 2, characterized in that: The storage capacity of the external EEPROM is 8k×8 bits or more.

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