Semiconductor structure and forming method thereof

Abstract

The invention relates to the technical field of semiconductors, and relates to a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate which comprises a substrate and an insulating layer, the substrate comprises an array region and a mark region, the array region is internally provided with a shallow trench isolation structure and an active region, and the insulating layer covers the substrate; forming a bit line contact hole; sequentially forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating covering layer on one side, far away from the substrate, of the insulating layer, wherein the bit line contact hole is filled with the first conductive layer; etching the insulating covering layer to respectively form insulating parts in the array region and the mark region; and etching the etching stop layer, the second conductive layer and the first conductive layer by taking the insulating part as a mask so as to form a bit line structure in the array region and form a mark pattern in the mark region. According to the forming method, the structure defects can be reduced, and the product yield can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration and fast transmission speed. As the core component of DRAM, the bit line structure plays a vital role in the electrical performance of the device. However, during the process of bit line structure manufacturing, structural defects are prone to occur due to the influence of process technology, and the product yield is low.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce structural defects and improve product yield.

[0005] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a base and an insulating layer, the base comprising an array area and a marking area, the array area being provided with a shallow trench isolation structure and a plurality of active areas separated by the shallow trench isolation structure, the insulating layer covering the shallow trench isolation structure, the active area and the marking area;

[0007] Etching the active area and the insulating layer located on the top of the active area to form a bit line contact hole;

[0008] forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole;

[0009] The insulating cover layer is etched to form insulating portions in the array region and the mark region respectively, wherein the orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; the etching rate of the etching stop layer is lower than the etching rate of the insulating cover layer;

[0010] The etching stop layer, the second conductive layer and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

[0011] In an exemplary embodiment of the present disclosure, an etching selectivity ratio between the insulating cap layer and the etching stop layer is greater than 10:1.

[0012] In an exemplary embodiment of the present disclosure, the material of the etching stop layer is undoped silicon, and the material of the insulating cap layer is silicon nitride.

[0013] In an exemplary embodiment of the present disclosure, etching the insulating cover layer to form insulating portions in the array region and the mark region respectively includes:

[0014] forming a mask layer on a surface of the insulating cover layer;

[0015] Etching the mask layer to form mask structures in the array region and the mark region respectively, wherein an orthographic projection of the mask structure in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole;

[0016] The insulating cover layer is etched using the mask layer having the mask structure as a mask to form the insulating portion in the array region and the mark region respectively.

[0017] In an exemplary embodiment of the present disclosure, the etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and to form a mark pattern in the mark area, including:

[0018] Using the insulating portion as a mask, etching the etching stop layer until the second conductive layer is exposed;

[0019] The second conductive layer and the first conductive layer are etched using the structure formed by the insulating portion and the remaining etching stop layer as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

[0020] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0021] The width of the insulating portion in a direction parallel to the substrate is detected, and when the width is within a first preset deviation range, the etching stop layer, the second conductive layer and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a marking pattern in the marking area.

[0022] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0023] The widths of different film layers in the bit line structure in a direction parallel to the substrate are detected, and when the width difference of different film layers in the bit line structure in a direction parallel to the substrate exceeds a second preset deviation range, the detection result is fed back to an etching machine used to etch the etching stop layer, the second conductive layer, and the first conductive layer.

[0024] In an exemplary embodiment of the present disclosure, the substrate further includes a peripheral area, the peripheral area is arranged side by side with the array area and the marking area, and the orthographic projection of the etching stop layer on the substrate covers the array area, the peripheral area and the marking area;

[0025] Before forming the insulating cover layer, the forming method further comprises:

[0026] removing the etching stop layer located in the peripheral area;

[0027] After forming the insulating cover layer, the forming method further comprises:

[0028] The insulating cover layer, the second conductive layer, the first conductive layer and the insulating layer in the peripheral region are etched to form a gate structure.

[0029] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0030] forming an isolation layer covering the sidewalls and top of the gate structure;

[0031] An insulating material layer is formed in the peripheral region outside the gate structure and the isolation layer, and a surface of the insulating material layer is flush with a surface of the isolation layer located on the top of the gate structure.

[0032] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is formed by any of the above-mentioned methods for forming a semiconductor structure.

[0033] The semiconductor structure and the formation method thereof disclosed in the present invention, by setting an etching stop layer below the insulating cover layer, when etching the insulating cover layer to form the insulating portion, the etching end point can be stopped on the etching stop layer, and in this process, the structure of the second conductive layer below will not be damaged, thereby avoiding the problem of uneven etching loss in different regions of the second conductive layer, which helps to improve the uniformity of the key dimensions of the finally formed bit line structure. When the second conductive layer is subsequently etched, the second conductive layer can be etched through by the same etching process, avoiding the load effect and necking phenomenon caused by different etching times, which helps to improve the profile of the bit line structure and further improve the uniformity of the bit line structure. In addition, since the etching rate of the etching stop layer is relatively small, the surface of the etching stop layer will not be greatly damaged in the process of forming the insulating portion, and different regions of the etching stop layer are still in a relatively flat state. When the etching stop layer, the second conductive layer and the first conductive layer are subsequently etched, the film layers of the array area and the marking area can be consumed synchronously, which can reduce the probability of the marking area being over-etched, and help to improve the product yield.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0036] Figure 1 Schematic diagram of the marking area in the related art.

[0037] Figure 2 Flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0038] Figure 3 Schematic diagram of the structure of the array area after completing step S120 in the embodiment of the present disclosure.

[0039] Figure 4 Schematic diagram of the marking area in an embodiment of the present disclosure.

[0040] Figure 5 Schematic diagram of the peripheral area in an embodiment of the present disclosure.

[0041] Figure 6 It is a schematic diagram of the array area after completing step S130 in the embodiment of the present disclosure.

[0042] Figure 7It is a schematic diagram of the marking area after completing step S130 in the embodiment of the present disclosure.

[0043] Figure 8 Schematic diagram of a mask material layer and a second photoresist layer in an embodiment of the present disclosure.

[0044] Fig. 9 Schematic diagram of the gate structure in an embodiment of the present disclosure.

[0045] Fig.10 Schematic diagram of an isolation layer and an insulating material layer in an embodiment of the present disclosure.

[0046] Fig.11 Schematic diagram of the array area after completing step S140 in the embodiment of the present disclosure.

[0047] Fig.12 It is a schematic diagram of the marking area after completing step S140 in the embodiment of the present disclosure.

[0048] Fig.13 Schematic diagram of the array area after completing step S210 in the embodiment of the present disclosure.

[0049] Fig.14 It is a schematic diagram of the marking area after completing step S210 in the embodiment of the present disclosure.

[0050] Fig.15 Schematic diagram of the array area after completing step S220 in the embodiment of the present disclosure.

[0051] Fig.16 It is a schematic diagram of the marking area after completing step S220 in the embodiment of the present disclosure.

[0052] Fig.17 Schematic diagram of the array area after completing step S150 in the embodiment of the present disclosure.

[0053] Fig.18 It is a schematic diagram of the marking area after completing step S150 in the embodiment of the present disclosure.

[0054] Fig.19 Schematic diagram of the array area after completing step S310 in the embodiment of the present disclosure.

[0055] Fig. 20 It is a schematic diagram of the marking area after completing step S310 in the embodiment of the present disclosure.

[0056] Description of reference numerals:

[0057] 10. Marking pattern; 20. Substrate; 1. Substrate; 11. Base; 111. Shallow trench isolation structure; 112. Active area; 113. Bit line contact hole; 114. First doped area; 115. Channel area; 116. Second doped area; 12. Insulating layer; 121. First insulating layer; 122. Second insulating layer; 2. First conductive layer; 3. Second conductive layer; 31. Conductive barrier layer; 32. Conductive material layer; 4. Etching stop layer; 5. Insulating cover layer; 51. Insulating portion; 6. Mask layer; 61. Mask structure; 7. Mask material layer; 8. Second photoresist layer; 100. Bit line structure; 200. Marking pattern; 300. Gate structure; 400. Isolation layer; 401. First sub-film layer; 402. Second sub-film layer; 403. Third sub-film layer; 500. Insulating material layer; A. Array area; B. Marking area; C. Peripheral area DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0060] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0061] Usually, a marking pattern 10 is formed simultaneously during the process of manufacturing the bit line structure (BL) of a dynamic random access memory (DRAM). The main process includes: forming a conductive layer for forming the bit line structure and the marking pattern 10 and an insulating layer covering the conductive layer on a substrate 20; etching the insulating layer and the conductive layer step by step to form the bit line structure and the marking pattern 10; however, in the process of etching the insulating layer, in order to ensure that the insulating layer is completely etched through, over-etching will be performed for a certain period of time. During this process, it is inevitable that some areas of the conductive layer will be damaged. This process is superimposed on the subsequent process of forming the bit line contact structure, which may lead to the problem of inconsistent key dimensions of different areas of the finally formed bit line structure; and in the subsequent process, the conductive layer needs to be etched again to form the bit line structure. In this way, the conductive layer undergoes two etching processes, and the etching load effect and necking phenomenon are relatively obvious, and the uniformity of the structural profile is relatively poor. In addition, in the subsequent process of etching the conductive layer to form the bit line structure, due to the influence of the process technology (etching load effect or plasma), the etching progress of different areas may be different, and the phenomenon of over-etching of the marking area is prone to occur (such as Figure 1 (As shown in area a in the middle), the structural defects are quite obvious and the product yield is low.

[0062] Based on this, the present disclosure provides a method for forming a semiconductor structure. Figure 2 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 2 As shown, the forming method includes steps S110 to S150, wherein:

[0063] Step S110, providing a substrate, wherein the substrate comprises a base and an insulating layer, the base comprises an array region and a marking region, a shallow trench isolation structure and a plurality of active regions separated by the shallow trench isolation structure are provided in the array region, and the insulating layer covers the shallow trench isolation structure, the active region and the marking region;

[0064] Step S120, etching the active area and the insulating layer located on the top of the active area to form a bit line contact hole;

[0065] Step S130, forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole;

[0066] Step S140, etching the insulating cover layer to form insulating portions in the array region and the mark region respectively, wherein an orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; an etching rate of the etching stop layer is less than an etching rate of the insulating cover layer;

[0067] Step S150 , etching the etching stop layer, the second conductive layer, and the first conductive layer using the insulating portion as a mask to form a bit line structure in the array region and to form a mark pattern in the mark region.

[0068] The method for forming a semiconductor structure disclosed in the present invention provides an etching stop layer below the insulating cover layer, so that when etching the insulating cover layer to form an insulating portion, the etching endpoint can be stopped on the etching stop layer, and in this process, the structure of the second conductive layer below will not be damaged, thereby avoiding the problem of uneven etching loss in different regions of the second conductive layer, which helps to improve the uniformity of the key dimensions of the finally formed bit line structure. When the second conductive layer is subsequently etched, the second conductive layer can be etched through by the same etching process, avoiding the load effect and necking phenomenon caused by different etching times, which helps to improve the profile of the bit line structure and further improve the uniformity of the bit line structure. In addition, since the etching rate of the etching stop layer is relatively small, the surface of the etching stop layer will not be greatly damaged in the process of forming the insulating portion, and different regions of the etching stop layer are still in a relatively flat state. When the etching stop layer, the second conductive layer and the first conductive layer are subsequently etched, the film layers of the array area and the marking area can be consumed synchronously, which can reduce the probability of the marking area being over-etched, and help to improve the product yield.

[0069] The steps and specific details of the method for forming a semiconductor structure disclosed in the present invention are described in detail below:

[0070] like Figure 2 As shown, in step S110, a substrate is provided, the substrate comprising a base and an insulating layer, the base comprising an array area and a marking area, a shallow trench isolation structure and a plurality of active areas separated by the shallow trench isolation structure are provided in the array area, and the insulating layer covers the shallow trench isolation structure, the active area and the marking area.

[0071] like Figure 3 and Figure 4 As shown, the substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made to the shape and material of the substrate 11 herein.

[0072] In some embodiments of the present disclosure, please continue to refer to Figure 3 and Figure 4 As shown, the substrate 11 may include an array area A and a marking area B. The marking area B may be located at the periphery of the array area A, and the marking area B may surround the periphery of the array area A. For example, the array area A may be a circular area, a rectangular area, or an irregular pattern area. Of course, it may also be an area of ​​other shapes, which is not particularly limited here. The marking area B may be an annular area and may surround the periphery of the array area A. It may be a circular ring area, a rectangular ring area, or an annular area of ​​other shapes, which are not listed here one by one. The array area A can be used to form a capacitor array, a transistor array, a word line structure and a bit line structure connecting transistors and capacitors, and the marking area B can be used to form a marking pattern, which can be used as a positioning mark during the process.

[0073] In some embodiments of the present disclosure, the substrate 11 may be a silicon substrate, and a shallow trench isolation structure 111 is formed inside the array area A of the substrate 11. The shallow trench isolation structure 111 can be formed by forming a trench in the substrate 11 and then filling the trench with an isolation material layer. The material of the shallow trench isolation structure 111 may include silicon nitride or silicon oxide, etc., which is not particularly limited here. The cross-sectional shape of the shallow trench isolation structure 111 can be set according to actual needs. The shallow trench isolation structure 111 can separate a plurality of active areas 112 on the substrate 11.

[0074] In an exemplary embodiment of the present disclosure, Figure 5 As shown, the substrate 11 may further include a peripheral region C, which may be arranged side by side with the array region A and the marking region B. For example, the peripheral region C may be arranged adjacent to the array region A, the peripheral region C may surround the periphery of the array region A, and the marking region B may be located on a side of the peripheral region C away from the array region A. The peripheral region C may be used to form word line contact plugs and peripheral transistors. In some embodiments of the present disclosure, the peripheral region C may include a first doping region 114, a channel region 115, and a second doping region 116 that are sequentially adjacently arranged.

[0075] The insulating layer 12 can cover the surface of the substrate 11 in a conformal manner. It can be a thin film formed on the substrate 11 or a coating formed on the substrate 11. The specific form of the insulating layer 12 is not specifically limited here. For example, the insulating layer 12 can be formed on the surface of the substrate 11 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the insulating layer 12 can also be formed by other methods. The formation method of the insulating layer 12 is not specifically limited here. The insulating layer 12 can be a single-layer film structure or a composite film structure composed of multiple film layers. The specific form of the insulating layer 12 is not specifically limited here. In some embodiments of the present disclosure, the insulating layer 12 may include a first insulating layer 121 and a second insulating layer 122, wherein the first insulating layer 121 may cover the surface of the shallow trench isolation structure 111, each active area 112 and the marking area B, and the second insulating layer 122 may cover the surface of the first insulating layer 121, and the end of the second insulating layer 122 is flush with the end of the first insulating layer 121. The first insulating layer 121 and the second insulating layer 122 are made of different materials. For example, the first insulating layer 121 may be made of silicon oxide, and the second insulating layer 122 may be made of silicon nitride.

[0076] like Figure 2 As shown, in step S120 , the active area 112 and the insulating layer 12 located on the top of the active area 112 are etched to form a bit line contact hole 113 .

[0077] A photoresist layer may be formed on the surface of the insulating layer 12 by spin coating or other methods. The material of the photoresist layer may be a positive photoresist or a negative photoresist, which is not particularly limited herein. The photoresist layer is exposed using a mask, and the pattern of the mask may match the pattern required for the bit line contact hole 113. Subsequently, the exposed photoresist layer may be developed to form a plurality of spaced development areas, each of which may expose the surface of the insulating layer 12. In a direction parallel to the substrate 11, the shape of the development area may be circular or rectangular, and the orthographic projection of the development area on the substrate 11 may at least partially overlap with the active area 112.

[0078] The active area 112 and the insulating layer 12 located on the top of the active area 112 can be etched in each developing area by an isotropic etching process. In this process, the insulating layer 12 can be penetrated, and the top height of the active area 112 directly opposite to the developing area can be reduced. The hole segment formed by the recessed portion in the active area 112 after etching and the through hole in the insulating layer 12 corresponding to the recessed portion can be used as the bit line contact hole 113. The structure after completing step S120 in the embodiment of the present disclosure is as follows: Figure 3 shown.

[0079] like Figure 2As shown, in step S130 , a first conductive layer 2 , a second conductive layer 3 , an etching stop layer 4 and an insulating cover layer 5 are sequentially formed on a side of the insulating layer 12 away from the substrate 11 , and the first conductive layer 2 fills the bit line contact hole 113 .

[0080] See also Figure 6 and Figure 7 As shown, the first conductive layer 2, the second conductive layer 3, the etching stop layer 4 and the insulating cover layer 5 can be stacked and distributed in sequence along a direction perpendicular to the substrate 11. In some embodiments of the present disclosure, the material of the first conductive layer 2 can be doped polysilicon, and the first conductive layer 2 can be formed on the surface of the insulating layer 12 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, the first conductive layer 2 can cover the entire surface of the insulating layer 12 and fill the bit line contact holes 113.

[0081] The second conductive layer 3 can be a single film layer or a multi-layer film layer, which is not specifically limited here. Optionally, the second conductive layer 3 can be a composite film layer structure composed of multiple film layers, for example, the second conductive layer 3 can include a conductive barrier layer 31 and a conductive material layer 32, wherein the conductive barrier layer 31 covers the surface of the first conductive layer 2, and the conductive material layer 32 is located on the surface of the conductive barrier layer 31; the material of the conductive barrier layer 31 can be titanium nitride, and the material of the conductive material layer 32 can be tungsten, and the conductive barrier layer 31 can prevent the metal ions in the conductive material layer 32 from diffusing into the first conductive layer 2, which helps to improve the stability of the device; at the same time, the resistance of the conductive material layer 32 is relatively small, which helps to improve the conductivity.

[0082] In some embodiments of the present disclosure, the material of the etching stop layer 4 may be an insulating material. For example, the material of the etching stop layer 4 is non-doped silicon, for example, it may be non-doped single crystal silicon or non-doped polycrystalline silicon, etc. Compared with doped silicon, non-doped silicon can reduce the resistance and parasitic capacitance of the subsequent bit line structure. The thickness of the etching stop layer 4 may be less than the thickness of the insulating cover layer 5, and its thickness may be greater than one-fifteenth of the thickness of the insulating cover layer 5. The etching stop layer 4 may be formed on the surface of the second conductive layer 3 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the etching stop layer 4 may also be formed by other methods. The formation method of the etching stop layer 4 is not specifically limited here. It should be noted that in the process, for the convenience of the process, the etching stop layer 4 can be covered with the surface of the second conductive layer 3, that is, the orthographic projection of the etching stop layer 4 on the substrate 11 covers the array area A, the peripheral area C and the marking area B.

[0083] In some embodiments of the present disclosure, in order to prevent the setting of the etching stop layer 4 from affecting the electrical performance of the transistor subsequently formed in the peripheral region C, before forming the insulating cover layer 5, the etching stop layer 4 located in the peripheral region C can be removed by a dry etching process. For example, a first photoresist layer can be formed on the surface of the etching stop layer 4 by spin coating or other methods. The material of the first photoresist layer can be photoresist. The first photoresist layer is exposed and developed to form a development area. The positive projection of the development area on the substrate 11 overlaps with the peripheral region C at least partially. The etching stop layer 4 is dry-etched in the development area to remove the etching stop layer 4 located on the peripheral region C. In this process, the etching rate of the etching gas used relative to the second conductive layer 3 is much lower than the etching rate relative to the etching stop layer 4, so as to avoid damaging the second conductive layer 3 below it during the removal of the etching stop layer 4. For example, when the material of the etching stop layer 4 is undoped silicon and the material of the film layer near the etching stop layer 4 in the second conductive layer 3 is tungsten, the etching stop layer 4 can be etched by a gas containing hydrogen bromide to remove the etching stop layer 4 located on the peripheral region C.

[0084] After removing the etching stop layer 4 located in the peripheral area C, the first photoresist layer may be removed, and an insulating cover layer 5 may be formed, and the insulating cover layer 5 may cover the surface of the remaining etching stop layer 4 and the surface of the second conductive layer 3 in the peripheral area C that is not covered by the etching stop layer 4. In some embodiments of the present disclosure, the material of the insulating cover layer 5 may be silicon nitride, and the insulating cover layer 5 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the insulating cover layer 5 may also be formed by other methods, and the formation method of the insulating cover layer 5 is not particularly limited here.

[0085] In some embodiments of the present disclosure, after forming the insulating cover layer 5, the forming method of the present disclosure may further include:

[0086] Step S1301 , etching the insulating cover layer 5 , the second conductive layer 3 , the first conductive layer 2 , and the insulating layer 12 located in the peripheral region C to form a gate structure.

[0087] A mask material layer 7 may be formed on the surface of the insulating cover layer 5 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the material of the mask material layer 7 may include a spin-on hard mask (SOH); then a photoresist material layer may be formed on the surface of the mask material layer 7 by spin coating or other methods, and the photoresist material layer may be exposed and developed to form a second photoresist layer 8, such as Figure 8 As shown, the orthographic projection of the second photoresist layer 8 on the substrate 11 can cover the array region A, the mark region B and the channel region of the peripheral region C.

[0088] like Fig. 9As shown, the mask material layer 7 not covered by the second photoresist layer 8 and the insulating cover layer 5, the second conductive layer 3, the first conductive layer 2 and the insulating layer 12 directly below the mask material layer 7 may be etched to form a gate structure 300 in the peripheral region C. It should be noted that after the gate structure 300 is formed, the second photoresist layer 8 may be removed by ashing or other processes, thereby exposing the gate structure 300 and the top of the insulating cover layer 5.

[0089] In some embodiments of the present disclosure, the forming method of the present disclosure may further include step S1302 and step S1303, wherein:

[0090] Step S1302 , forming an isolation layer 400 covering the sidewalls and the top of the gate structure 300 .

[0091] The material of the isolation layer 400 may be an insulating material, and the isolation layer 400 may be used to insulate and protect the surface of the gate structure 300 to reduce the risk of short circuit or coupling between the gate structure 300 and other surrounding structures. The isolation layer 400 may be a composite film layer structure composed of multiple layers of thin films. For example, the isolation layer 400 may include a first sub-film layer 401, a second sub-film layer 402, and a third sub-film layer 403, and the first sub-film layer 401, the second sub-film layer 402, and the third sub-film layer 403 may sequentially conformally cover the sidewalls and top of the gate structure 300, that is, the first sub-film layer 401 may conformally cover the sidewalls and surface of the gate structure 300, and the second sub-film layer 402 may be located between the first sub-film layer 401 and the third sub-film layer 403. The material of the first sub-film layer 401 may be the same as that of the third sub-film layer 403, and the material of the second sub-film layer 402 may be different from that of the first sub-film layer 401. For example, the material of the first sub-film layer 401 and the material of the third sub-film layer 403 may both be silicon nitride, and the material of the second sub-film layer 402 may be silicon oxide.

[0092] Step S1303 , forming an insulating material layer 500 in the peripheral region C outside the gate structure 300 and the isolation layer 400 , wherein the surface of the insulating material layer 500 is flush with the surface of the isolation layer 400 located on the top of the gate structure 300 .

[0093] like Fig.10As shown, an insulating material can be deposited on the surface of the structure formed by the substrate 1, the gate structure 300, and the isolation layer 400 exposed in the peripheral area C by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The insulating material can at least fill the height difference between the surface of the isolation layer 400 on the top of the gate structure 300 and the surface of the substrate 1; then, the surface of the insulating material can be modified by back etching or grinding to make the surface of the remaining insulating material flush with the surface of the isolation layer 400 on the top of the gate structure 300, and the remaining insulating material can be used as an insulating material layer 500.

[0094] In some embodiments of the present disclosure, step S140 may be performed after the insulating material layer 500 is formed.

[0095] like Figure 2 As shown, in step S140, the insulating covering layer 5 is etched to form insulating portions 51 in the array area A and the marking area B, respectively, and the orthographic projection of the insulating portion 51 located in the array area A on the substrate 11 at least partially overlaps with the active area 112 located in the bit line contact hole 113; the etching rate of the etching stop layer 4 is less than the etching rate of the insulating covering layer 5.

[0096] like Fig.11 and Fig.12 As shown, in the process of etching to form the insulating portion 51, the etching endpoint can be stopped on the etching stop layer 4, and no damage will be caused to the structure of the second conductive layer 3 below, thereby avoiding the problem of uneven etching loss in different areas of the second conductive layer 3, and helping to improve the uniformity of the key dimensions of the finally formed bit line structure 100.

[0097] In some embodiments of the present disclosure, the etching selectivity ratio of the insulating cover layer 5 to the etching stop layer 4 is greater than 10: 1. Since the etching rate of the etching stop layer 4 is relatively small, the surface of the etching stop layer 4 will not be greatly damaged during the formation of the insulating portion 51, and different regions of the etching stop layer 4 are still in a relatively flat state. When the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 are subsequently etched, the film layers of the array area A and the marking area B can be consumed synchronously, which can reduce the probability of the marking area B being over-etched, and help improve the product yield.

[0098] In an exemplary embodiment of the present disclosure, the insulating cover layer 5 is etched to form insulating portions 51 in the array region A and the mark region B, respectively (ie, step S140), including steps S210 to S230, wherein:

[0099] Step S210 , forming a mask layer 6 on the surface of the insulating cover layer 5 .

[0100] A mask layer 6 can be formed on the surface of the insulating covering layer 5 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The mask layer 6 can be a multi-layer film structure or a single-layer film structure. Its material can be at least one of a carbon film layer, SiO2, SiN, polysilicon and SiCN. Of course, it can also be other materials, which are not listed here one by one.

[0101] In some embodiments, the mask layer 6 may be a multilayer, which may include a silicon oxynitride layer and a carbon film layer. The carbon film layer may be first formed on the surface of the insulating cover layer 5, and then the silicon oxynitride layer may be formed on the surface of the carbon film layer.

[0102] In step S220 , the mask layer 6 is etched to form mask structures 61 in the array area A and the mark area B respectively, and the orthographic projection of the mask structure 61 in the array area A on the substrate 11 at least partially overlaps with the active area 112 in the bit line contact hole 113 .

[0103] The number of the mask structures 61 can be multiple, and the multiple mask structures 61 can be distributed at intervals; Fig.15 As shown, the orthographic projection of a portion of the mask structure 61 on the substrate 11 is located in the array region A, and the orthographic projection of the portion of the mask structure 61 on the substrate 11 at least partially overlaps with the active region 112 in the bit line contact hole 113; Fig.16 As shown, the orthographic projection of another portion of the mask structure 61 on the substrate 11 is located within the marking area B.

[0104] In step S230 , the insulating cover layer 5 is etched using the mask layer 6 having the mask structure 61 as a mask to form the insulating portion 51 in the array region A and the mark region B respectively.

[0105] The insulating cover layer 5 can be etched by a dry etching process using the mask layer 6 as a mask, thereby forming a plurality of insulating portions 51. The etching gas for dry etching can be set according to the materials of the insulating cover layer 5 and the etching stop layer 4 under the insulating cover layer 5 to ensure that the etching selectivity of the etching gas to the insulating cover layer 5 is much greater than its etching selectivity to the etching stop layer 4. For example, when the material of the insulating cover layer 5 is silicon nitride and the material of the etching stop layer 4 is undoped silicon, the etching gas can be a mixture of CH2FCHF2, oxygen and argon.

[0106] like Figure 2 As shown, in step S150, the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 are etched using the insulating portion 51 as a mask to form a bit line structure 100 in the array region A and a mark pattern 200 in the mark region B.

[0107] Each insulating portion 51 can be used as a mask to etch the etching stop layer 4, the first conductive layer 2 and the second conductive layer 3 thereunder, thereby forming a bit line structure 100 and a marking pattern 200. In the present disclosure, after the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 are etched, the insulating portion 51 located in the array area A and the remaining etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 thereunder together constitute the bit line structure 100; the insulating portion 51 located in the marking area B and the remaining etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 thereunder together constitute the marking pattern 200. In the embodiment of the present disclosure, the structure of the array area after completing step S150 is as follows: Fig.17 After completing step S150, the structure of the marking area is as shown in Fig.18 shown.

[0108] In an exemplary embodiment of the present disclosure, etching the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 using the insulating portion 51 as a mask to form a bit line structure 100 in the array area A and forming a mark pattern 200 in the mark area B (i.e., step S150) includes steps S310 and S320, wherein:

[0109] In step S310 , the etching stop layer 4 is etched using the insulating portion 51 as a mask until the second conductive layer 3 is exposed.

[0110] In some embodiments of the present disclosure, after forming the insulating portion 51, the mask layer 6 can be removed to expose the top of the insulating portion 51, and then the etching stop layer 4 can be dry-etched using the insulating portion 51 as a mask to remove the etching stop layer 4 in the area not covered by the insulating portion 51; in this process, the etching gas can be set according to the specific materials of the etching stop layer 4, the insulating portion 51, and the top film layer in the second conductive layer 3 below, so as to minimize damage to the surface of the second conductive layer 3 without destroying the shape and size of the insulating portion 51. For example, when the material of the insulating portion 51 is silicon nitride, the material of the etching stop layer 4 is undoped silicon, and the material of the top film layer in the second conductive layer 3 is tungsten, the etching gas can be a mixed gas including hydrogen bromide. In the embodiment of the present disclosure, after completing step S310, the structure of the array area is as follows: Fig.19 After completing step S310, the structure of the marking area is as shown in Fig. 20 shown.

[0111] In step S320, the second conductive layer 3 and the first conductive layer 2 are etched using the structure formed by the insulating portion 51 and the remaining etching stop layer 4 as a mask to form a bit line structure 100 in the array area A and a marking pattern 200 in the marking area B.

[0112] The insulating portion 51 and the remaining etching stop layer 4 thereunder can be used together as a mask to perform dry etching on the second conductive layer 3 and the first conductive layer 2. In this process, since the second conductive layer 3 has not been etched before, the second conductive layer 3 can be etched through in one etching process, thereby avoiding the load effect and necking phenomenon caused by different etching times, helping to improve the profile of the bit line structure 100 and further improving the uniformity of the bit line structure 100.

[0113] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include:

[0114] Step S160, detecting the width of the insulating portion 51 in a direction parallel to the substrate 11, and when the width is within a first preset deviation range, etching the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 using the insulating portion 51 as a mask to form a bit line structure 100 in the array area A, and forming a marking pattern 200 in the marking area B.

[0115] For example, after forming the insulating portion 51 and before etching the etching stop layer 4, the width of the insulating portion 51 in the direction parallel to the substrate 11 can be detected by critical dimension (CD) detection, and the detected width values ​​of each insulating portion 51 can be compared. When the difference in the width values ​​of each insulating portion 51 is within the first preset deviation range, it is determined that the etching process of the insulating portion 51 meets the process standard, and the next etching step can be performed (for example, etching the etching stop layer 4, the second conductive layer 3, and the first conductive layer 2 using the insulating portion 51 as a mask). The first preset deviation range can be 0nm to 5nm, that is, when the absolute value of the difference in the width of the two insulating portions 51 with the largest size difference among the insulating portions 51 is within 5nm (including 5nm), it can be considered that the width of the insulating portion 51 in the direction parallel to the substrate 11 is within the first preset deviation range.

[0116] It should be noted that when the difference in the width values ​​of each insulating portion 51 is outside the first preset deviation range, it is determined that the etching process of the insulating portion 51 does not meet the process standard, and the detection result can be fed back to the etching machine; so as to adjust the process parameters of the etching process for forming the insulating portion 51 according to the detection result; after the process parameters are adjusted, the above process can be repeated to form a new insulating portion 51 until the width of the formed insulating portion 51 in the direction parallel to the substrate 11 is within the first preset deviation range, and then continue with the next process (i.e., execute step S150).

[0117] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include:

[0118] Step S170, detecting the widths of different film layers in the bit line structure 100 in a direction parallel to the substrate 11, and when the width difference of different film layers in the bit line structure 100 in a direction parallel to the substrate 11 exceeds a second preset deviation range, feeding back the detection result to an etching machine used to etch the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2.

[0119] After forming the bit line structure 100 and the marking pattern 200, the width of the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 in the direction parallel to the substrate 11 can be measured by optically measuring the critical dimension (OCD), and the width values ​​of each film layer detected can be compared. When the difference in the width values ​​of different film layers is within the second preset deviation range, it is determined that the etching process of the etching stop layer 4, the second conductive layer 3, and the first conductive layer 2 meets the process standard. The second preset deviation range can be 0nm to 8nm, that is, when the absolute value of the difference in the width of the two film layers with the largest size difference in different film layer structures is within 8nm (including 8nm), it can be considered that the width of the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 in the direction parallel to the substrate 11 is within the second preset deviation range.

[0120] It should be noted that when the difference in the width values ​​of the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 is outside the second preset deviation range, it is determined that the etching process of the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 does not meet the process standard, and the detection result can be fed back to the etching machine, so as to adjust the process parameters for etching the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 according to the detection result, so as to control the profile of the bit line structure 100 more accurately in the future. At the same time, since the profile of the bit line structure 100 is accurately controlled through two-step closed-loop detection (CD detection and OCD detection), the probability of the bit line structure 100 having dimensional abnormalities is reduced, which helps to increase the process window of the capacitor hole used to form the capacitor plug in the future, thereby reducing the process difficulty.

[0121] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0122] The embodiments of the present disclosure further provide a semiconductor structure, which can be formed by the method for forming a semiconductor structure of any of the above embodiments.

[0123] The specific details and manufacturing processes of each part of the above-mentioned semiconductor structure have been described in detail in the corresponding semiconductor structure forming method, and therefore, they will not be repeated here.

[0124] For example, the semiconductor structure may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.

[0125] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and an insulating layer, the base comprising an array area and a marking area, the array area being provided with a shallow trench isolation structure and a plurality of active areas separated by the shallow trench isolation structure, the insulating layer covering the shallow trench isolation structure, the active area and the marking area; Etching the active area and the insulating layer located on the top of the active area to form a bit line contact hole; forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole; Etching the insulating cover layer to form insulating portions in the array region and the mark region respectively, wherein an orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; The etching rate of the etching stop layer is lower than the etching rate of the insulating cover layer; The etching stop layer, the second conductive layer and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

2. The forming method according to claim 1, characterized in that: An etching selectivity ratio of the insulating cover layer to the etching stop layer is greater than 10:

1.

3. The forming method according to claim 1, characterized in that: The material of the etching stop layer is non-doped silicon, and the material of the insulating cover layer is silicon nitride.

4. The forming method according to any one of claims 1 to 3, characterized in that: The etching of the insulating cover layer to form insulating portions in the array area and the mark area respectively includes: forming a mask layer on a surface of the insulating cover layer; Etching the mask layer to form mask structures in the array region and the mark region respectively, wherein an orthographic projection of the mask structure in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; The insulating cover layer is etched using the mask layer having the mask structure as a mask to form the insulating portions in the array region and the mark region respectively.

5. The forming method according to any one of claims 1 to 3, characterized in that: The etching stop layer, the second conductive layer and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a mark pattern in the mark area, including: Using the insulating portion as a mask, etching the etching stop layer until the second conductive layer is exposed; The second conductive layer and the first conductive layer are etched using the structure formed by the insulating portion and the remaining etching stop layer as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

6. The forming method according to any one of claims 1 to 3, characterized in that: The forming method further comprises: The width of the insulating portion in a direction parallel to the substrate is detected, and when the width is within a first preset deviation range, the etching stop layer, the second conductive layer and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a marking pattern in the marking area.

7. The forming method according to any one of claims 1 to 3, characterized in that: The forming method further comprises: The widths of different film layers in the bit line structure in a direction parallel to the substrate are detected, and when the width difference of different film layers in the bit line structure in a direction parallel to the substrate exceeds a second preset deviation range, the detection result is fed back to an etching machine used to etch the etching stop layer, the second conductive layer, and the first conductive layer.

8. The forming method according to any one of claims 1 to 3, characterized in that: The substrate further includes a peripheral area, the peripheral area is arranged side by side with the array area and the marking area, and the orthographic projection of the etching stop layer on the substrate covers the array area, the peripheral area and the marking area; Before forming the insulating cover layer, the forming method further comprises: removing the etching stop layer located in the peripheral area; After forming the insulating cover layer, the forming method further comprises: The insulating cover layer, the second conductive layer, the first conductive layer and the insulating layer in the peripheral region are etched to form a gate structure.

9. The forming method according to claim 8, characterized in that: The forming method further comprises: forming an isolation layer covering the sidewalls and top of the gate structure; An insulating material layer is formed in the peripheral region outside the gate structure and the isolation layer, and a surface of the insulating material layer is flush with a surface of the isolation layer located on the top of the gate structure.

10. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 9.

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