Semiconductor common block structure, semiconductor memory and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor common block structure, a semiconductor memory and a preparation method thereof, and the semiconductor common block structure comprises a semiconductor common unit structure, a source drain layer and a shielding cover structure. The semiconductor common unit structure comprises a first storage unit and a second storage unit which are distributed side by side in a mirroring manner along a first direction, the first storage unit and the second storage unit share the same source-drain unit layer, and the first direction is parallel to the surface of the substrate; each of the first memory unit and the second memory unit comprises a first transistor and a second transistor, and a fourth source-drain region of the second transistor in the first memory unit and a fourth source-drain region of the second transistor in the second memory unit are respectively connected to two opposite surfaces of the source-drain unit layer; and all the source-drain unit layers in the same plane are sequentially connected end to end to form a source-drain layer. The shielding case structure accommodates all the second transistors therein, and all the first transistors are located outside the shielding case structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor common block structure, a semiconductor memory and a method for manufacturing the same. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. Traditional DRAM storage cells usually include transistors and capacitors. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information is written into the capacitor. This structure needs to continuously refresh the charge in the capacitor to ensure that the data is not lost, and the charge in the capacitor needs to be released when reading, and then rewritten after the reading is completed, which consumes a lot of power. At the same time, due to the large area occupied by the manufacturing process of the capacitor, size miniaturization becomes a problem.

[0003] The two-transistor capacitorless dynamic random access memory (2Transistor 0Capacitor, 2T0C) uses two vertical structure transistors as the unit structure, where the drain of one transistor is connected to the gate of the other transistor, and the gate capacitance is used to store charge and change the transistor transconductance to store information. This structure can increase the storage density by continuously increasing the number of stacked layers in the vertical direction without reducing the critical size. However, each layer of devices needs to be completed before the next layer of devices can be made. The process is long, the cost is high, and the device reliability is low.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a semiconductor common block structure, a semiconductor memory and a preparation method thereof, which can simplify the process flow, reduce manufacturing costs, increase storage density, and reduce interference of external electric fields on charge storage areas.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor common block structure, which is prepared on a substrate and includes:

[0007] A plurality of semiconductor common unit structures located on the substrate, the semiconductor common unit structures comprising: a first storage unit and a second storage unit, the first storage unit and the second storage unit are arranged side by side in a mirror image along a first direction, the first storage unit and the second storage unit share a same source-drain unit layer, and the first direction is parallel to the surface of the substrate;

[0008] Wherein, the first storage unit and the second storage unit both include:

[0009] a first transistor, located above the top surface of the substrate, the first transistor comprising: a first gate, a first gate dielectric layer and a first semiconductor layer, the first gate extending along the first direction, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, the first semiconductor layer covering the surface of the first gate dielectric layer, and the first semiconductor layer comprising a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction; a second transistor, arranged side by side with the first transistor along the first direction, the second transistor comprising a second gate, a second gate dielectric layer and a second semiconductor layer, the second gate extending along the first direction, the second gate dielectric layer conformally covering the sidewall and the end of the second gate away from the first transistor, the second semiconductor layer covering the surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction; the second source and drain region is conductively connected to the second gate, the fourth source and drain region in the first storage unit and the fourth source and drain region in the second storage unit are respectively connected to two opposite surfaces of the source and drain unit layer;

[0010] The plurality of semiconductor common unit structures are arranged at intervals along a second direction and a third direction, the second direction is parallel to the substrate and intersects the first direction, and the third direction is perpendicular to the first direction and the second direction;

[0011] A source-drain layer, formed by sequentially connecting all the source-drain unit layers in the same plane end to end;

[0012] The shielding cover structure has a shielding inner cavity, all the second transistors are accommodated in the shielding inner cavity, and all the first transistors are located outside the shielding cover structure.

[0013] In an exemplary embodiment of the present disclosure, the shielding cover structure is a shell structure, which includes at least one shell layer of conductive material.

[0014] In an exemplary embodiment of the present disclosure, the semiconductor common block structure further includes:

[0015] a plurality of word lines extending along the second direction and arranged at intervals along the first direction and the third direction, each of the word lines being connected to gates of a row of the first transistors arranged along the second direction in the same plane;

[0016] a plurality of first bit lines extending along the third direction and arranged at intervals along the first direction and the second direction, each of the first bit lines covering an outer periphery of a row of the first source and drain regions arranged along the third direction in the same plane;

[0017] A plurality of second bit lines extend along the third direction and are arranged at intervals along the first direction and the second direction, each of the second bit lines covers the periphery of a row of the third source and drain regions arranged along the third direction in the same plane.

[0018] In an exemplary embodiment of the present disclosure, the word line includes a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the third direction, the orthographic projections of any two lead-out ends of the word lines on the substrate do not overlap, and the orthographic projections of any two main extension portions of the word lines on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each word line decreases or increases successively.

[0019] In an exemplary embodiment of the present disclosure, the semiconductor common block structure further includes:

[0020] The connecting line extends along the third direction and is connected to the lead-out end of the word line.

[0021] According to one aspect of the present disclosure, there is provided a semiconductor memory, comprising:

[0022] A substrate and a plurality of semiconductor common block structures as described above located on the substrate, wherein the plurality of semiconductor common block structures are arranged along the first direction;

[0023] Two adjacent semiconductor common block structures are arranged independently of each other.

[0024] According to one aspect of the present disclosure, there is provided a method for preparing a semiconductor memory, comprising:

[0025] providing a substrate;

[0026] A first memory cell and a second memory cell are formed on the substrate, wherein the first memory cell and the second memory cell are arranged side by side in a mirror image along a first direction, wherein the first direction is parallel to the surface of the substrate; the first memory cell and the second memory cell each include a first transistor and a second transistor arranged side by side along the first direction, wherein a source and drain region of the first transistor is electrically connected to a gate of the second transistor;

[0027] forming a shielding cover structure for accommodating the second transistor of the first storage unit and the second transistor of the second storage unit in the shielding inner cavity;

[0028] A source-drain unit layer is formed between the first memory cell and the second memory cell; a source-drain region of the second transistor of the first memory cell and a source-drain region of the second transistor of the second memory cell are respectively connected to two opposite sides of the source-drain unit layer.

[0029] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0030] Before forming the second transistor, forming a word line material layer;

[0031] The first transistor, the second transistor, the word line material layer and the shielding cover structure are formed on the substrate, including:

[0032] Alternatingly depositing a first insulating material layer and a semiconductor material layer on the substrate in sequence to form a stacked structure;

[0033] Performing patterning on the stacked structure to form a patterned stacked structure, wherein the pattern of the patterned stacked structure includes a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction is parallel to the surface of the substrate, the second direction is parallel to the substrate and intersects with the first direction; the first pattern overlaps with the second pattern;

[0034] forming a second insulating material layer filling the gaps in the patterned stacked structure;

[0035] A plurality of first openings are formed along a third direction penetrating the patterned stacked structure and the second insulating material layer, the first openings being arranged in one-to-one correspondence with the second patterns, and the first openings divide the corresponding second pattern into two sub-patterns that are distributed side by side in a mirror image along the first direction; the third direction is perpendicular to the first direction and the second direction, and the first openings are parallel to the plane where the second direction and the third direction are located;

[0036] Part of the semiconductor material layer is etched away laterally toward both sides through the first opening to form a plurality of accommodating portions, wherein the accommodating portions include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and a word line accommodating groove extending along the second direction and connected to the row of first transistor accommodating grooves;

[0037] A first semiconductor layer, a first gate dielectric layer and a first gate material layer are sequentially deposited in the accommodation portion; the first semiconductor layer covers the side wall and the bottom surface of the accommodation portion, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the accommodation portion;

[0038] The first gate material layer deposited in the word line accommodating groove is etched away to form a first gate of the first transistor, and then the word line accommodating groove is filled with word line material to form a word line material layer, wherein the word line material layer is in contact with and connected to the first gate; the first transistor comprises the first gate, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, and the first semiconductor layer on the first gate comprises a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction;

[0039] Forming a plurality of second openings along the third direction penetrating the patterned stacked structure and the second insulating material layer filled inside the patterned stacked structure, wherein the second openings are located at a middle position between two adjacent first openings, and the second openings are parallel to the second direction and the plane where the third direction is located;

[0040] Etching away a portion of the first insulating material layer laterally toward both sides through the second opening to form a second gate of the second transistor, and etching away a portion of the second insulating material layer toward both sides of the patterned stacked structure along the second direction to define an outline of the shielding cover structure;

[0041] A second gate dielectric layer and a second semiconductor layer are sequentially deposited on the exposed surface of the second gate and the contour surface of the shielding cover structure, the second gate dielectric layer conformally covers the side wall of the second gate, the end of the second gate away from the first transistor and the contour surface of the shielding cover structure, the second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer located on the second gate includes a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction.

[0042] In an exemplary embodiment of the present disclosure, before forming a plurality of first openings penetrating the patterned stacked structure and the second insulating material layer along the third direction, the method for preparing the semiconductor memory further includes:

[0043] forming an etch stop layer embedded in the second insulating material layer;

[0044] Forming the second insulating material layer and the etch stop layer includes:

[0045] Depositing a third insulating material layer on the exposed surfaces of the substrate and the patterned stacked structure, wherein the third insulating material layer fills a gap between two adjacent first patterns in the patterned stacked structure, and depositing an etching stop material layer on the surface of the third insulating material layer;

[0046] The remaining gaps in the patterned stacking structure are filled with insulating material and flattened to form the second insulating material layer and the etching stop layer. The second insulating material layer, the etching stop layer and the upper surface of the patterned stacking structure are flush, and the etching stop layer is used to define the shape and size of the shielding cover structure in the first direction.

[0047] In an exemplary embodiment of the present disclosure, the step of etching away a portion of the first insulating material layer laterally toward both sides through the second opening to form a second gate of the second transistor, and etching away a portion of the second insulating material layer toward both sides of the patterned stacked structure along the second direction to define the outline of the shielding cover structure includes:

[0048] The first insulating material layer is etched away laterally toward both sides through the second opening, and the second insulating material layer is etched away toward both sides of the patterned stacked structure along the second direction. The etching stops when the etching stops.

[0049] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0050] After forming the second semiconductor layer, a filling layer is formed to fill the shielding inner cavity of the shielding cover structure, and the filling layer closes the second opening.

[0051] In an exemplary embodiment of the present disclosure, a source-drain unit layer is formed between the first memory unit and the second memory unit, including:

[0052] forming a plurality of third openings penetrating the filling layer along the third direction, wherein the third openings are located within the second openings and expose the fourth source and drain regions in the second transistor, and the third openings are parallel to the second direction and the plane where the third direction is located;

[0053] Filling a conductive material in the third opening to form a source-drain unit layer;

[0054] The method for preparing the semiconductor memory further includes:

[0055] Etching the first insulating material layer and the second insulating material layer to form a plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction;

[0056] A first bit line is formed in the first bit line accommodating hole, and a second bit line is formed in the second bit line accommodating hole; each of the first bit lines is wrapped around the periphery of a row of the first source and drain regions arranged in the same plane along the third direction, and each of the second bit lines is wrapped around the periphery of a row of the third source and drain regions arranged in the same plane along the third direction.

[0057] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0058] Each of the word line material layers and the first insulating material layer and the second insulating material layer covering each of the word lines are processed to form a plurality of word lines extending along the second direction and arranged at intervals along the third direction, wherein the word lines include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the word line lead-out structure, the orthographic projections of any two of the word lines' lead-out ends on the substrate do not overlap, and the orthographic projections of any two of the word lines' main extension portions on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the word lines decreases successively.

[0059] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0060] forming a covering layer on a side of each of the lead-out ends away from the substrate;

[0061] Etching the cover layer to form a plurality of connection holes penetrating the cover layer along the third direction, wherein orthographic projections of different connection holes on the substrate at least partially overlap with orthographic projections of different lead-out ends on the substrate;

[0062] A conductive material is deposited in the connection hole to form a connection line.

[0063] In the semiconductor common block structure disclosed in the present invention, the first storage unit and the second storage unit in each semiconductor common unit structure can be distributed laterally on the substrate surface along a direction parallel to the substrate. During the manufacturing process, the first storage unit and the second storage unit can be formed at the same time. In this process, there is no need to wait for the first storage unit process to be completed before forming the second storage unit. The manufacturing process flow is short and the manufacturing cost is low. Since the first storage unit and the second storage unit share the same source and drain unit layer, the signal path and conditions received by the two are consistent, which helps to reduce the reading error and data inconsistency caused by the difference in signal transmission; it can also reduce the area of ​​the area where the first storage unit and the second storage unit are located, improve the device integration, and thus improve the storage density of the memory. Multiple semiconductor common unit structures are arranged at intervals along the second direction and the third direction, which can maximize the use of the substrate area and further increase the storage density. In addition, all the second transistors are accommodated in the shielding inner cavity of the shielding cover structure, and the shielding cover structure can effectively isolate the interference of the external electric field (for example, the electric field generated by the first transistor) generated by each conductive structure located outside the shielding cover structure and adjacent to the second transistor on each second transistor, reduce the influence of the external electric field on the storage area, and enhance the stability and reliability of the memory.

[0064] The semiconductor memory disclosed in the present invention is a dual-transistor capacitor-free dynamic random access memory. The two transistors in the storage unit are located above the substrate and are arranged horizontally. The channel is parallel to the substrate direction. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitor-free dynamic random access memory that increases the storage density by vertical stacking, the height of each layer in the semiconductor memory disclosed in the present invention is greatly reduced, and the storage density is higher.

[0065] Compared to the existing vertical structure dual-transistor capacitor-free dynamic random access memory preparation method that requires preparing storage functional layers layer by layer to achieve vertical stacking and increase storage density, all storage units in the preparation method of the semiconductor memory disclosed in the present invention can be prepared at the same time. Therefore, the preparation method of the semiconductor memory disclosed in the present invention has a shorter process flow and lower manufacturing cost. In addition, during the process, a shielding cover structure that can accommodate all second transistors can be prepared through a one-time process. The shielding cover structure can effectively isolate the external electric field (for example, the electric field generated by the first transistor) generated by each conductive structure located outside the shielding cover structure and adjacent to the second transistor from interfering with each second transistor, thereby reducing the impact of the external electric field on the storage area and enhancing the stability and reliability of the memory.

[0066] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0068] Figure 1 Schematic diagram of a semiconductor common block structure in an embodiment of the present disclosure.

[0069] Figure 2 Schematic diagram of a semiconductor shared unit structure in an embodiment of the present disclosure.

[0070] Figure 3 For along Figure 1 Cross-sectional view taken along the AA direction.

[0071] Figure 4 Schematic diagram of a semiconductor memory in an embodiment of the present disclosure.

[0072] Figure 5 The flowchart of the method for preparing the semiconductor memory in the embodiment of the present disclosure is shown.

[0073] Figure 6 Schematic diagram of the stacked structure in an embodiment of the present disclosure.

[0074] Figure 7 It is a schematic diagram of the structure after completing step S2 in the embodiment of the present disclosure.

[0075] Figure 8 It is a schematic diagram of the structure after completing step S3 in the embodiment of the present disclosure.

[0076] Fig. 9 It is a schematic diagram of the structure after completing step S4 in the embodiment of the present disclosure.

[0077] Fig.10 Schematic diagram of the second mask layer and the second photoresist layer in an embodiment of the present disclosure.

[0078] Fig.11 FIG. 4 is a schematic diagram of a word line accommodating groove in an embodiment of the present disclosure.

[0079] Fig.12 For along Fig.11 Cross-sectional view taken along the AA direction.

[0080] Fig.13 for Fig.12 The structure in FIG. 1 is a schematic diagram of the structure after completing step S6.

[0081] Fig.14 for Fig.13The structure in FIG. 1 is a schematic diagram of the structure after completing step S7.

[0082] Fig.15 FIG. 4 is a schematic diagram of an insulating material filled in a first opening in an embodiment of the present disclosure.

[0083] Fig.16 Schematic diagram of the second opening in the embodiment of the present disclosure.

[0084] Fig.17 It is a cross-sectional view after completing step S9 in the embodiment of the present disclosure.

[0085] Fig.18 It is a cross-sectional view after completing step S10 in the embodiment of the present disclosure.

[0086] Fig.19 It is a cross-sectional view after completing step S310 in the embodiment of the present disclosure.

[0087] Fig. 20 Schematic diagram of the source-drain unit layer in the embodiment of the present disclosure.

[0088] Fig.21 Schematic diagram of the third opening in the embodiment of the present disclosure.

[0089] Fig. 22 Schematic diagram of a fourth mask layer and a fourth photoresist layer in an embodiment of the present disclosure.

[0090] Fig.23 FIG. 4 is a schematic diagram of a first bit line accommodating hole and a second bit line accommodating hole in an embodiment of the present disclosure.

[0091] Fig.24 For along Fig.23 Cross-sectional view taken along the dashed line.

[0092] Fig.25 Schematic diagram of a first bit line and a second bit line in an embodiment of the present disclosure.

[0093] Fig.26 Schematic diagram of etching the blocking layer and the mask material layer in the embodiment of the present disclosure.

[0094] Fig. 27 Schematic diagram of the first graphic mask layer in an embodiment of the present disclosure.

[0095] Fig.28 Schematic diagram of the n-1th graphical stacking structure in an embodiment of the present disclosure.

[0096] Fig.29 Schematic diagram of the covering layer and the connecting holes in the embodiment of the present disclosure.

[0097] Fig.30 It is a partial cross-sectional view of a plurality of word lines in a step shape in an embodiment of the present disclosure.

[0098] Description of reference numerals:

[0099] 1. substrate; 2. first storage unit; 3. second storage unit; 4. source-drain layer; 410. source-drain unit layer; 10. first transistor; 101. first gate; 1011. first gate material layer; 102. first gate dielectric layer; 103. first semiconductor layer; 20. second transistor; 201. second gate; 202. second gate dielectric layer; 203. second semiconductor layer; 5. word line; 510. word line material layer; 51. conductive barrier material layer; 52. metal material layer; 501. main extension portion; 502. lead-out end portion; 6. first bit line; 601. first bit line accommodating hole; 7. second bit line; 701. second bit line accommodating hole; 8. insulating material; 81. third opening; 9. protective layer; 30. stacked structure; 301. first insulating material layer; 302. semiconductor material layer; 303. second insulating Material layer; 304, etching stop layer; 40, patterned stacked structure; 401, first pattern; 402, second pattern; 4021, sub-pattern; 403, first opening; 404, first transistor accommodating groove; 405, word line accommodating groove; 406, second opening; 50, development pattern; 60, second photoresist layer; 6001, first development area; 70, shielding cover structure; 710, shielding inner cavity; 80, connecting line; 801, connecting hole; 90, filling layer; 100, first mask layer; 200, second mask layer; 300, covering layer; 400, fourth mask layer; 500, fourth photoresist layer; 5001, third development area; 600, stacking structure; 700, first graphic mask layer; 800, etching stop layer; 900, mask material layer; x, first direction; y, second direction; z, third direction. DETAILED DESCRIPTION

[0100] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0101] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0102] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", "third" and "fourth" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0103] With the rapid development of the semiconductor industry, the storage density requirements for memory are increasing. However, the traditional 1T1C (i.e., one transistor and one capacitor) structure faces severe challenges in improving storage density. The reduction of its key dimensions is limited by the lithography capability limit of the lithography machine, and it is difficult to continue to shrink. At the same time, it is difficult to achieve three-dimensional stacking in the 1T1C structure, and the improvement of storage density is therefore severely restricted by the key dimensions. In order to break through this bottleneck, those skilled in the art will turn their research focus to the 2T0C (i.e., two transistors, no capacitor) structure. In the existing vertically structured 2T0C DRAM memory, the transistor channel in the storage unit is perpendicular to the substrate, and a significant improvement in storage density is achieved by stacking the storage function layers in sequence. However, the structural process flow of the sequentially stacked storage function layers is long, the manufacturing cost is high, and the device reliability is low.

[0104] Based on this, an embodiment of the present disclosure provides a semiconductor common block structure, which is prepared on a substrate. Figure 1 A schematic diagram of a semiconductor common block structure disclosed in the present invention is shown, Figure 1 As shown, the semiconductor common block structure includes a plurality of semiconductor common unit structures, a source-drain layer 4 and a shielding cover structure 70 located on a substrate 1. Figure 2 As shown, the semiconductor shared unit structure includes: a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 are arranged side by side in a mirror image along a first direction x, the first storage unit 2 and the second storage unit 3 share the same source-drain unit layer 410, and the first direction x is parallel to the surface of the substrate 1;

[0105] The first storage unit 2 and the second storage unit 3 both include: a first transistor 10, which is located above the top surface of the substrate 1, and the first transistor 10 includes: a first gate 101, a first gate dielectric layer 102 and a first semiconductor layer 103, the first gate 101 extends along a first direction x, the first gate dielectric layer 102 conformally covers the sidewall and one end of the first gate 101, the first semiconductor layer 103 covers the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 includes a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction x; a second transistor 20, which is distributed side by side with the first transistor 10 along the first direction x, and the second transistor 20 includes a second gate 201, a second gate dielectric layer 2 02 and a second semiconductor layer 203, the second gate 201 extends along the first direction x, the second gate dielectric layer 202 conformally covers the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction x; the second source and drain region is conductively connected to the second gate 201 (for example, the second source and drain region is conductively connected to the second gate 201 through the semiconductor material layer 302), and the fourth source and drain region in the first storage unit 2 and the fourth source and drain region in the second storage unit 3 are respectively connected to the two opposite sides of the source and drain unit layer 410;

[0106] The plurality of semiconductor common unit structures are arranged at intervals along a second direction y and a third direction z, wherein the second direction y is parallel to the substrate 1 and intersects with the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y;

[0107] A source-drain layer 4 is formed by connecting all source-drain unit layers 410 in the same plane end to end in sequence;

[0108] The shielding cover structure 70 has a shielding inner cavity, in which all the second transistors 20 are accommodated, and all the first transistors 10 are located outside the shielding cover structure 70 .

[0109] In the semiconductor shared block structure disclosed in the present invention, the first storage unit 2 and the second storage unit 3 in each semiconductor shared unit structure can be distributed laterally on the surface of the substrate 1 along a direction parallel to the substrate 1. During the manufacturing process, the first storage unit 2 and the second storage unit 3 can be formed at the same time. In this process, there is no need to wait for the first storage unit 2 to be completed before forming the second storage unit 3. The manufacturing process is short and the manufacturing cost is low. Since the first storage unit 2 and the second storage unit 3 share the same source and drain unit layer 410, the signal paths and conditions received by the two are consistent, which helps to reduce the reading errors and data inconsistencies caused by differences in signal transmission; it can also reduce the area of ​​the first storage unit 2 and the second storage unit 3, improve the device integration, and thus improve the storage density of the memory. Multiple semiconductor shared unit structures are arranged at intervals along the second direction y and the third direction z, which can maximize the utilization of the substrate 1 area and further increase the storage density. In addition, by accommodating all the second transistors 20 in the shielding inner cavity of the shielding cover structure 70, the shielding cover structure 70 can effectively isolate the external electric field generated by the conductive structures located outside the shielding cover structure 70 and adjacent to the second transistor 20 (for example, the electric field generated by the first transistor 10) from interfering with the second transistors 20, thereby reducing the impact of the external electric field on the storage area and enhancing the stability and reliability of the memory.

[0110] The following is a detailed description of the various parts and specific details of the semiconductor common block structure disclosed in the present invention:

[0111] Please continue to see Figure 1 As shown, the semiconductor block structure may include a plurality of semiconductor common unit structures located on a substrate 1, wherein: the substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. The substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not particularly limited herein.

[0112] Please continue to see Figure 2 As shown, the semiconductor shared unit structure may include a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 may be formed on a substrate 1, the first storage unit 2 and the second storage unit 3 may both be 2T0C (i.e., including two transistors and no capacitor) structures, the first storage unit 2 and the second storage unit 3 may be distributed side by side in a mirror image along a first direction x, and the first storage unit 2 and the second storage unit 3 may share the same source-drain unit layer 410, which may reduce the area of ​​the region where the first storage unit 2 and the second storage unit 3 are located, improve the device integration, and thus improve the storage density of the memory. In an exemplary embodiment of the present disclosure, the first direction x may be parallel to the surface of the substrate 1.

[0113] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, the first storage unit 2 and the second storage unit 3 both include a first transistor 10 and a second transistor 20, wherein:

[0114] The first transistor 10 is located above the top surface of the substrate 1. The first transistor 10 may be a CAA (Channel-All-Around) structure transistor and the channel is parallel to the plane where the substrate 1 is located and may extend along the first direction x. The first transistor 10 may include: a first gate 101, a first gate dielectric layer 102 and a first semiconductor layer 103; the first gate 101 may be in the shape of a strip and may extend along the first direction x; the material of the first gate 101 may be a conductive material, for example, the material of the first gate 101 may be indium zinc oxide (IZO) or polysilicon. The first gate dielectric layer 102 may conformally cover the sidewall and one end of the first gate 101, and the material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, and of course, it may also be other materials, which are not listed here one by one. The first semiconductor layer 103 may conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 may include a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction x, wherein the first source and drain region is located on a side of the first channel region away from the source and drain unit layer 410, and the second source and drain region is located on a side of the first channel region close to the source and drain unit layer 410. The material of the first semiconductor layer 103 and the material of the first gate 101 may be matched with each other; for example, when the material of the first gate 101 is indium zinc oxide (IZO), the material of the first semiconductor layer 103 may be indium gallium zinc oxide (IGZO); when the material of the first gate 101 is polycrystalline silicon, the material of the first semiconductor layer 103 may be single crystal silicon.

[0115] Optionally, the material of the first semiconductor layer 103 of the present invention is indium gallium zinc oxide (IGZO). Compared with the traditional method of using single crystal silicon as the material of the first semiconductor layer 103, the present invention uses indium gallium zinc oxide (IGZO) as the material of the first semiconductor layer 103. This is because the off-state current of the IGZO thin film transistor (Thin Film Transistor-TFT) is extremely small, and its use in 2T0C DRAM storage cells can significantly reduce the leakage rate, help reduce device power consumption, and improve device reliability.

[0116] The second transistor 20 may also be located above the top surface of the substrate 1. The second transistor 20 may be a CAA structure transistor and the channel is parallel to the plane where the substrate 1 is located, and may extend along the first direction x. The second transistor 20 may be arranged side by side with the first transistor 10 along the first direction x, that is, the second transistor 20 and the first transistor 10 are laterally arranged on the surface of the substrate 1. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be in a strip shape and may extend along the first direction x. For example, the second gate 201 and the first gate 101 may be arranged in sequence along the first direction x. The material of the second gate 201 may be a conductive material, for example, it may be indium zinc oxide (IZO) or polysilicon. In some embodiments of the present disclosure, the material of the second gate 201 is the same as that of the first gate 101. For example, the materials of the second gate 201 and the first gate 101 may both be indium zinc oxide (IZO). The second gate dielectric layer 202 can conformally cover the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The material of the second gate dielectric layer 202 can be a material with a high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, and of course, it can also be other materials, which are not listed here. It should be noted that the material of the second gate dielectric layer 202 can be the same as that of the first gate dielectric layer 102. The second semiconductor layer 203 may conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source and drain region, a second channel region, and a fourth source and drain region sequentially distributed along the first direction x, wherein the third source and drain region is located on a side of the second channel region away from the source and drain unit layer 410, and the fourth source and drain region is located on a side of the second channel region close to the source and drain unit layer 410; the material of the second semiconductor layer 203 and the material of the second gate 201 may cooperate with each other; for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 may be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polycrystalline silicon, the material of the second semiconductor layer 203 may be single crystal silicon. In some embodiments of the present disclosure, the material of the second semiconductor layer 203 may be the same as that of the first semiconductor layer 103, for example, the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 may both be indium gallium zinc oxide (IGZO).

[0117] In an exemplary embodiment of the present disclosure, the first transistor 10 may be a write transistor, and the second transistor 20 may be a read transistor. The second source and drain region of the first transistor 10 may be conductively connected to the second gate 201 of the second transistor 20 through a semiconductor material layer 302 (for example, indium zinc oxide). The charge in the gate capacitance of the second transistor 20 (that is, the read transistor) may be changed by the first transistor 10 (that is, the write transistor), thereby affecting the resistance state between the source and drain of the second transistor 20 (that is, the read transistor), thereby achieving the distinction between "0" and "1".

[0118] In an exemplary embodiment of the present disclosure, the source-drain unit layer 410 may extend in a direction perpendicular to the substrate 1, that is, the plane where the source-drain unit layer 410 is located is perpendicular to the first direction x, and the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 distributed along the first direction x. Such a design can ensure that the signal paths and conditions received by the first storage unit 2 and the second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistencies caused by differences in signal transmission.

[0119] In some embodiments of the present disclosure, a plurality of semiconductor common unit structures may be arranged along the second direction y and the third direction z. For example, a plurality of semiconductor common unit structures may form a plurality of common unit structure groups arranged along the third direction z, and each common unit structure group may include a plurality of semiconductor common unit structures arranged along the second direction y. All source-drain unit layers 410 located in the same plane in different common unit structure groups are sequentially connected end to end to form a source-drain layer 4.

[0120] The second direction y is parallel to the substrate 1 and intersects with the first direction x. For example, the second direction y may be perpendicular to the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y. It should be noted that parallel can be absolutely parallel or approximately parallel; similarly, perpendicular can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable in the manufacturing process. In the present disclosure, the angle deviation may be caused by the limitation of the manufacturing process, so that the angle between the first direction x (or the second direction y) and the surface of the substrate 1 has a certain deviation, or the angle between the third direction z and the first direction x (or the second direction y) shows a certain deviation. As long as the angle deviation is within the preset range, the first direction x (or the second direction y) can be considered to be parallel to the substrate 1; or, the third direction z can be considered to be perpendicular to the first direction x (or the second direction y). For example, the preset range may be 10°, that is, when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is less than or equal to 10°, the first direction x (or the second direction y) may be considered to be parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is greater than or equal to 80° and less than or equal to 100°, the third direction z may be considered to be perpendicular to the first direction x (or the second direction y).

[0121] like Figure 3 As shown, the shielding cover structure 70 may have a shielding inner cavity 710, in which all the second transistors 20 in the semiconductor common block structure are accommodated, and all the first transistors 10 are located outside the shielding cover structure 70. Since the second transistors 20 are mainly used to store charges, that is, each second transistor 20 constitutes a charge storage area; all the second transistors 20 are enclosed in the shielding cover structure 70, that is: the storage area can be isolated from the outside by the shielding cover structure 70, which can reduce the influence of the peripheral electric field (for example, the electric field generated by the first transistor 10) generated by each conductive structure located outside the shielding cover structure 70 and adjacent to the second transistor 20 on the storage area, thereby improving the stability and reliability of the device.

[0122] In an exemplary embodiment of the present disclosure, the shielding cover structure 70 may be a shell structure, which may include at least one conductive material shell layer. For example, the material of the conductive material shell layer may be indium gallium zinc oxide (IGZO). During the use of the device, the conductive material shell layer can quickly redistribute the charges in the external electric field inside it due to its conductivity, thereby dispersing and limiting the penetration of the electric field, thereby shielding the external electric field.

[0123] In other embodiments of the present disclosure, the shielding cover structure 70 may also include a dielectric layer, which may be located on the surface of the conductive material shell layer, for example, the dielectric layer may conformally cover the surface of the conductive material shell layer. The material of the dielectric layer may be a material with a relatively high dielectric constant, and the dielectric layer with a high dielectric constant can induce a relatively strong reverse electric field under the action of the electric field, thereby effectively offsetting or weakening the penetration of the external electric field. For example, the material of the dielectric layer may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. In the shielding cover structure 70 formed by the combination of the dielectric layer and the conductive material shell layer, when the external electric field acts on the shielding cover structure 70, the dielectric layer with a high dielectric constant will induce an internal electric field in the opposite direction of the external electric field to offset the external electric field, thereby weakening the influence of the external electric field on the internal area. At the same time, the high conductivity of the conductive material shell layer enables the charge to be quickly redistributed inside it, further dispersing and limiting the penetration of the electric field, so that the electric field strength inside the shielding cover structure 70 is significantly reduced.

[0124] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1 As shown, the semiconductor common block structure may further include a plurality of word lines 5, a plurality of first bit lines 6 and a plurality of second bit lines 7, wherein:

[0125] A plurality of word lines 5 may extend along the second direction y and be arranged at intervals along the first direction x and the third direction z, and each word line 5 is connected to the gates of a row of first transistors 10 arranged along the second direction y in the same plane. For example, each common cell structure group may include two word lines 5, and the two word lines 5 may be arranged at intervals along the first direction x, wherein one word line 5 may be contacted and connected to all ends of a row of first gate electrodes 101 arranged along the second direction y in all first storage cells 2 in the same common cell structure group that are not covered by the first gate dielectric layer 102; and another word line 5 may be contacted and connected to all ends of a row of first gate electrodes 101 arranged along the second direction y in all second storage cells 3 in the same common cell structure group that are not covered by the first gate dielectric layer 102. The word lines 5 connected to the first storage cells 2 in the plurality of common cell structure groups arranged along the third direction z may be spaced and distributed along the third direction z.

[0126] The material of the word line 5 can be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, titanium nitride or polysilicon. Of course, the material of the word line 5 can also be other materials with good conductive properties, which are not listed here one by one.

[0127] In some embodiments of the present disclosure, please continue to refer to Figure 1 and Figure 3As shown, the word line 5 may include a main extension portion 501 and a lead-out end portion 502 located at at least one end of the main extension portion 501; in the third direction z, the orthographic projections of the lead-out ends 502 of any two word lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extension portions 501 of any two word lines 5 on the substrate 1 overlap; in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each word line 5 decreases or increases in sequence. That is, at least one end of the multiple word lines 5 arranged along the third direction z is in a step shape; at this time, the lead-out end portions 502 of each word line 5 are exposed.

[0128] In an exemplary embodiment of the present disclosure, each word line 5 includes two lead-out ends 502 located at both ends of the main extension portion 501 in the second direction y, and each lead-out end 502 has the same size in the second direction y. For example, the two lead-out ends 502 in the same word line 5 have the same size in the second direction y, and the lead-out ends 502 in different word lines 5 also have the same size in the second direction y.

[0129] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1 and Figure 3 As shown, the semiconductor common block structure further includes a connection line 80, and the connection line 80 is connected to the lead-out end 502 of the word line 5, that is, each lead-out end 502 is correspondingly provided with a connection line 80. The material of the connection line 80 can be a conductive material, for example, its material can be a titanium nitride or a combined film layer structure of titanium nitride and tungsten, and the signal can be transmitted to the lead-out end 502 of the word line 5 through the connection line 80, and then transmitted to the inside of the word line 5. For example, the connection line 80 can extend along the third direction z, and two adjacent connection lines 80 are insulated. When the word line 5 includes two lead-out ends 502, the two lead-out ends 502 are provided with a connection line 80.

[0130] In an exemplary embodiment of the present disclosure, the word line 5 can be electrically led out at the same time through two connecting wires 80. During the signal transmission process, the two connecting wires 80 can make the signal more evenly distributed, which helps to reduce the reflection and attenuation of the signal during the transmission process, thereby improving the integrity and stability of the signal transmission. At the same time, the design of providing connecting wires 80 at both ends can balance the electromagnetic field distribution around the word line 5 to a certain extent, reduce the impact of external electromagnetic interference on signal transmission, and improve the anti-interference ability of the circuit.

[0131] In an exemplary embodiment of the present disclosure, when the length of each word line 5 decreases in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the connection line 80 is connected to the side of the lead-out end 502 away from the substrate 1, so as to lead each word line 5 upward from the front. Alternatively, when the length of each word line 5 increases in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the connection line 80 is connected to the side of the lead-out end 502 close to the substrate 1, so as to lead each word line 5 upward and downward from the back. Different connection lines 80 can be distributed in parallel and all extend along the third direction z.

[0132] Please continue to see Figure 1 As shown, the plurality of first bit lines 6 in the present disclosure may extend along the third direction z and be arranged at intervals along the first direction x and the second direction y, and each first bit line 6 is coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane. For example, the semiconductor common block structure of the present disclosure may include a plurality of bit line groups arranged at intervals along the second direction y, and each bit line group may include two first bit lines 6, and the two first bit lines 6 may be arranged at intervals along the first direction x, wherein one first bit line 6 may be coated on the periphery of a row of first source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of common unit structure groups arranged along the third direction z; the other first bit line 6 may be coated on the periphery of a row of first source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of common unit structure groups arranged along the third direction z. It should be noted that different semiconductor common unit structures arranged along the second direction y are respectively provided with a corresponding bit line group, and each first bit line 6 in different bit line groups may be arranged at intervals along the second direction y and distributed in parallel.

[0133] Please continue to see Figure 1 As shown, the plurality of second bit lines 7 in the present disclosure may extend along the third direction z and be arranged at intervals along the first direction x and the second direction y, and each second bit line 7 is coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane. For example, each bit line group may include two second bit lines 7, and the two second bit lines 7 may be distributed at intervals along the first direction x, wherein one second bit line 7 may be coated on the periphery of a row of third source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of shared unit structure groups arranged along the third direction z; and the other second bit line 7 may be coated on the periphery of a row of third source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of shared unit structure groups arranged along the third direction z. It should be noted that each second bit line 7 in different bit line groups may be arranged at intervals along the second direction y and distributed in parallel.

[0134] In an exemplary embodiment of the present disclosure, the materials of the first bit line 6 and the second bit line 7 are both conductive materials, and the conductive materials can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. For example, the first bit line 6 and the second bit line 7 can both include a conductive barrier layer and a metal layer; taking the first bit line 6 as an example, the metal layer can be in a strip shape and extend along the third direction z, and the metal layer can be coated on the periphery of each first source and drain region in a plurality of common unit structure groups arranged along the third direction z, and the conductive barrier layer can at least conformally cover the surface of the metal layer, and the conductive barrier layer can prevent metal ions in the metal layer from diffusing into other surrounding structures, which helps to reduce the risk of short circuit or coupling and improve device reliability. In some embodiments of the present disclosure, the material of the conductive barrier layer can be titanium nitride, and the material of the metal layer can be tungsten, and titanium nitride can prevent tungsten ions from diffusing into other surrounding structures.

[0135] The following is an explanation of the reading and writing process of the semiconductor common block structure disclosed in the present invention:

[0136] In the process of writing "1", a positive voltage (greater than the threshold voltage Vth) is added to the write word line WWL to turn on the first transistor 10 (i.e., the write transistor), and a positive voltage is added to the write bit line WBL to inject charge into the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor); after the charge injection, the positive voltage applied to the write word line WWL and the positive voltage applied to the write bit line WBL are removed to save the "1" state. In the process of reading "1", a read voltage is added to the drain of the second transistor 20 (i.e., the read transistor). Since there is a certain charge stored in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a relatively low resistance state, and a relatively large current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "1". In the process of writing "0", a positive voltage (greater than the threshold voltage Vth) is added to the write word line WWL to turn on the first transistor 10 (i.e., the write transistor), and a negative voltage is added to the write bit line WBL to extract charge from the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor); after the charge is extracted, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed to save the "0" state. In the process of reading "0", a read voltage is added to the drain of the second transistor 20 (i.e., the read transistor). Since there is no charge in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a higher resistance state, and a smaller current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "0".

[0137] The present disclosure also provides a semiconductor memory device, such as Figure 4As shown, the semiconductor memory includes a substrate 1 and a plurality of semiconductor common block structures as in any of the above embodiments located on the substrate 1, wherein the plurality of semiconductor common block structures are arranged along a first direction x; and two adjacent semiconductor common block structures are independently arranged. For example, adjacent semiconductor common block structures in the semiconductor memory are spaced apart. Other details and beneficial effects of the semiconductor memory disclosed in the present invention have been described in detail in the embodiments of the corresponding semiconductor common block structures, and therefore, will not be repeated here.

[0138] A semiconductor common block structure is defined to include two semiconductor storage block structures distributed in a mirror-symmetrical manner along a source-drain layer 4: a first semiconductor storage block structure and a second semiconductor storage block structure, wherein the first semiconductor storage block structure and the second semiconductor storage block structure share a source-drain layer 4.

[0139] The specific principles of reading and writing the semiconductor memory provided by the present disclosure are as follows:

[0140] When writing: selecting a word line 5 and a first bit line 6 can select a storage unit (including a first transistor 10 (i.e., a write transistor) and a second transistor 20 (i.e., a read transistor)), and by applying voltages to the selected word line 5 and the selected first bit line 6 respectively to turn on the first transistor 10 (i.e., the write transistor), charges can be injected into or extracted from the gate capacitance of the second transistor 20 (i.e., the read transistor), thereby realizing a write operation.

[0141] When reading: when a storage unit (including a first transistor 10 (i.e., a write transistor) and a second transistor 20 (i.e., a read transistor)) is selected for reading, all the first transistors 10 in the semiconductor storage block structure where the selected storage unit is located (except the first transistor 10 corresponding to the selected storage unit) are turned on, and charges are extracted from the gate capacitances of all the second transistors 20 (i.e., read transistors) except the selected storage unit, and then all the first transistors 10 (i.e., write transistors) are turned off; a read voltage is applied to a second bit line 7 and a source-drain layer 4 corresponding to the selected storage unit to implement the read operation of the selected storage unit.

[0142] It should be understood that after each read operation, a refresh operation needs to be performed on the semiconductor memory block structure where the selected memory cell is located to restore the storage data of the semiconductor memory block structure before the read operation.

[0143] The semiconductor memory disclosed in the present invention is a dual-transistor capacitor-free dynamic random access memory. The two transistors in the storage unit are located above the substrate 1 and are arranged horizontally. The channel is parallel to the direction of the substrate 1. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitor-free dynamic random access memory that increases the storage density by vertical stacking, the height of each layer in the semiconductor memory disclosed in the present invention is greatly reduced, and the storage density is higher.

[0144] The present disclosure also provides a method for preparing a semiconductor memory. Figure 5 As shown, the preparation method may include steps S110 to S140, wherein:

[0145] Step S110, providing a substrate 1;

[0146] Step S120, forming a first memory cell 2 and a second memory cell 3 on a substrate 1, wherein the first memory cell 2 and the second memory cell 3 are arranged side by side in a mirror image along a first direction x, and the first direction x is parallel to the surface of the substrate 1; the first memory cell 2 and the second memory cell 3 both include a first transistor 10 and a second transistor 20 arranged side by side along the first direction x, and a source and drain region of the first transistor 10 is electrically connected to a gate of the second transistor 20;

[0147] Step S130, forming a shielding cover structure 70 to accommodate the second transistor 20 of the first storage unit 2 and the second transistor 20 of the second storage unit 3 in the shielding inner cavity 710;

[0148] Step S140 , forming a source-drain unit layer 410 between the first memory cell 2 and the second memory cell 3 ; a source-drain region of the second transistor 20 of the first memory cell 2 and a source-drain region of the second transistor 20 of the second memory cell 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 .

[0149] Compared with the preparation method of the existing vertical structure dual-transistor capacitor-free dynamic random access memory that needs to prepare the storage functional layer layer by layer to achieve vertical stacking and increase the storage density, the preparation method of the semiconductor memory disclosed in the present invention can prepare all the storage units at the same time. Therefore, the preparation method of the semiconductor memory disclosed in the present invention has a shorter process flow and lower manufacturing cost. In addition, during the process, a shielding cover structure 70 capable of accommodating all the second transistors 20 can be prepared by a single process. The shielding cover structure 70 can effectively isolate the interference of the external electric field (for example, the electric field generated by the first transistor 10) generated by each conductive structure located outside the shielding cover structure 70 and adjacent to the second transistor 20 to each second transistor 20, thereby reducing the influence of the external electric field on the storage area and enhancing the stability and reliability of the memory.

[0150] The following is a detailed description of the steps and specific details of the method for preparing a semiconductor memory disclosed in the present invention:

[0151] In step S110 , a substrate 1 is provided.

[0152] The substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. The substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not particularly limited here.

[0153] In step S120, a first memory cell 2 and a second memory cell 3 are formed on a substrate 1, and the first memory cell 2 and the second memory cell 3 are arranged side by side in a mirror-image manner along a first direction x, and the first direction x is parallel to the surface of the substrate 1; the first memory cell 2 and the second memory cell 3 both include a first transistor 10 and a second transistor 20 arranged side by side along the first direction x, and a source and drain region of the first transistor 10 is electrically connected to the gate of the second transistor 20.

[0154] Please continue to see Figure 2 As shown, both the first storage unit 2 and the second storage unit 3 can be 2T0C (i.e., including two transistors and no capacitor) structures, and both the first storage unit 2 and the second storage unit 3 include a first transistor 10 and a second transistor 20, and both the first transistor 10 and the second transistor 20 can be CAA (Channel-All-Around) structure transistors, and the channels are parallel to the plane where the substrate 1 is located, and can extend along the first direction x. The first transistor 10 may include: a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103, the first gate 101 may be in a strip shape, and may extend along the first direction x; the first gate dielectric layer 102 may conformally cover the sidewall and one end of the first gate 101. The first semiconductor layer 103 may conformally cover the surface of the first gate dielectric layer 102. The second transistor 20 and the first transistor 10 are laterally distributed on the surface of the substrate 1. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be in a strip shape and may extend along the first direction x. For example, the second gate 201 and the first gate 101 may be sequentially distributed along the first direction x. The second gate dielectric layer 202 may conformally cover the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The second semiconductor layer 203 may conformally cover the surface of the second gate dielectric layer 202.

[0155] In step S130 , a shielding cover structure 70 is formed to accommodate the second transistor 20 of the first memory cell 2 and the second transistor 20 of the second memory cell 3 in the shielding inner cavity 710 .

[0156] Please continue to see Figure 3 As shown, the shielding cover structure 70 may have a shielding inner cavity 710, in which all the second transistors 20 in the semiconductor common block structure are accommodated, and all the first transistors 10 are located outside the shielding cover structure 70. Since the second transistors 20 are mainly used to store charges, that is, each second transistor 20 constitutes a charge storage area; all the second transistors 20 are enclosed in the shielding cover structure 70, that is: the storage area can be isolated from the outside world by the shielding cover structure 70, which can reduce the influence of the external electric field on the storage area and improve the stability and reliability of the device.

[0157] In an exemplary embodiment of the present disclosure, the shielding cover structure 70 may be a shell structure, which may include at least one conductive material shell layer. For example, the material of the conductive material shell layer may be indium gallium zinc oxide (IGZO). During the use of the device, the conductive material shell layer can quickly redistribute the charges in the external electric field inside it due to its conductivity, thereby dispersing and limiting the penetration of the electric field, thereby shielding the external electric field.

[0158] In other embodiments of the present disclosure, the shielding cover structure 70 may also include a dielectric layer, which may be located on the surface of the conductive material shell layer, for example, the dielectric layer may conformally cover the surface of the conductive material shell layer. The material of the dielectric layer may be a material with a relatively high dielectric constant, and the dielectric layer with a high dielectric constant can induce a relatively strong reverse electric field under the action of the electric field, thereby effectively offsetting or weakening the penetration of the external electric field. For example, the material of the dielectric layer may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. In the shielding cover structure 70 formed by the combination of the dielectric layer and the conductive material shell layer, when the external electric field acts on the shielding cover structure 70, the dielectric layer with a high dielectric constant will induce an internal electric field in the opposite direction of the external electric field to offset the external electric field, thereby weakening the influence of the external electric field on the internal area. At the same time, the high conductivity of the conductive material shell layer enables the charge to be quickly redistributed inside it, further dispersing and limiting the penetration of the electric field, so that the electric field strength inside the shielding cover structure 70 is significantly reduced.

[0159] In an exemplary embodiment of the present disclosure, the method for preparing a semiconductor memory of the present disclosure may further include: forming a word line material layer before forming the second transistor 20. The word line material layer may extend along the second direction y, and the word line material layer may be connected to the gate of the first transistor 10. Forming the first transistor 10, the second transistor 20, the word line material layer and the shielding cover structure 70 on the substrate 1 may include steps S1 to S10, wherein:

[0160] Step S1 : first insulating material layers 301 and semiconductor material layers 302 are alternately deposited on a substrate 1 in sequence to form a stacked structure 30 .

[0161] like Figure 6 As shown, the stacked structure 30 may include multiple layers of first insulating material layers 301 and multiple layers of semiconductor material layers 302, and the multiple layers of first insulating material layers 301 and the multiple layers of semiconductor material layers 302 may be alternately distributed in a direction perpendicular to the substrate 1 (i.e., the third direction z). In an exemplary embodiment of the present disclosure, the material of the first insulating material layer 301 may be silicon oxide, and the material of the semiconductor material layer 302 may be indium zinc oxide (IZO). The first insulating material layer 301 and the semiconductor material layer 302 may be alternately deposited on the substrate 1 in sequence by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that the film layer in contact with the substrate 1 in the stacked structure 30 is the first insulating material layer 301, and at the same time, the film layer farthest from the substrate 1 in the stacked structure 30 is also the first insulating material layer 301.

[0162] In an exemplary embodiment of the present disclosure, after forming the stacked structure 30, a protective layer 9 may be formed on the surface of the stacked structure 30, and the protective layer 9 may prevent the first insulating material layer 301 at the top of the stacked structure 30 from being damaged during subsequent etching. The material of the protective layer 9 is different from that of the first insulating material layer 301, and the material thereof may be silicon nitride.

[0163] Step S2, patterning the stacked structure 30 to form a patterned stacked structure 40, the pattern of the patterned stacked structure 40 includes a plurality of first patterns 401 extending along the first direction x and spaced apart along the second direction y, and a plurality of second patterns 402 extending along the second direction y and spaced apart along the first direction x; the first direction x is parallel to the surface of the substrate 1, the second direction y is parallel to the substrate 1 and intersects with the first direction x; the first pattern 401 overlaps with the second pattern 402.

[0164] The stacked structure 30 may be patterned by etching. A first mask layer 100 may be formed on a side of the stacked structure 30 away from the substrate 1. For example, when a protective layer 9 is formed on the surface of the stacked structure 30, a first mask layer 100 may be formed on the surface of the protective layer 9; then a first photoresist layer may be formed on the surface of the first mask layer 100, and the first photoresist layer may be exposed and developed to form a developed pattern 50, and the developed pattern 50 corresponds to the first pattern 401 and the second pattern 402. The protective layer 9 and the stacked structure 30 may be anisotropically etched using the developed pattern 50 as a mask to form a patterned stacked structure 40. It should be noted that after the patterned stacked structure 40 is formed, the developed pattern 50 and the first mask layer 100 may be removed to expose the surface of the protective layer 9. It should be noted that for the sake of subsequent description, the protective layer 9 may be used as a part of the patterned stacked structure 40, that is, the patterned stacked structure 40 includes the protective layer 9. In the embodiment of the present disclosure, the structure after completing step S2 is as follows Figure 7 shown.

[0165] In some embodiments of the present disclosure, the first pattern 401 and the second pattern 402 are both in strip shape, and the second direction y is perpendicular to the first direction x. In this case, the second pattern 402 is distributed perpendicularly to the first pattern 401 .

[0166] Step S3 , forming a second insulating material layer 303 filling up the gaps in the patterned stacked structure 40 .

[0167] The second insulating material layer 303 is made of the same material as the first insulating material layer 301. For example, the second insulating material layer 303 and the second insulating material layer 303 can be made of silicon oxide. The second insulating material layer 303 can fill the gaps in the patterned stacked structure 40, and the surface of the second insulating material layer 303 away from the substrate 1 is flush with the surface of the patterned stacked structure 40 away from the substrate 1. For example, when the top of the patterned stacked structure 40 is the protective layer 9, the surface of the second insulating material layer 303 away from the substrate 1 is flush with the surface of the protective layer 9 away from the substrate 1. In the implementation of the present disclosure, the structure after completing step S3 is as follows: Figure 8 shown.

[0168] In some embodiments of the present disclosure, please continue to refer to Figure 8 As shown, before forming a plurality of first openings penetrating the patterned stacked structure 40 and the second insulating material layer 303 along the third direction z, that is, before executing step S4, the method for preparing a semiconductor memory device disclosed herein further includes: forming an etching stop layer 304 embedded in the second insulating material layer 303, wherein the end of the etching stop layer 304 away from the substrate 1 is flush with the top surface of the second insulating material layer 303. The material of the etching stop layer 304 can be a material having a large etching selectivity ratio with the first insulating material layer 301 and the second insulating material layer 303, and is used to control the etching amount when etching the first insulating material layer 301 and / or the second insulating material layer 303 in the subsequent step, and define the contour pattern of the shielding cover structure 70.

[0169] In an exemplary embodiment of the present disclosure, forming the second insulating material layer 303 and the etching stop layer 304 includes step S210 and step S220, wherein:

[0170] Step S210 , depositing a third insulating material layer on the exposed surfaces of the substrate 1 and the patterned stacked structure 40 , the third insulating material layer filling the gap between two adjacent first patterns 401 in the patterned stacked structure 40 , and depositing an etching stop material layer on the surface of the third insulating material layer.

[0171] The material of the third insulating material layer can be the same as that of the first insulating material layer 301. For example, the materials of the third insulating material layer and the first insulating material layer 301 can both be silicon oxide. The third insulating material layer can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. In this process, the third insulating material layer can fill the gap between two adjacent first patterns 401 in the patterned stacked structure 40, and can cover the side wall surface of the patterned stacked structure 40; then, an etching stop material layer can be formed on the surface of the structure formed by the third insulating material layer and the patterned stacked structure 40, that is, at least part of the etching stop material layer can extend along the third direction z, and can cover the surface of the third insulating material layer located on the side wall of the patterned stacked structure 40.

[0172] In step S220, the remaining gaps in the patterned stacking structure 40 are filled with insulating material 8 and planarized to form a second insulating material layer 303 and an etching stop layer 304. The second insulating material layer 303, the etching stop layer 304 and the upper surface of the patterned stacking structure 40 are flush, and the etching stop layer 304 is used to define the shape and size of the shielding cover structure 70 in the first direction x.

[0173] After the etching stop material layer is formed, the insulating material can be continuously deposited until the insulating material fills the remaining gaps in the patterned stacked structure 40, and the insulating material is the same as the material of the third insulating material layer. After the insulating material fills the remaining gaps in the patterned stacked structure 40, the structure composed of the patterned stacked structure 40, the third insulating material layer, the etching stop material layer and the insulating material can be chemically mechanically polished to make the patterned stacked structure 40, the third insulating material layer, the etching stop material layer and the insulating material flush with the surface away from the substrate 1, and the third insulating material layer and the insulating material remaining after polishing can be used together as the second insulating material layer 303, and the etching stop material layer remaining after polishing can be used as the etching stop layer 304.

[0174] Step S4, forming a plurality of first openings 403 penetrating the patterned stacked structure 40 and the second insulating material layer 303 along the third direction z, the first openings 403 being arranged one-to-one with the second patterns 402, the first openings 403 dividing the corresponding second pattern 402 into two sub-patterns 4021 mirror-distributed side by side along the first direction x; the third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the planes where the second direction y and the third direction z are located.

[0175] like Fig. 9As shown, the patterned stacked structure 40 and the second insulating material layer 303 can be etched to form a first opening 403 extending along the second direction y and penetrating the second pattern 402 along the third direction z; the number of the first openings 403 can be multiple, and the multiple first openings 403 are arranged in a one-to-one correspondence with the multiple second patterns 402, and different first openings 403 are distributed at intervals along the first direction x and are parallel to each other.

[0176] In some embodiments of the present disclosure, before forming the first opening 403, a protective material may be deposited on the surface of the structure formed by the second insulating material layer 303, the etching stop layer 304 and the patterned stacked structure 40 to form a new protective layer 9 (the new protective layer 9 is composed of the original protective layer 9 on the top of the patterned stacked structure 40 and the newly deposited protective material). The protective material is the same as the material of the original protective layer 9 on the top of the patterned stacked structure 40, for example, the protective material may be silicon nitride. Fig.10 As shown, a second mask layer 200 can be formed on the surface of the new protective layer 9, and a second photoresist layer 60 can be formed on the surface of the second mask layer 200. The second photoresist layer 60 is exposed and developed to form a plurality of first development areas 6001 extending along the second direction y and spaced apart along the first direction x. In the first direction x, each first development area 6001 is located in the middle area of ​​each second pattern 402. The second mask layer 200 and the second pattern 402 can be etched in the first development area 6001 to form a first opening 403 in the patterned stacked structure 40; the first opening 403 divides the second pattern 402 into two sub-patterns 4021 that are mirror-distributed along the first direction x.

[0177] It should be noted that after forming the first opening 403, the second photoresist layer 60 and the second mask layer 200 may be removed, thereby exposing the surface of the protective layer 9. In the embodiment of the present disclosure, the structure after completing step S4 is as follows: Fig. 9 shown.

[0178] In step S5, a portion of the semiconductor material layer 302 is etched away laterally toward both sides through the first opening 403 to form a plurality of accommodating portions, the accommodating portions comprising a row of first transistor accommodating grooves 404 extending along the first direction x and arranged along the second direction y, and a word line accommodating groove 405 extending along the second direction y and connecting the row of first transistor accommodating grooves 404.

[0179] like Fig.11 and Fig.12As shown, the semiconductor material layer 302 on both sides of the first opening 403 can be etched by an isotropic etching process to form a plurality of accommodating parts arranged along the third direction z. The word line accommodating groove 405 in the accommodating part is located in the area where the sub-pattern 4021 of the second pattern 402 is located, and the semiconductor material layer 302 in the area corresponding to the sub-pattern 4021 of the second pattern 402 can be completely etched away to form the word line accommodating groove 405; the first transistor accommodating groove 404 is located in the area where the first pattern 401 is located. When etching the semiconductor material layer 302, the semiconductor material layer 302 corresponding to the first pattern 401 is not completely etched, and the depth of the first transistor accommodating groove 404 is less than half of the length of the first pattern 401 between two adjacent first openings 403. During the etching process, the etching depth of the first transistor accommodating groove 404 can be controlled by controlling the etching time.

[0180] Step S6, depositing the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer 1011 in sequence in the accommodating portion; the first semiconductor layer 103 covers the side wall and the bottom surface of the accommodating portion, the first gate dielectric layer 102 conformally covers the surface of the first semiconductor layer 103, and the first gate material layer 1011 fills the remaining space of the accommodating portion.

[0181] The material of the first semiconductor layer 103 may be indium gallium zinc oxide (IGZO) or single crystal silicon. The material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, the material may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. The material of the first gate material layer 1011 may be indium zinc oxide (IZO) or polycrystalline silicon. It should be noted that the material of the first gate material layer 1011 matches the material of the first semiconductor layer 103; for example, when the material of the first semiconductor layer 103 is indium gallium zinc oxide (IGZO), the material of the first gate material layer 1011 is indium zinc oxide (IZO); when the material of the first semiconductor layer 103 is single crystal silicon, the material of the first gate material layer 1011 is polycrystalline silicon.

[0182] In some embodiments of the present disclosure, the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer 1011 can be sequentially deposited on the side of the protective layer 9 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, the first semiconductor layer 103 can conformally cover the inner wall of the accommodating portion. For process convenience, the first semiconductor layer 103 can also cover the surface of the protective layer 9 and the side walls of each insulating material 8 layer exposed in the first opening 403; the first gate dielectric layer 102 can conformally cover the surface of the first semiconductor layer 103, and the first gate material layer 1011 is located on the surface of the first gate dielectric layer 102 and can fill the remaining space of the accommodating portion. In this process, in order to ensure that the first gate material layer 1011 can fill the remaining space of the accommodating portion, the first gate material layer 1011 can fill the first opening 403 at the same time. Subsequently, the first gate material layer 1011 located in the first opening 403 and the first gate material layer 1011 located on the top of the protective layer 9 can be removed. In the implementation of the present disclosure, the structure after completing step S6 is as follows: Fig.13 shown.

[0183] Step S7, etching away the first gate material layer 1011 deposited in the word line accommodating groove 405 to form the first gate 101 of the first transistor 10, and then filling the word line accommodating groove 405 with word line 5 material to form a word line material layer 510, and the word line material layer 510 is in contact with the first gate 101; the first transistor 10 includes a first gate 101, a first gate dielectric layer 102 conformally covering the sidewall and one end of the first gate 101, and a first semiconductor layer 103 conformally covering the first gate dielectric layer 102, and the first semiconductor layer 103 on the first gate 101 includes a first source and drain region, a first channel region, and a second source and drain region distributed in sequence along the first direction x.

[0184] The first gate material layer 1011 can be etched back by isotropic etching to remove the first gate material layer 1011 in the word line accommodating groove 405, and the first gate material layer 1011 in the first transistor accommodating groove 404 is used as the first gate 101 of the first transistor 10, the first gate dielectric layer 102 covered on the surface of the first gate 101 is used as the first gate dielectric layer 102 of the first transistor 10, and the first semiconductor layer 103 covered on the surface of the first gate dielectric layer 102 is used as the active region of the first transistor 10, and the active region can be divided into a first source and drain region, a first channel region, and a second source and drain region distributed in sequence along the first direction x, wherein the region in the active region close to the word line accommodating groove 405 can be used as the first source and drain region. The first gate 101, the first gate dielectric layer 102, and the first semiconductor layer 103 can together constitute the first transistor 10.

[0185] After forming the first gate 101, the word line 5 material may be filled into the word line accommodating groove 405 to form a word line material layer 510. The material of the word line material layer 510 may be a conductive material, and the conductive material may be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. In the implementation of the present disclosure, the structure after completing step S7 is as follows: Fig.14 shown.

[0186] In an exemplary embodiment of the present disclosure, please continue to refer to Fig.14 As shown, the word line material layer 510 may include a conductive barrier material layer 51 and a metal material layer 52, wherein the conductive barrier material layer 51 may be located on the sidewall and bottom of the word line accommodating groove 405, that is, the conductive barrier material layer 51 may be in contact with the first gate 101 at the bottom of the word line accommodating groove 405. The metal material layer 52 may fill the remaining space in the word line accommodating groove 405. It should be noted that in the process of forming the conductive barrier material layer 51, the conductive barrier material layer 51 may be deposited on the top of the protective layer 9 and the sidewall of the first opening 403 for process convenience, and the metal material layer 52 may also fill the first opening 403; then the metal material layer 52, the conductive barrier material layer 51, the first gate dielectric layer 102 and the first semiconductor layer 103 located on the top of the protective layer 9 and in the first opening 403 may be removed; and the conductive barrier material layer 51 and the metal material layer 52 remaining in the word line accommodating groove 405 are used as the word line material layer 510.

[0187] In an exemplary embodiment of the present disclosure, Fig.15 As shown, after forming the word line material layer 510, the first opening 403 may be filled with an insulating material 8, and the insulating material 8 may be the same material as the first insulating material layer 301 and the second insulating material layer 303. For example, the insulating material 8 may be silicon oxide. The insulating material 8 may be filled in the first opening 403 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this process, for the convenience of the process, the insulating material 8 may cover the surface of the protective layer 9 at the same time. Subsequently, the insulating material 8 may be subjected to chemical mechanical polishing, so that the surface of the insulating material 8 filled this time away from the substrate 1 is flush with the surface of the protective layer 9 away from the substrate 1.

[0188] In an exemplary embodiment of the present disclosure, after the first opening 403 is filled with the insulating material 8, a protective material may be deposited on the surface of the insulating material 8 and the protective layer 9 to form a new protective layer 9. The new protective layer 9 is composed of the original protective layer 9 and the newly deposited protective material.

[0189] Step S8, forming a plurality of second openings 406 along the third direction z that penetrate the patterned stacked structure 40 and the second insulating material layer 303 filled inside the patterned stacked structure 40, the second openings 406 are located in the middle position between two adjacent first openings 403, and the second openings 406 are parallel to the plane where the second direction y and the third direction z are located.

[0190] like Fig.16 As shown, after the first opening 403 is filled with the insulating material 8, the patterned stacked structure 40 and the second insulating material layer 303 can be anisotropically etched to form a plurality of second openings 406 extending along the second direction y and penetrating the patterned stacked structure 40 along the third direction z, and a second opening 406 can be formed between every two first openings 403; and in the first direction x, the second opening 406 is located in the middle position between two adjacent first openings 403.

[0191] For example, a third mask layer may be formed on the surface of the new protective layer 9, a third photoresist layer may be formed on the surface of the third mask layer, the third photoresist layer may be etched to form a plurality of second development areas, the second development areas may be strip-shaped and may extend along the second direction y, a second development area may be formed between every two first openings 403 on the patterned stacked structure 40, and the orthographic projection of the second development area on the patterned stacked structure 40 is located in the middle of two adjacent first openings 403. The third mask layer and the patterned stacked structure 40, i.e., the second insulating material layer 303, may be anisotropically etched in the second development area to form a second opening 406 that penetrates the patterned stacked structure 40 and the second insulating material layer 303 along the third direction z. After the second opening 406 is formed, the third photoresist layer and the third mask layer may be removed.

[0192] In step S9 , a portion of the first insulating material layer 301 is etched away laterally through the second opening 406 to form the second gate 201 of the second transistor 20 , and a portion of the second insulating material layer 303 is etched away along the second direction y on both sides of the patterned stacked structure 40 to define the outline of the shielding cover structure 70 .

[0193] like Fig.17As shown, the first insulating material layer 301 can be etched away in the horizontal direction (i.e., the first direction x) to both sides through the second opening 406 by an isotropic etching process, and the second insulating material layer 303 can be etched in the second direction y to both sides. If an etching stop layer 304 embedded in the second insulating material layer 303 is previously formed, the etching is stopped when the etching stop layer 304 is isotropically etched through the second opening 406 to form the outline of the shielding cover structure 70; if the etching stop layer 304 embedded in the second insulating material layer 303 is previously not formed, the etching is isotropically etched through the second opening 406 by controlling the etching time to form the outline of the shielding cover structure 70. At this time, the side walls of the semiconductor material layer 302 located on both sides of the second opening 406 are exposed. It should be noted that when the first insulating material layer 301 is etched, the first insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the length of the exposed semiconductor material layer 302 after the etching is completed is less than half of the length of the first insulating material layer 301 between two adjacent first openings 403. The exposed portion of the semiconductor material layer 302 after etching the first insulating material layer 301 and the second insulating material layer 303 can be used as the second gate 201 of the second transistor 20 .

[0194] In step S10, a second gate dielectric layer 202 and a second semiconductor layer 203 are sequentially deposited on the exposed surface of the second gate 201 and the contour surface of the shielding cover structure 70, wherein the second gate dielectric layer 202 conformally covers the side wall of the second gate 201, the end of the second gate 201 away from the first transistor 10 and the contour surface of the shielding cover structure 70, and the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 located on the second gate 201 includes a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction x.

[0195] like Fig.18As shown, a second gate dielectric layer 202 and a second semiconductor layer 203 may be sequentially formed on the exposed surface of the second gate 201 and the contour surface of the shielding cover structure 70 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, wherein the material of the second gate dielectric layer 202 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. The second gate dielectric layer 202 located on the second gate 201 may be the gate dielectric layer of the second transistor 20, and the second gate dielectric layer 202 located on the contour surface of the shielding cover structure 70 may serve as a dielectric layer in the shielding cover structure 70. The material of the second semiconductor layer 203 may correspond to the material of the second gate 201, for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 is indium gallium zinc oxide (IGZO). The second semiconductor layer 203 located on the second gate 201 can be used as the active region of the second transistor 20, and the active region of the second transistor 20 can be divided into a third source-drain region, a second channel region, and a fourth source-drain region sequentially distributed along the first direction x, wherein the region near the word line accommodating groove 405 in the active region of the second transistor 20 can be used as the third source-drain region, and the second semiconductor layer 203 located on the contour surface of the shielding cover structure 70 can be the conductive material shell layer of the shielding cover structure 70. The second gate 201, the second gate dielectric layer 202, and the second semiconductor layer 203 can together constitute the second transistor 20.

[0196] In an exemplary embodiment of the present disclosure, the method for preparing a semiconductor memory of the present disclosure may further include:

[0197] In step S310 , after forming the second semiconductor layer 203 , a filling layer 90 is formed to fill the shielding inner cavity 710 of the shielding cover structure 70 , and the filling layer 90 closes the second opening 406 .

[0198] like Fig.19 As shown, the shielding cavity 710 can be filled with insulating material by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form a filling layer 90. The filling layer 90 can fill the shielding cavity 710 and close the second opening 406. In this process, for process convenience, the insulating material can be deposited simultaneously on the top of the patterned stacked structure 40. After the second opening 406 is filled with the insulating material, the insulating material located on the top of the patterned stacked structure 40 can be removed.

[0199] In step S140 , a source-drain unit layer 410 is formed between the first memory cell 2 and the second memory cell 3 ; a source-drain region of the second transistor 20 of the first memory cell 2 and a source-drain region of the second transistor 20 of the second memory cell 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 .

[0200] like Fig. 20 As shown, the source-drain unit layer 410 can extend in a direction perpendicular to the substrate 1, that is, the plane where the source-drain unit layer 410 is located is perpendicular to the first direction x, the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to the two opposite sides of the source-drain unit layer 410 distributed along the first direction x, and all the source-drain unit layers 410 in the same plane are sequentially connected end to end to form a source-drain layer 4. Such a design can ensure that the signal paths and conditions received by each first storage unit 2 and each second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistency caused by differences in signal transmission.

[0201] In an exemplary embodiment of the present disclosure, a source-drain unit layer 410 is formed between the first memory cell 2 and the second memory cell 3, including steps S410 and S420, wherein:

[0202] Step S410, forming a plurality of third openings 81 penetrating the filling layer 90 along the third direction z, the third openings 81 are located in the second openings 406, and the third openings 81 expose the fourth source and drain regions in the second transistor 20, and the third openings 81 are parallel to the plane where the second direction y and the third direction z are located.

[0203] like Fig.21 As shown, the filling layer 90 can be anisotropically etched along the third direction z to form a third opening 81 extending along the second direction y and penetrating the filling layer 90 along the third direction z in the area corresponding to each second opening 406, and the third opening 81 can expose the fourth source and drain regions located at the end of the second gate 201 in each second transistor 20.

[0204] Step S420 , filling the third opening 81 with a conductive material to form a source-drain unit layer 410 .

[0205] The conductive material may be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. A conductive material may be filled in the third opening 81 to form a source-drain layer 4, and the source-drain layer 4 may fill the third opening 81. The portion of the source-drain layer 4 located between the first storage unit 2 and the second storage unit 3 spaced along the first direction x in the same plane may be used as a source-drain unit layer 410, that is, in the third direction z, each source-drain unit layer 410 is connected end to end to form a source-drain layer 4. In an exemplary embodiment of the present disclosure, the source-drain unit layer 410 may include a conductive barrier layer and a conductive metal layer, and the material of the conductive barrier layer may be a conductive material having an ion blocking function, for example, it may be titanium nitride or tantalum nitride. A conductive barrier layer that conformally covers the sidewalls and bottom of the third opening 81 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. At this time, the conductive barrier layer may be in contact with and connected to both the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 exposed in the third opening 81. The material of the conductive metal layer may be a metal material with good conductivity, for example, tungsten. The metal material may be deposited in the third opening 81 with the conductive barrier layer by chemical vapor deposition, physical vapor deposition or atomic layer deposition, thereby forming a conductive metal layer. The conductive barrier layer may prevent metal ions in the conductive metal layer from diffusing into other surrounding structures, thereby helping to improve device reliability.

[0206] In an exemplary embodiment of the present disclosure, after the source-drain unit layer 410 is formed, a protective material can be deposited on the structure formed by the source-drain unit layer 410 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 is composed of the original protective layer 9 and the newly deposited protective material), and the protective material is the same as the material of the original protective layer 9.

[0207] In an exemplary embodiment of the present disclosure, the method for preparing a semiconductor memory further includes step S510 and step S520, wherein:

[0208] In step S510 , the first insulating material layer 301 and the second insulating material layer 303 are etched to form a plurality of first bit line accommodating holes 601 and second bit line accommodating holes 701 extending along the third direction z.

[0209] like Fig. 22As shown, a fourth mask layer 400 and a fourth photoresist layer 500 may be formed on the surface of the protective layer 9, and the fourth photoresist layer 500 may be etched to form a plurality of third development areas 5001 in an array, and the third development areas 5001 may be rectangular, square, circular or elliptical, etc. The fourth mask layer 400, the protective layer 9, the patterned stacked structure 40 and the second insulating material layer 303 may be anisotropically etched in the third development area 5001 to form a plurality of first bit line accommodating holes 601 spaced apart along the second direction y and extending along the third direction z and a plurality of second bit line accommodating holes 701 spaced apart along the second direction y and extending along the third direction z, the first bit line accommodating holes 601 may expose the surface of each first active area arranged along the third direction z, and the second bit line accommodating holes 701 may expose the surface of each third active area arranged along the third direction z. After forming each first bit line accommodating hole 601 and each second bit line accommodating hole 701, the fourth photoresist layer 500 and the fourth mask layer 400 may be removed. Fig.23 and Fig.24 shown.

[0210] Step S520, forming a first bit line 6 in the first bit line accommodating hole 601, and forming a second bit line 7 in the second bit line accommodating hole 701; each first bit line 6 is coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 is coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0211] like Fig.25 As shown, a first bit line 6 can be formed in each first bit line accommodating hole 601, and a second bit line 7 can be formed in each second bit line accommodating hole 701. The materials of the first bit line 6 and the second bit line 7 can be conductive materials, and the conductive materials can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The first bit line 6 can be coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 can be coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0212] In an exemplary embodiment of the present disclosure, forming the first bit line 6 and the second bit line 7 may include: forming a conductive barrier layer that conformally covers the first bit line accommodating hole 601 and the second bit line accommodating hole 701, filling the first bit line accommodating hole 601 and the second bit line accommodating hole 701 with the conductive barrier layer with metal material to form a metal layer, the material of the conductive barrier layer is titanium nitride, and the material of the metal layer is tungsten. Titanium nitride can prevent tungsten ions from diffusing into other surrounding structures, which helps to improve the reliability of the device.

[0213] In an exemplary embodiment of the present disclosure, after forming the first bit line 6 and the second bit line 7, each word line material layer 510 and the first insulating material layer 301 and the second insulating material layer 303 covering each word line 5 may be processed to form a plurality of word lines 5 extending along the second direction y and arranged at intervals along the third direction z (e.g., Figure 1 As shown in the figure, the word line 5 includes a main extension portion 501 and a lead-out end portion 502 located at at least one end of the main extension portion 501; in the word line 5 lead-out structure, the orthographic projections of the lead-out ends 502 of any two word lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extension portions 501 of any two word lines 5 on the substrate 1 do overlap; in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the lengths of the word lines 5 decrease successively.

[0214] For the convenience of subsequent description, the structure formed by the patterned stacked structure 40, the second insulating material layer 303 and the word line material layer 510 is defined as a stacked structure 600. The stacked structure 600 can be cyclically processed by a trim-etch process to convert multiple word line material layers 510 extending along the second direction y and arranged along the third direction z into multiple word lines 5 extending along the second direction y and arranged at intervals along the third direction z. In the third direction z, the ends of the multiple word lines 5 can be stepped, and in two adjacent word lines 5, in the direction from the side close to the substrate 1 to the side away from the substrate 1, the word line 5 located in the upper layer exposes the lead-out end 502 of the word line 5 located in the lower layer.

[0215] In an exemplary embodiment of the present disclosure, the number of word line material layers 510 in the stacked structure 600 is n, and the number of insulating material layers (including the first insulating material layer 301 and the second insulating material layer 303) covering the word line material layer 510 is n+1, where n>2; in the third direction z, each word line material layer 510 can be defined as the first to nth word line material layers 510 from top to bottom, and each insulating material layer can be defined as the first to n+1th insulating material layers from top to bottom; processing the stacked structure 600 using a trimming etching process to form a plurality of word lines 5 extending along the second direction y and arranged at intervals along the third direction z may include the following steps:

[0216] S10, forming a first graphic mask layer on the stacked structure, wherein the length of the first graphic mask layer in the second direction y is less than the length of the first word line material layer 510, and the orthographic projection of the first graphic mask layer on the stacked structure does not overlap with at least one end of the first word line material layer 510.

[0217] In an exemplary embodiment of the present disclosure, Fig.26 and Fig. 27As shown, before forming the first graphic mask layer 700, an etching stop layer 800 may be formed on the surface of the stacked structure, and a mask material layer 900 may be formed on the surface of the etching stop layer 800. The mask material layer 900 includes a plurality of mask patterns extending along the second direction y and spaced along the first direction x. The orthographic projection of the mask pattern on the substrate 1 completely coincides with the orthographic projection of the stacked structure on the substrate 1. The mask material layer 900 having the mask pattern may be used to etch the etching stop layer 800 (when the stacked structure further includes a protective layer 9, the protective layer 9 is etched at the same time) to form an opening exposing the first insulating material layer. Subsequently, the mask material layer 900 may be removed, and then the first graphic mask layer 700 may be formed on the surface of the etching stop layer 800. In the second direction y, the length of the first graphic mask layer 700 is less than the length of the word line material layer 510, and the orthographic projection of the first graphic mask layer 700 on the stacked structure does not overlap with at least one end of the first word line material layer 510. For example, in the second direction y, the first pattern mask layer 700 may be located in the middle area of ​​the stack structure, and the orthographic projection of the first pattern mask layer 700 on the stack structure does not overlap with both ends of the first word line material layer 510 .

[0218] S20, using the first pattern mask layer 700 as a mask to etch the first insulating material layer and the first word line material layer 510 to expose at least one end of the second insulating material layer 8 to form a first patterned stacked structure.

[0219] It should be noted that, during the anisotropic etching process, the film layer structure in the area other than the stacking structure in the semiconductor block structure can be protected by the etching stop layer 800 and the protection layer 9 to prevent damage to other structures during the etching process.

[0220] S30, forming a second graphic mask layer on the first graphic stack structure, wherein the length of the second graphic mask layer in the second direction y is less than the length of the first layer of word line material layer 510 remaining after the last etching, and the orthographic projection of the second graphic mask layer on the substrate 1 does not overlap with at least one end of the first layer of word line material layer 510 remaining after the last etching.

[0221] In some embodiments of the present disclosure, the first graphic mask layer 700 may be removed before forming the second graphic mask layer, thereby exposing the surface of the first graphic stack structure, and then forming the second graphic stack structure on the first graphic stack structure. In the second direction y, the length of the second graphic stack structure may be less than the length of the first layer word line material layer 510 in the first graphic stack structure, and the orthographic projection of the second graphic mask layer on the substrate 1 does not overlap with at least one end of the first layer word line material layer 510 of the first graphic stack structure. For example, in the second direction y, the second graphic mask layer may be located in the middle area on the first graphic stack structure, and the orthographic projection of the second graphic mask layer on the first graphic stack structure does not overlap with both ends of the first layer word line material layer 510.

[0222] In some other embodiments of the present disclosure, the first graphic mask layer 700 does not need to be removed before forming the second graphic mask layer, and the edge of the first graphic mask layer 700 in the second direction y can be etched so that the length of the first graphic mask layer 700 in the second direction y is less than the length of the first word line material layer 510 in the first graphic stacking structure, and the orthographic projection of the first graphic mask layer 700 on the substrate 1 does not overlap with at least one end of the first word line material layer 510 of the first graphic stacking structure. The first graphic mask layer 700 after edge etching can be defined as the second graphic mask layer.

[0223] S40, using the second pattern mask layer as a mask to etch the exposed second material insulating layer and the second word line material layer 510 to expose at least one end of the next insulating material layer to form a second patterned stacked structure.

[0224] During the etching of the second insulating material layer and the second word line material layer 510, the film layer structure in the semiconductor block structure except for the stacked structure can still be protected by the etching stop layer 800 and the protective layer 9 to prevent damage to other structures during the etching process.

[0225] Repeat steps S30-S40 until at least one end of the nth insulating material layer is exposed to form an n-1th graphical stacking structure; each word line material layer 510 remaining after etching is used as a word line 5, and the area of ​​each word line 5 that does not overlap with other word lines 5 is used as a lead-out end 502. After forming the n-1th graphical stacking structure, the insulating material layer located on the lead-out end 502 of each word line 5 can be removed, and then the lead-out end 502 of each word line 5 is exposed, and the part of the word line 5 that is not the lead-out end 502 can be used as the main body extension 501.

[0226] In the present disclosure, the insulating material layer and the word line material layer 510 are etched down layer by layer by repeating steps S30 and S40 until at least one end of the nth insulating material layer is exposed. Fig.28 Each repetition of steps S30 and S40 will form a new patterned stacking structure, and in each repetition of steps S30 and S40, the ends of each word line material layer 510 that has been etched before will be etched again, so that the ends of each word line material layer 510 will be synchronously retracted inwards during each etching process, and each word line material layer 510 in the n-1th patterned stacking structure can be used as a word line 5, and the ends of each word line 5 are arranged in a step shape.

[0227] In an exemplary embodiment of the present disclosure, the method for preparing a semiconductor memory may further include steps S530 to S550, wherein:

[0228] Step S530 : forming a cover layer 300 on a side of each lead-out end portion 502 away from the substrate 1 .

[0229] like Fig.29 As shown, the material of the cover layer 300 is the same as the material of the insulating material layer (e.g., the first insulating material layer 301 and the second insulating material layer 303), for example, the material of the cover layer 300 and the material of the insulating material layer are both silicon oxide. The cover layer 300 can be formed on the side of the lead-out end 502 away from the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0230] Step S540 , etching the cover layer 300 to form a plurality of connection holes 801 penetrating the cover layer 300 along the third direction z, wherein the orthographic projections of different connection holes 801 on the substrate 1 at least partially overlap with the orthographic projections of different lead-out ends 502 on the substrate 1 .

[0231] A fifth mask layer may be formed on the cover layer 300, and the fifth mask layer is etched to form a plurality of mask holes penetrating the cover layer 300 along the third direction z. Fig.29 As shown, the cover layer 300 can be etched at the mask hole by an isotropic etching process to form a plurality of connection holes 801 penetrating the cover layer 300 along the third direction z. The connection holes 801 can be distributed in a one-to-one correspondence with the lead-out ends 502. For example, each connection hole 801 can expose each lead-out end 502. The cross-sectional shape of the connection hole 801 can be circular, elliptical, rectangular, polygonal or irregular, which is not particularly limited here. It should be noted that after the connection holes 801 are formed, the fifth mask layer can be removed, thereby exposing the etching stop layer 800 or the protective layer 9 on the top of the stacked structure 30.

[0232] Step S550 , depositing a conductive material in the connection hole 801 to form a connection line 80 .

[0233] The conductive material may be a material with strong conductive properties, which may include one material or two materials. For example, the conductive material may be titanium nitride and / or tungsten. For example, the conductive material may include titanium nitride and tungsten, and a titanium nitride layer that conformally covers the sidewalls and bottom of the connection hole 801 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this process, for the convenience of the process, the titanium nitride layer may simultaneously cover the etching stopper layer 800 or the protective layer 9 at the top of the stacked structure 30. Subsequently, tungsten may be filled in the connection hole 801 having the titanium nitride layer by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the tungsten may fill the connection hole. In this process, for the convenience of the process, tungsten may simultaneously cover the surface of the titanium nitride layer at the top of the stacked structure 30. It should be noted that after tungsten fills the connecting hole 801, the titanium carbide layer, tungsten and etching stop layer 800 located at the top of the stacked structure can be removed by back etching or grinding, and the ends of the titanium carbide layer and tungsten in the connecting hole away from the substrate 1 are made flush with the surface of the protective layer 9 away from the substrate 1, and the remaining titanium carbide layer and tungsten in the connecting hole 801 can be used as a connecting line 80.

[0234] Please note that, see Figure 1 and Fig.30 As shown, when the word line 5 includes two lead-out ends 502, each lead-out end 502 is provided with a connecting wire 80. The word line 5 can be electrically led out at the same time through the two connecting wires 80. During the signal transmission process, the two connecting wires 80 can make the signal more evenly distributed, which helps to reduce the reflection and attenuation of the signal during the transmission process, thereby improving the integrity and stability of the signal transmission. At the same time, the design of providing connecting wires 80 at both ends can balance the electromagnetic field distribution around the word line 5 to a certain extent, reduce the influence of external electromagnetic interference on signal transmission, and improve the anti-interference ability of the circuit.

[0235] It should be noted that, although the steps of the method for preparing a semiconductor memory in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0236] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor common block structure, prepared on a substrate, characterized in that: include: A plurality of semiconductor common unit structures located on the substrate, the semiconductor common unit structures comprising: a first storage unit and a second storage unit, the first storage unit and the second storage unit are arranged side by side in a mirror image along a first direction, the first storage unit and the second storage unit share a same source-drain unit layer, and the first direction is parallel to the surface of the substrate; Wherein, the first storage unit and the second storage unit both include: a first transistor, located above the top surface of the substrate, the first transistor comprising: a first gate, a first gate dielectric layer and a first semiconductor layer, the first gate extending along the first direction, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, the first semiconductor layer covering the surface of the first gate dielectric layer, and the first semiconductor layer comprising a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction; a second transistor, arranged side by side with the first transistor along the first direction, the second transistor comprising a second gate, a second gate dielectric layer and a second semiconductor layer, the second gate extending along the first direction, the second gate dielectric layer conformally covering the sidewall and the end of the second gate away from the first transistor, the second semiconductor layer covering the surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction; the second source and drain region is conductively connected to the second gate, the fourth source and drain region in the first storage unit and the fourth source and drain region in the second storage unit are respectively connected to two opposite surfaces of the source and drain unit layer; The plurality of semiconductor common unit structures are arranged at intervals along a second direction and a third direction, the second direction is parallel to the substrate and intersects the first direction, and the third direction is perpendicular to the first direction and the second direction; A source-drain layer, formed by sequentially connecting all the source-drain unit layers in the same plane end to end; The shielding cover structure has a shielding inner cavity, all the second transistors are accommodated in the shielding inner cavity, and all the first transistors are located outside the shielding cover structure.

2. The semiconductor common block structure according to claim 1, characterized in that: The shielding cover structure is a shell structure, which includes at least one shell layer of conductive material.

3. The semiconductor common block structure according to claim 1, characterized in that: The semiconductor common block structure further comprises: a plurality of word lines extending along the second direction and arranged at intervals along the first direction and the third direction, each of the word lines being connected to gates of a row of the first transistors arranged along the second direction in the same plane; a plurality of first bit lines extending along the third direction and arranged at intervals along the first direction and the second direction, each of the first bit lines covering an outer periphery of a row of the first source and drain regions arranged along the third direction in the same plane; A plurality of second bit lines extend along the third direction and are arranged at intervals along the first direction and the second direction, each of the second bit lines covers the periphery of a row of the third source and drain regions arranged along the third direction in the same plane.

4. The semiconductor common block structure according to claim 3, characterized in that: The word line includes a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the third direction, the orthographic projections of any two lead-out ends of the word lines on the substrate do not overlap, and the orthographic projections of any two main extension portions of the word lines on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the lengths of the word lines decrease or increase in sequence.

5. The semiconductor common block structure according to claim 4, characterized in that: The semiconductor common block structure further comprises: The connecting line extends along the third direction and is connected to the lead-out end of the word line.

6. A semiconductor memory, characterized in that: include: A substrate and a plurality of semiconductor common block structures according to any one of claims 1 to 5 located on the substrate, wherein the plurality of semiconductor common block structures are arranged along the first direction; Two adjacent semiconductor common block structures are arranged independently of each other.

7. A method for preparing a semiconductor memory, characterized in that: include: providing a substrate; A first memory cell and a second memory cell are formed on the substrate, wherein the first memory cell and the second memory cell are arranged side by side in a mirror image along a first direction, wherein the first direction is parallel to the surface of the substrate; the first memory cell and the second memory cell each include a first transistor and a second transistor arranged side by side along the first direction, wherein a source and drain region of the first transistor is electrically connected to a gate of the second transistor; forming a shielding cover structure for accommodating the second transistor of the first storage unit and the second transistor of the second storage unit in the shielding inner cavity; A source-drain unit layer is formed between the first memory cell and the second memory cell; a source-drain region of the second transistor of the first memory cell and a source-drain region of the second transistor of the second memory cell are respectively connected to two opposite sides of the source-drain unit layer.

8. The method for preparing a semiconductor memory according to claim 7, characterized in that: The preparation method further comprises: Before forming the second transistor, forming a word line material layer; The first transistor, the second transistor, the word line material layer and the shielding cover structure are formed on the substrate, including: Alternatingly depositing a first insulating material layer and a semiconductor material layer on the substrate in sequence to form a stacked structure; Performing patterning on the stacked structure to form a patterned stacked structure, wherein the pattern of the patterned stacked structure includes a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction is parallel to the surface of the substrate, the second direction is parallel to the substrate and intersects with the first direction; the first pattern overlaps with the second pattern; forming a second insulating material layer filling the gaps in the patterned stacked structure; A plurality of first openings are formed along a third direction penetrating the patterned stacked structure and the second insulating material layer, the first openings being arranged in one-to-one correspondence with the second patterns, and the first openings divide the corresponding second pattern into two sub-patterns that are distributed side by side in a mirror image along the first direction; the third direction is perpendicular to the first direction and the second direction, and the first openings are parallel to the plane where the second direction and the third direction are located; Part of the semiconductor material layer is etched away laterally toward both sides through the first opening to form a plurality of accommodating portions, wherein the accommodating portions include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and a word line accommodating groove extending along the second direction and connected to the row of first transistor accommodating grooves; A first semiconductor layer, a first gate dielectric layer and a first gate material layer are sequentially deposited in the accommodation portion; the first semiconductor layer covers the side wall and the bottom surface of the accommodation portion, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the accommodation portion; The first gate material layer deposited in the word line accommodating groove is etched away to form a first gate of the first transistor, and then the word line accommodating groove is filled with word line material to form a word line material layer, wherein the word line material layer is in contact with and connected to the first gate; the first transistor comprises the first gate, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, and the first semiconductor layer on the first gate comprises a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction; Forming a plurality of second openings along the third direction penetrating the patterned stacked structure and the second insulating material layer filled inside the patterned stacked structure, wherein the second openings are located at a middle position between two adjacent first openings, and the second openings are parallel to the second direction and the plane where the third direction is located; Etching away a portion of the first insulating material layer laterally toward both sides through the second opening to form a second gate of the second transistor, and etching away a portion of the second insulating material layer toward both sides of the patterned stacked structure along the second direction to define an outline of the shielding cover structure; A second gate dielectric layer and a second semiconductor layer are sequentially deposited on the exposed surface of the second gate and the contour surface of the shielding cover structure, the second gate dielectric layer conformally covers the side wall of the second gate, the end of the second gate away from the first transistor and the contour surface of the shielding cover structure, the second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer located on the second gate includes a third source and drain region, a second channel region and a fourth source and drain region sequentially distributed along the first direction.

9. The method for preparing a semiconductor memory according to claim 8, characterized in that: Before forming a plurality of first openings penetrating the patterned stacked structure and the second insulating material layer along the third direction, the method for preparing the semiconductor memory further includes: forming an etch stop layer embedded in the second insulating material layer; Forming the second insulating material layer and the etch stop layer includes: Depositing a third insulating material layer on the exposed surfaces of the substrate and the patterned stacked structure, wherein the third insulating material layer fills a gap between two adjacent first patterns in the patterned stacked structure, and depositing an etching stop material layer on the surface of the third insulating material layer; The remaining gaps in the patterned stacking structure are filled with insulating material and flattened to form the second insulating material layer and the etching stop layer. The second insulating material layer, the etching stop layer and the upper surface of the patterned stacking structure are flush, and the etching stop layer is used to define the shape and size of the shielding cover structure in the first direction.

10. The method for preparing a semiconductor memory according to claim 9, characterized in that: The step of etching away a portion of the first insulating material layer laterally toward both sides through the second opening to form a second gate of the second transistor, and etching away a portion of the second insulating material layer toward both sides of the patterned stacked structure along the second direction to define the outline of the shielding cover structure comprises: The first insulating material layer is etched away laterally toward both sides through the second opening, and the second insulating material layer is etched away toward both sides of the patterned stacked structure along the second direction. The etching stops when the etching stops.

11. The method for preparing a semiconductor memory according to claim 8, characterized in that: The preparation method further comprises: After forming the second semiconductor layer, a filling layer is formed to fill the shielding inner cavity of the shielding cover structure, and the filling layer closes the second opening.

12. The method for preparing a semiconductor memory according to claim 11, characterized in that: A source-drain unit layer is formed between the first memory unit and the second memory unit, comprising: forming a plurality of third openings penetrating the filling layer along the third direction, wherein the third openings are located within the second openings and expose the fourth source and drain regions in the second transistor, and the third openings are parallel to the second direction and the plane where the third direction is located; Filling a conductive material in the third opening to form a source-drain unit layer; The method for preparing the semiconductor memory further includes: Etching the first insulating material layer and the second insulating material layer to form a plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction; A first bit line is formed in the first bit line accommodating hole, and a second bit line is formed in the second bit line accommodating hole; each of the first bit lines is wrapped around the periphery of a row of the first source and drain regions arranged in the same plane along the third direction, and each of the second bit lines is wrapped around the periphery of a row of the third source and drain regions arranged in the same plane along the third direction.

13. The method for preparing a semiconductor memory according to claim 8, characterized in that: The preparation method further comprises: Each of the word line material layers and the first insulating material layer and the second insulating material layer covering each of the word lines are processed to form a plurality of word lines extending along the second direction and arranged at intervals along the third direction, wherein the word lines include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the word line lead-out structure, the orthographic projections of any two of the word lines' lead-out ends on the substrate do not overlap, and the orthographic projections of any two of the word lines' main extension portions on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the word lines decreases successively.

14. The method for preparing a semiconductor memory according to claim 13, characterized in that: The preparation method further comprises: forming a covering layer on a side of each of the lead-out ends away from the substrate; Etching the cover layer to form a plurality of connection holes penetrating the cover layer along the third direction, wherein orthographic projections of different connection holes on the substrate at least partially overlap with orthographic projections of different lead-out ends on the substrate; A conductive material is deposited in the connection hole to form a connection line.

Images