Three-dimensional capacitor structure of high-voltage charge pump and preparation method thereof

Abstract

The invention provides a three-dimensional capacitor structure of a high-voltage charge pump and a preparation method thereof, and the structure comprises an MOS capacitor which comprises a substrate, a first capacitor medium, and a polysilicon electrode; the three-dimensional vertical natural capacitor comprises at least two capacitor layers which are vertically stacked, each capacitor layer comprises a plurality of first metal electrode plates and second metal electrode plates which are arranged at intervals, and a second capacitor medium is arranged between every two adjacent first metal electrode plates and second metal electrode plates; an insulating layer is arranged between two adjacent capacitor layers, a conductive hole is formed in the insulating layer, and the first metal electrode plate and the second metal electrode plate in the two adjacent capacitor layers are connected with each other through the conductive hole; the first metal electrode plate is connected with a substrate of the MOS capacitor, and the second metal electrode plate is connected with a polycrystalline silicon electrode of the MOS capacitor. Through circuit layout and an innovative capacitor structure, the performance of the charge pump can be maintained, and meanwhile, the occupied chip area of the charge pump can be greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a three-dimensional capacitor structure of a high-voltage charge pump and a preparation method thereof. Background Art

[0002] In modern electronic systems, non-volatile memory (NVM) is becoming increasingly important due to its ability to retain data after power is removed. Non-volatile memory modules (NVM) are widely used in various electronic devices, including but not limited to computers, smartphones, embedded systems, etc. These modules usually contain logic circuits, high-voltage circuits, and non-volatile memory standard cells to achieve data storage and retrieval.

[0003] In the design of non-volatile memory modules, high-voltage circuits, especially charge pumps, are key components for implementing the programming and erasing functions of memory cells. The charge pump provides the required high voltage by generating a voltage higher than the power supply voltage, which is essential for the operation of the memory cell. However, the design and integration of the charge pump in the module often takes up a considerable chip area, which directly affects the size and cost of the entire memory module.

[0004] Taking the 2M capacity ESF3 (third generation SST embedded super flash memory) module as an example, the high voltage charge pump area may account for up to 20%. In the charge pump unit, the capacitor part occupies about 95% of the area. The capacitor plays a role in energy storage and regulation in the charge pump, but its large occupied area limits the further improvement of module integration.

[0005] As electronic devices develop towards smaller size and higher density, reducing chip area and improving integration have become important challenges for designers. In particular, in non-volatile memory modules, the area of ​​the charge pump and its capacitors accounts for a significant proportion. Therefore, compressing this part of the capacitor area and achieving a more compact design is of great significance for improving the performance of the entire module and reducing costs.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional capacitor structure of a high-voltage charge pump and a preparation method thereof, so as to solve the problem of excessively large area occupied by the high-voltage charge pump in the prior art.

[0008] To achieve the above-mentioned purpose and other related purposes, the present invention provides a three-dimensional capacitor structure of a high-voltage charge pump, and the three-dimensional capacitor structure of the high-voltage charge pump includes: a MOS capacitor, including a substrate, a first capacitor medium arranged on the substrate, and a polysilicon electrode arranged on the first capacitor medium; a three-dimensional vertical natural capacitor, including at least two vertically stacked capacitor layers, each capacitor layer including a plurality of first metal electrode plates and second metal electrode plates arranged at intervals, and a second capacitor medium is spaced between two adjacent first metal electrode plates and second metal electrode plates; an insulating layer is arranged between two adjacent capacitor layers, and a conductive hole is arranged in the insulating layer, and the conductive hole connects the first metal electrode plates in the two adjacent capacitor layers to each other and connects the second metal electrode plates in the two adjacent capacitor layers to each other; the first metal electrode plate is connected to one of the substrate and the polysilicon electrode, and the second metal electrode plate is connected to the other of the substrate and the polysilicon electrode.

[0009] Optionally, the number of capacitor layers of the three-dimensional vertical natural capacitor is 2 to 6 layers.

[0010] Optionally, the material of the first metal electrode plate and the second metal electrode plate is one of copper, aluminum, gold, titanium, tungsten and metal nitride.

[0011] Optionally, the material of the second capacitor medium is one of silicon dioxide, silicon nitride, silicon oxyfluoride, porous medium and polymer medium.

[0012] Optionally, the thickness of the insulating layer is 50 nanometers to 500 nanometers.

[0013] Optionally, the width of the first metal electrode plate and the second metal electrode plate is 30 nanometers to 400 nanometers, the spacing between the first metal electrode plate and the second metal electrode plate is 30 nanometers to 500 nanometers, and the thickness of the second capacitor dielectric layer is 30 nanometers to 500 nanometers.

[0014] Optionally, the conductive holes are a conductive hole structure that is continuously arranged relative to the same first metal electrode plate or the second metal electrode plate.

[0015] Optionally, multiple first metal electrode plates in the same layer are short-circuited by a first metal strip, and multiple second metal electrode plates are short-circuited by a second metal strip, and the first metal strip and the second metal strip are respectively located at opposite ends of the first metal electrode plate and the second metal electrode plate, so as to set the first metal electrode plate and the second metal electrode plate in the same layer as a forked structure.

[0016] Optionally, the conductive holes corresponding to the first metal electrode plate and the conductive holes corresponding to the second metal electrode plate are arranged relative to each other or in an alternating arrangement.

[0017] Optionally, the conductive holes are configured as a plurality of conductive units arranged at intervals corresponding to the same first metal electrode plate or the second metal electrode plate.

[0018] Optionally, the conductive units corresponding to the first metal electrode plate and the conductive units corresponding to the second metal electrode plate are arranged opposite to each other or in an alternating arrangement.

[0019] The present invention also provides a method for preparing a three-dimensional capacitor structure of a high-voltage charge pump, comprising the steps of: providing a substrate, sequentially forming a first capacitor dielectric and a polysilicon electrode on the substrate to form a MOS capacitor; forming a three-dimensional vertical natural capacitor on the MOS capacitor, the three-dimensional vertical natural capacitor comprising at least two vertically stacked capacitor layers, each capacitor layer comprising a plurality of first metal electrode plates and second metal electrode plates arranged at intervals, and a second capacitor dielectric being spaced between two adjacent first metal electrode plates and second metal electrode plates; an insulating layer being arranged between two adjacent capacitor layers, a conductive hole being arranged in the insulating layer, the conductive hole connecting the first metal electrode plates in the two adjacent capacitor layers to each other and connecting the second metal electrode plates in the two adjacent capacitor layers to each other; the first metal electrode plate being connected to one of the substrate and the polysilicon electrode, and the second metal electrode plate being connected to the other of the substrate and the polysilicon electrode.

[0020] As described above, the three-dimensional capacitor structure of the high-voltage charge pump and the method for manufacturing the same of the present invention have the following beneficial effects:

[0021] The present invention adopts MOS capacitor (MOS CAP) and back-end metal layer (BEOL) vertical natural capacitor stack to form a capacitor structure of a high-voltage charge pump. Through circuit layout and innovative capacitor structure, the chip area occupied by the charge pump can be greatly reduced while maintaining the performance of the charge pump.

[0022] In the traditional charge pump design, the capacitor part occupies a large space, which limits the integration and performance of the high-voltage charge pump. The present invention effectively utilizes the vertical space of the chip by vertically stacking the MOS capacitor (MOS CAP) with the back-end metal layer, thereby reducing the area requirement in the horizontal direction. This design not only improves the density of the capacitor, but also allows more circuit components to be integrated within the same chip area, improving the performance and reliability of the entire circuit.

[0023] The capacitor area of ​​the present invention can be saved by about 50%. The significant area reduction not only helps to reduce production costs, but also provides the possibility for further circuit optimization and functional integration. Through this innovative design, the present invention provides an important technological advancement for the development of non-volatile storage technology, which is expected to produce significant competitive advantages in the market.

[0024] At the same time, the present invention also provides a scalable solution, that is, as the number of stacked capacitor layers increases, the circuit area that can be saved also increases accordingly. This design method provides flexibility for storage modules of different sizes and requirements, and the number of stacked capacitor layers can be adjusted according to actual needs to achieve the best area saving effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0026] Figure 1 It is a schematic structural diagram of a three-dimensional capacitor structure of a high-voltage charge pump according to an embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram showing the electrode plate structure of the three-dimensional capacitor structure of the high-voltage charge pump according to an embodiment of the present invention.

[0028] Figure 3 to Figure 6 It is a schematic diagram showing the arrangement of conductive holes in a three-dimensional capacitor structure of a high-voltage charge pump according to an embodiment of the present invention.

[0029] Component number description

[0030] 10 MOS capacitor

[0031] 101 Substrate

[0032] 102 First capacitor dielectric

[0033] 103 Polysilicon Electrode

[0034] 20 Three-dimensional vertical capacitor

[0035] 201 First metal electrode plate

[0036] 202 First Metal Bar

[0037] 203 second metal electrode plate

[0038] 204 Second Metal Bar

[0039] 205 Conductive hole DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0042] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0043] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0044] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0045] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] like Figure 1 to Figure 6As shown, in an embodiment of the present invention, a three-dimensional capacitor structure of a high-voltage charge pump is provided. The charge pump achieves the ability to provide high voltage output in a limited space through innovative structural design, while significantly reducing the chip area occupied. The three-dimensional capacitor structure of the high-voltage charge pump of the present embodiment includes: a MOS capacitor 10, including a substrate, a first capacitor dielectric 102 arranged on the substrate 101, and a polysilicon electrode 103 arranged on the first capacitor dielectric 102; a three-dimensional vertical natural capacitor 20, including at least two vertically stacked capacitor layers, each capacitor layer including a plurality of first metal electrode plates 201 and second metal electrode plates 203 arranged at intervals, and a second capacitor dielectric is spaced between two adjacent first metal electrode plates 201 and second metal electrode plates 203; an insulating layer is arranged between two adjacent capacitor layers, and a conductive hole 205 is arranged in the insulating layer, and the conductive hole 205 connects the first metal electrode plates 201 in the two adjacent capacitor layers to each other and connects the second metal electrode plates 203 in the two adjacent capacitor layers to each other; the first metal electrode plate 201 is connected to one of the substrate 101 and the polysilicon electrode 103 of the MOS capacitor 10, and the second metal electrode plate 203 is connected to the other of the substrate 101 and the polysilicon electrode 103 of the MOS capacitor 10. In one embodiment, the first metal electrode plate 201 and the substrate 101 of the MOS capacitor 10 can be connected as a negative electrode of the capacitor, and the second metal electrode plate 203 and the polysilicon electrode 103 of the MOS capacitor 10 can be connected as a positive electrode of the capacitor.

[0048] It should be noted that the polarities and specific connection methods of the substrate 101, the polysilicon electrode 103, the first metal electrode plate 201, and the second metal electrode plate 203 can be set according to actual needs and are not limited to Figure 1 Polarity and connection shown.

[0049] Specifically, Figure 1 As shown, the MOS capacitor 10 includes a substrate 101, which serves as the base and lower electrode plate of the MOS capacitor 10. A first capacitor dielectric 102 is arranged on the substrate 101. The first capacitor dielectric 102 can be, for example, silicon dioxide, silicon nitride, silicon oxynitride or other high-K dielectrics. A polysilicon electrode 103 is arranged on the first capacitor dielectric 102, which serves as the upper electrode plate of the MOS capacitor 10 and forms a capacitor structure with the substrate 101 and the first capacitor dielectric 102.

[0050] Specifically, Figure 1As shown, the three-dimensional vertical natural capacitor 20 includes at least two vertically stacked capacitor layers, each capacitor layer is composed of a plurality of first metal electrode plates 201 and second metal electrode plates 203 arranged at intervals, and a second capacitor medium is spaced between adjacent first metal electrode plates 201 and second metal electrode plates 203 to form a capacitor structure. The material of the first metal electrode plate 201 and the second metal electrode plate 203 can be selected from one of copper, aluminum, gold, titanium, tungsten and metal nitride to ensure good conductivity and stability. The material of the second capacitor medium can be selected from one of silicon dioxide, silicon nitride, silicon oxyfluoride, porous medium and polymer medium, which can be selected according to the required dielectric constant.

[0051] Specifically, each capacitor layer, insulating layer and conductive hole 205 can be arranged in the same layer as the interconnection metal layer of the device or circuit, that is, they can be formed simultaneously with the interconnection metal layer in the same deposition and patterning process. The three-dimensional vertical natural capacitor 20 of this embodiment does not actually require additional preparation of insulating layers and metal layers, but can be designed and prepared using the original interconnection metal layer, without the need for additional process steps, and has the advantages of simple process and low process cost.

[0052] The capacitance value of the three-dimensional vertical natural capacitor 20 of this embodiment can increase with the increase of the number of capacitor layers. In some embodiments, the number of capacitor layers of the three-dimensional vertical natural capacitor 20 is 2 to 6 layers. For example, in this embodiment, the number of capacitor layers of the three-dimensional vertical natural capacitor 20 is 4 layers. Of course, the number of capacitor layers can be determined according to actual needs and is not limited to the examples listed here. The present invention also provides a scalable solution, that is, for the same required capacitance value, as the number of stacked capacitor layers increases, the circuit area that can be saved also increases accordingly. This design method provides flexibility for storage modules of different sizes and requirements, and the number of stacked capacitor layers can be adjusted according to actual needs to achieve the best area saving effect.

[0053] In one embodiment, the thickness of the insulating layer is 50 nanometers to 500 nanometers, for example, 100 nanometers, 200 nanometers, 300 nanometers, etc. The insulating layer is used to isolate two adjacent capacitor layers. The material of the insulating layer can be, for example, silicon dioxide, silicon nitride, silicon oxynitride, etc., and is not limited to the examples listed here.

[0054] In one embodiment, the width of the first metal electrode plate 201 and the second metal electrode plate 203 is 30 nanometers to 400 nanometers, for example, 50 nanometers, 100 nanometers, 200 nanometers, etc., the spacing between the first metal electrode plate 201 and the second metal electrode plate 203 is 30 nanometers to 500 nanometers, for example, 50 nanometers, 100 nanometers, 200 nanometers, etc., and the thickness of the second capacitor dielectric layer is 30 nanometers to 500 nanometers, for example, 50 nanometers, 100 nanometers, 200 nanometers, etc.

[0055] In one embodiment, Figure 2 As shown (conductive holes are not shown), multiple first metal electrode plates 201 in the same layer are short-circuited by the first metal strip 202, and multiple second metal electrode plates 203 are short-circuited by the second metal strip 204. The first metal strip 202 and the second metal strip 204 are respectively located at opposite ends of the first metal electrode plate 201 and the second metal electrode plate 203, so that the first metal electrode plate 201 and the second metal electrode plate 203 in the same layer are set as a forked structure. The first metal electrode plate 201 and the second metal electrode plate 203 with the forked structure can facilitate the separate lead-out of the first metal electrode plate 201 and the second metal electrode plate 203, thereby greatly saving the area occupied by the lead wires.

[0056] In one embodiment, the conductive holes 205 are continuously arranged with respect to the same first metal electrode plate 201 or the second metal electrode plate 203 to reduce resistance and process difficulty. The conductive holes 205 corresponding to the first metal electrode plate 201 and the conductive holes 205 corresponding to the second metal electrode plate 203 are arranged relative to each other, such as Figure 3 As shown, the conductive holes 205 arranged relatively can reduce the difficulty of design and manufacturing, and can increase the variable range of the size of the conductive holes 205. Alternatively, in another embodiment, the conductive holes 205 corresponding to the first metal electrode plate 201 and the conductive holes 205 corresponding to the second metal electrode plate 203 are arranged in a staggered manner, such as Figure 4 As shown, the staggered arrangement of the conductive vias 205 can increase the average spacing between adjacent conductive vias 205 , greatly reduce the risk of short circuits between the conductive vias 205 , and improve the process window.

[0057] In one embodiment, the conductive hole 205 is a conductive hole structure comprising a plurality of conductive units arranged at intervals relative to the same first metal electrode plate 201 or the second metal electrode plate 203, so as to improve the flexibility of the arrangement design of the conductive hole 205. The conductive units corresponding to the first metal electrode plate 201 and the conductive units corresponding to the second metal electrode plate 203 are arranged relative to each other, such as Figure 5 As shown, the conductive units arranged relatively can reduce the difficulty of design and manufacturing, and can increase the variable range of the conductive unit size. Alternatively, in another embodiment, the conductive units corresponding to the first metal electrode plate 201 and the conductive units corresponding to the second metal electrode plate 203 are arranged in a staggered manner, such as Figure 6 As shown, the staggered arrangement of conductive units can increase the average spacing between adjacent conductive units, greatly reduce the risk of short circuits between conductive units, and improve the process window.

[0058] The present invention forms a capacitor structure of a high-voltage charge pump by adopting a MOS capacitor 10 device (MOS CAP) and a back-end metal layer (BEOL) vertically-generated capacitor stack. Through circuit layout and innovative capacitor structure, the chip area occupied by the high-voltage charge pump can be greatly reduced while maintaining the performance of the charge pump. In the traditional charge pump design, the capacitor part occupies a large space, which limits the integration and performance of the high-voltage charge pump. The present invention effectively utilizes the vertical space of the chip by vertically stacking the MOS capacitor 10 device (MOS CAP) and the back-end metal layer, thereby reducing the area requirement in the horizontal direction. This design not only improves the density of the capacitor, but also allows more circuit elements to be integrated within the same chip area, thereby improving the performance and reliability of the entire circuit.

[0059] like Figure 1 to Figure 6 As shown, this embodiment also provides a method for preparing a three-dimensional capacitor structure of a high-voltage charge pump, the preparation method comprising the following steps:

[0060] Step 1) provides a substrate 101 , and sequentially forms a first capacitor dielectric 102 and a polysilicon electrode 103 on the substrate 101 to form a MOS capacitor 10 .

[0061] The substrate 101 may be, for example, a silicon substrate, a germanium substrate, a germanium silicon substrate, etc., and is not limited to the examples listed here. The surface or the entirety of the substrate 101 may be conductively doped, such as N-type doping or P-type doping.

[0062] The first capacitor dielectric 102 may be formed on the surface of the substrate 101 by, for example, a chemical vapor deposition process.

[0063] The polysilicon electrode 103 may be formed on the surface of the first capacitor dielectric 102 by, for example, a chemical vapor deposition process. The polysilicon electrode 103 may be conductively doped, such as N-type doping or P-type doping.

[0064] Step 2), forming a three-dimensional vertical natural capacitor 20 on the MOS capacitor 10, the three-dimensional vertical natural capacitor 20 includes at least two capacitor layers stacked vertically, each capacitor layer includes a plurality of first metal electrode plates 201 and second metal electrode plates 203 arranged at intervals, and a second capacitor medium is spaced between two adjacent first metal electrode plates 201 and second metal electrode plates 203; an insulating layer is provided between two adjacent capacitor layers, and a conductive hole is provided in the insulating layer, and the conductive hole connects the first metal electrode plates 201 in the two adjacent capacitor layers to each other and connects the second metal electrode plates 203 in the two adjacent capacitor layers to each other; the first metal electrode plate 201 is connected to one of the substrate 101 and the polysilicon electrode 103 of the MOS capacitor 10, and the second metal electrode plate 203 is connected to the substrate 101 and the other of the polysilicon electrode 103 of the MOS capacitor 10. In one embodiment, the first metal electrode plate 201 and the substrate 101 of the MOS capacitor 10 can be connected as the negative electrode of the capacitor, and the second metal electrode plate 203 and the polysilicon electrode 103 of the MOS capacitor 10 can be connected as the positive electrode of the capacitor.

[0065] Specifically, the following steps may be included:

[0066] Step 1) firstly forms an isolation dielectric, such as a silicon dioxide layer, on the MOS capacitor 10 and performs planarization. For example, a chemical mechanical polishing (CMP) process may be used to planarize the isolation dielectric.

[0067] Step 2), depositing a first metal layer on the isolation medium, and patterning the first metal layer to form an interdigitated structure including a plurality of first metal electrode plates 201 and second metal electrode plates 203 arranged at intervals, and also forming a metal wiring structure of the device;

[0068] Step 3), depositing a first dielectric layer on the first metal layer, the first dielectric layer is filled between the adjacent first metal electrode plate 201 and the second metal electrode plate 203 to form a second capacitor dielectric, so as to form a capacitor layer, and at the same time, the first dielectric layer can also serve as an insulating layer between the first metal layer and the second metal layer above it;

[0069] Step 4), forming a through hole in the insulating layer to expose the first metal electrode plate 201 and the second metal electrode plate 203, and also to expose the metal wiring structure of the device;

[0070] Step 5), filling the through hole with a conductive material to form a conductive hole;

[0071] Step 6), repeating the above steps to form a three-dimensional vertical natural capacitor 20 including multiple capacitor layers;

[0072] Step 7), connecting the first metal electrode plate 201 to the substrate 101 of the MOS capacitor 10 through a conductive through hole or a lead process, and connecting the second metal electrode plate 203 to the polysilicon electrode 103 of the MOS capacitor 10.

[0073] As described above, the three-dimensional capacitor structure of the high-voltage charge pump and the preparation method thereof of the present invention have the following beneficial effects:

[0074] The present invention adopts MOS capacitor (MOS CAP) and back-end metal layer (BEOL) vertical natural capacitor stack to form a capacitor structure of a high-voltage charge pump. Through circuit layout and innovative capacitor structure, the chip area occupied by the charge pump can be greatly reduced while maintaining the performance of the charge pump.

[0075] In the traditional charge pump design, the capacitor part occupies a large space, which limits the integration and performance of the high-voltage charge pump. The present invention effectively utilizes the vertical space of the chip by vertically stacking the MOS capacitor (MOS CAP) with the back-end metal layer, thereby reducing the area requirement in the horizontal direction. This design not only improves the density of the capacitor, but also allows more circuit components to be integrated within the same chip area, improving the performance and reliability of the entire circuit.

[0076] The capacitor area of ​​the present invention can be saved by about 50%. The significant area reduction not only helps to reduce production costs, but also provides the possibility for further circuit optimization and functional integration. Through this innovative design, the present invention provides an important technological advancement for the development of non-volatile storage technology, which is expected to produce significant competitive advantages in the market.

[0077] At the same time, the present invention also provides a scalable solution, that is, as the number of stacked capacitor layers increases, the circuit area that can be saved also increases accordingly. This design method provides flexibility for storage modules of different sizes and requirements, and the number of stacked capacitor layers can be adjusted according to actual needs to achieve the best area saving effect.

[0078] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A three-dimensional capacitor structure of a high-voltage charge pump, characterized in that: The three-dimensional capacitor structure comprises: A MOS capacitor comprises a substrate, a first capacitor medium disposed on the substrate, and a polysilicon electrode disposed on the first capacitor medium; A three-dimensional vertical natural capacitor includes at least two capacitor layers stacked vertically, each of the capacitor layers includes a plurality of first metal electrode plates and second metal electrode plates arranged at intervals, and a second capacitor medium is spaced between two adjacent first metal electrode plates and second metal electrode plates; an insulating layer is arranged between two adjacent capacitor layers, and a conductive hole is arranged in the insulating layer, and the conductive hole connects the first metal electrode plates in the two adjacent capacitor layers to each other and connects the second metal electrode plates in the two adjacent capacitor layers to each other; the first metal electrode plate is connected to one of the substrate and the polysilicon electrode, and the second metal electrode plate is connected to the other of the substrate and the polysilicon electrode.

2. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The number of capacitor layers of the three-dimensional vertical natural capacitor is 2 to 6 layers.

3. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The material of the first metal electrode plate and the second metal electrode plate is one of copper, aluminum, gold, titanium, tungsten and metal nitride.

4. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The material of the second capacitor medium is one of silicon dioxide, silicon nitride, silicon oxyfluoride, porous medium and polymer medium.

5. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The thickness of the insulating layer is 50 nanometers to 500 nanometers.

6. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The width of the first metal electrode plate and the second metal electrode plate is 30 nanometers to 400 nanometers, the distance between the first metal electrode plate and the second metal electrode plate is 30 nanometers to 500 nanometers, and the thickness of the second capacitor dielectric layer is 30 nanometers to 500 nanometers.

7. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: Multiple first metal electrode plates in the same layer are short-circuited by a first metal strip, and multiple second metal electrode plates are short-circuited by a second metal strip. The first metal strip and the second metal strip are respectively located at opposite ends of the first metal electrode plate and the second metal electrode plate, so as to set the first metal electrode plate and the second metal electrode plate in the same layer into a forked structure.

8. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The conductive holes are a conductive hole structure that is continuously arranged relative to the same first metal electrode plate or the second metal electrode plate.

9. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 8, characterized in that: The conductive holes corresponding to the first metal electrode plate and the conductive holes corresponding to the second metal electrode plate are arranged oppositely or staggered.

10. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 1, characterized in that: The conductive holes are configured as a plurality of conductive units arranged at intervals corresponding to the same first metal electrode plate or the second metal electrode plate.

11. The three-dimensional capacitor structure of the high-voltage charge pump according to claim 10, characterized in that: The conductive units corresponding to the first metal electrode plate and the conductive units corresponding to the second metal electrode plate are arranged opposite to each other or in an alternating manner.

12. A method for preparing a three-dimensional capacitor structure of a high-voltage charge pump, characterized in that: Includes steps: Providing a substrate, and sequentially forming a first capacitor dielectric and a polysilicon electrode on the substrate to form a MOS capacitor; A three-dimensional vertical natural capacitor is formed on the MOS capacitor, and the three-dimensional vertical natural capacitor includes at least two capacitor layers stacked vertically, each of the capacitor layers includes a plurality of first metal electrode plates and second metal electrode plates arranged at intervals, and a second capacitor medium is spaced between two adjacent first metal electrode plates and second metal electrode plates; an insulating layer is provided between two adjacent capacitor layers, and a conductive hole is provided in the insulating layer, and the conductive hole connects the first metal electrode plates in the two adjacent capacitor layers to each other and connects the second metal electrode plates in the two adjacent capacitor layers to each other; the first metal electrode plate is connected to one of the substrate and the polysilicon electrode, and the second metal electrode plate is connected to the other of the substrate and the polysilicon electrode. .

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