System software design method and system for manufacturability verification of integrated circuit

Abstract

The invention provides a system software design method and system for manufacturability verification of an integrated circuit, and relates to the technical field of integrated circuits, and the method comprises the following steps: constructing a multi-level verification model based on integrated circuit design data, carrying out parallel computing processing on the multi-level verification model, generating a manufacturability prediction result, and identifying potential manufacturing defects. Based on the potential manufacturing defects, an optimization suggestion is automatically generated, and the optimization suggestion comprises a layout modification scheme and a process parameter adjustment scheme; applying the optimization suggestion to the integrated circuit design data to generate optimized design data; iterative verification is carried out on the optimized design data until preset manufacturability indexes are met, and the manufacturability indexes comprise the yield, reliability and performance parameters; and transmitting the integrated circuit manufacturing data packet to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and in particular to a system software design method and system for integrated circuit manufacturability verification. Background Art

[0002] As integrated circuit manufacturing processes continue to develop towards more advanced nodes, the gap between chip design and manufacturing is widening. Traditional design methods have been unable to guarantee the manufacturability of the design, which has led to problems such as reduced chip yield and substandard performance, seriously affecting the development of the integrated circuit industry. Therefore, it is becoming increasingly important to conduct manufacturability verification during the design phase. At present, integrated circuit manufacturability verification mainly faces the following challenges:

[0003] High verification complexity: With the continuous expansion of chip design scale and the continuous reduction of process nodes, more and more factors need to be considered in manufacturability verification, and the amount of calculation is growing exponentially. Traditional serial calculation methods can no longer meet the time requirements of verification. Multi-scale modeling is difficult: Integrated circuits involve multiple scales from nanoscale devices to centimeter-level chips, and the physical mechanisms and influencing factors at different scales are different. How to achieve multi-scale modeling and simulation under a unified framework is a huge challenge.

[0004] Insufficient defect identification accuracy: Existing defect identification methods are mainly based on rule checking and simple graphic analysis, which makes it difficult to accurately capture complex process effects and potential manufacturing defects. Especially for advanced process nodes, many defects are statistical in nature and are difficult to effectively identify with traditional methods. Lack of targeted optimization suggestions: Current manufacturability optimization is mostly based on fixed design rules, lacking consideration of specific design and process characteristics. This approach often leads to overly conservative designs, affecting chip performance and area efficiency.

[0005] Insufficient collaboration between design and manufacturing: Most existing manufacturability verification tools operate independently and are not highly integrated with design tools and manufacturing data. This makes it difficult to feed back verification results to the design process in a timely and effective manner, affecting the efficiency of design optimization. Poor adaptability to new processes and new devices: With the continuous emergence of new materials and new device structures, existing manufacturability verification methods and tools are difficult to quickly adapt to these changes. How to build a flexible and scalable verification framework has become an urgent problem to be solved.

[0006] In order to solve these problems, the industry has made some attempts. For example, parallel computing technology is used to improve the verification speed, machine learning methods are introduced to improve the accuracy of defect identification, and model-based optimization methods are developed to provide more targeted optimization suggestions. However, these methods are mostly local optimizations for a single problem and lack a systematic solution.

[0007] Therefore, it is urgent to develop an integrated and intelligent manufacturability verification system software that can comprehensively solve the above challenges, achieve seamless connection from design to manufacturing, and improve the design efficiency and manufacturing yield of integrated circuits. This is exactly the technical problem that the present invention aims to solve. Summary of the invention

[0008] The embodiments of the present invention provide a system software design method and system for integrated circuit manufacturability verification, which can solve the problems in the prior art.

[0009] According to a first aspect of the embodiments of the present invention,

[0010] Provides a system software design method for integrated circuit manufacturability verification, including:

[0011] Receive integrated circuit design data, the integrated circuit design data including layout data and process parameters; construct a multi-level verification model based on the integrated circuit design data, the multi-level verification model including a device-level model, a unit-level model and a chip-level model; perform parallel computing processing on the multi-level verification model to generate a manufacturability prediction result, the parallel computing processing adopts a distributed computing architecture to distribute the verification task to multiple computing nodes;

[0012] According to the manufacturability prediction results, potential manufacturing defects are identified, wherein the potential manufacturing defects include lithography hot spots, metal bridges, and via missing; based on the potential manufacturing defects, optimization suggestions are automatically generated, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; the optimization suggestions are applied to the integrated circuit design data to generate optimized design data; the optimized design data is iteratively verified until preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability, and performance parameters;

[0013] Generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and final manufacturability evaluation results; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

[0014] In an optional embodiment,

[0015] Based on the integrated circuit design data, a multi-level verification model is constructed, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; and the multi-level verification model is processed in parallel to generate a manufacturability prediction result, including:

[0016] Receiving integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters;

[0017] A multi-level verification model is constructed based on the integrated circuit design data, and the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; wherein, when constructing the device-level model, a TCAD tool is used to combine process parameters and device geometry information, and an accurate device physical model is constructed by considering quantum effects and stress effects; when constructing the unit-level model, a sensitivity analysis method is used to identify key parameters and establish a parameterized model; when constructing the chip-level model, a hierarchical wiring model and a timing model are used, combined with statistical static timing analysis technology, to establish a performance and reliability model within the entire chip;

[0018] In an optional embodiment,

[0019] The method further comprises:

[0020] The multi-level verification model is processed in parallel to generate a manufacturability prediction result, wherein the parallel processing includes:

[0021] Decompose the verification task into multiple independent subtasks, adopt the regional decomposition strategy for device-level models and unit-level models, and adopt the functional module decomposition strategy for chip-level models; use the dynamic load balancing algorithm to adjust the task allocation in real time according to the computational complexity and data dependency of each subtask;

[0022] A hybrid programming model of MPI and OpenMP is used to implement parallel computing, where MPI is used for inter-node communication and OpenMP is used for multi-threaded parallelism within a node. A data synchronization mechanism is designed to ensure data consistency between different computing nodes, and a hierarchical data integration method is used to combine the results of each subtask.

[0023] Based on the integrated data, manufacturability indicators are calculated, and the manufacturability indicators include process window, critical dimension variation and yield prediction; based on the manufacturability indicators, potential manufacturing defects are identified and optimization suggestions are generated; the optimization suggestions are applied to the integrated circuit design data to generate optimized design data; the steps of constructing a multi-level verification model, parallel computing and calculating manufacturability indicators are repeatedly executed on the optimized design data until the preset manufacturability requirements are met.

[0024] In an optional embodiment,

[0025] According to the manufacturability prediction results, potential manufacturing defects are identified, and the potential manufacturing defects include lithography hot spots, metal bridges, and via missing. Based on the potential manufacturing defects, optimization suggestions are automatically generated, and the optimization suggestions include layout modification solutions and process parameter adjustment solutions including:

[0026] Receiving the manufacturability prediction results of the integrated circuit; identifying potential manufacturing defects using a multi-scale defect recognition algorithm, wherein the multi-scale defect recognition algorithm includes: using a machine learning-assisted lithography simulation method to identify lithography hotspots, wherein a fast lithography model is used to perform a preliminary scan of the entire chip, and high-precision lithography simulation is applied to areas where problems may exist, and a convolutional neural network model trained with a large amount of historical data is combined to accurately identify and classify lithography hotspots; using an electric field simulation-based method to detect metal bridging, wherein a three-dimensional electric field distribution simulation is performed on the metal layer, an adaptive threshold algorithm is used to identify high electric field intensity areas, and metal spacing and metal density are comprehensively evaluated in combination with layout design rule check results;

[0027] A multi-level approach is applied to analyze via missingness, including using topology analysis algorithms at the chip level to check the connectivity of critical signal paths, applying pattern matching techniques at the cell level to identify high-risk layout structures, and considering local stress distribution and material properties at the device level to evaluate the failure probability during via formation.

[0028] In an optional embodiment,

[0029] The method further comprises:

[0030] Based on the identified potential manufacturing defects, automatically generate optimization suggestions using an intelligent optimization system, the intelligent optimization system including a layout modification solution generator and a process parameter adjustment solution generator;

[0031] The layout modification scheme generator generates layout modification suggestions using rule-based and heuristic algorithms, and introduces a genetic algorithm to automatically explore multiple layout modification schemes while keeping the circuit function unchanged;

[0032] The process parameter adjustment scheme generator uses machine learning technology to establish a process-defect correlation model, and uses a Bayesian optimization algorithm to automatically search for the optimal process parameter combination under the condition of satisfying the process window constraints;

[0033] The optimization suggestion integration module combines the layout modification plan and the process parameter adjustment plan to generate comprehensive optimization suggestions, which considers the mutual influence between different optimization measures to ensure that the final optimization plan is the global optimal one.

[0034] Rapidly simulate and verify the generated comprehensive optimization suggestions to evaluate their effectiveness;

[0035] According to the results of rapid simulation verification, the comprehensive optimization suggestions are iteratively optimized until the preset manufacturability requirements are met;

[0036] Apply the final comprehensive optimization suggestions to the integrated circuit design to generate optimized integrated circuit design data;

[0037] The manufacturability prediction is re-performed on the optimized integrated circuit design data to verify the optimization effect.

[0038] According to a second aspect of the embodiments of the present invention,

[0039] Provides a system software design system for integrated circuit manufacturability verification, including:

[0040] The first unit is used to receive integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters; based on the integrated circuit design data, construct a multi-level verification model, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; perform parallel computing processing on the multi-level verification model to generate a manufacturability prediction result, wherein the parallel computing processing adopts a distributed computing architecture to distribute the verification task to multiple computing nodes;

[0041] The second unit is used to identify potential manufacturing defects according to the manufacturability prediction result, wherein the potential manufacturing defects include lithography hot spots, metal bridges, and via missing; based on the potential manufacturing defects, automatically generate optimization suggestions, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; apply the optimization suggestions to the integrated circuit design data to generate optimized design data; iteratively verify the optimized design data until preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability, and performance parameters;

[0042] The third unit is used to generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and a final manufacturability evaluation result; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; and transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

[0043] According to a third aspect of the embodiments of the present invention,

[0044] An electronic device is provided, comprising:

[0045] processor;

[0046] a memory for storing processor-executable instructions;

[0047] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0048] A fourth aspect of the embodiments of the present invention is:

[0049] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0050] Beneficial effects:

[0051] Improve the accuracy and comprehensiveness of manufacturability assessments:

[0052] By building a multi-level verification model including device level, unit level and chip level, this method can comprehensively capture various potential problems in integrated circuit design from micro to macro. This multi-level approach can more accurately reflect the real manufacturing environment and significantly improve the accuracy of manufacturability assessment.

[0053] Significantly improve computing efficiency:

[0054] The distributed computing architecture is used for parallel processing, and verification tasks are assigned to multiple computing nodes, which greatly improves the computing speed. For complex modern integrated circuit designs, this method can shorten the verification time from traditional days or even weeks to hours, greatly accelerating the design iteration speed.

[0055] Enhanced defect identification capabilities:

[0056] The system can identify a variety of potential manufacturing defects, including lithography hot spots, metal bridges, and via missing, etc. This comprehensive defect identification capability can significantly reduce the risk of failure in the chip manufacturing process and improve the yield rate of the final product.

[0057] Achieve intelligent optimization:

[0058] Based on the potential defects identified, the system can automatically generate optimization suggestions, including layout modification solutions and process parameter adjustment solutions. This intelligent optimization process not only reduces manual intervention, but also explores more possible optimization solutions and finds better solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic diagram of a flow chart of a system software design method for integrated circuit manufacturability verification according to an embodiment of the present invention;

[0060] Figure 2 A schematic diagram of the structure of a system software design system for integrated circuit manufacturability verification according to an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0063] Figure 1 FIG. 1 is a flow chart of a system software design method for integrated circuit manufacturability verification according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0064] S101. Receive integrated circuit design data, the integrated circuit design data including layout data and process parameters; construct a multi-level verification model based on the integrated circuit design data, the multi-level verification model including a device-level model, a unit-level model and a chip-level model; perform parallel computing processing on the multi-level verification model to generate a manufacturability prediction result, the parallel computing processing adopts a distributed computing architecture to distribute the verification task to multiple computing nodes;

[0065] S102. According to the manufacturability prediction result, potential manufacturing defects are identified, wherein the potential manufacturing defects include lithography hot spots, metal bridges, and via missing; based on the potential manufacturing defects, optimization suggestions are automatically generated, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; the optimization suggestions are applied to the integrated circuit design data to generate optimized design data; the optimized design data is iteratively verified until preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability, and performance parameters;

[0066] S103. Generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and final manufacturability evaluation results; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

[0067] In an optional embodiment,

[0068] Based on the integrated circuit design data, a multi-level verification model is constructed, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; and the multi-level verification model is processed in parallel to generate a manufacturability prediction result, including:

[0069] Receiving integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters;

[0070] A multi-level verification model is constructed based on the integrated circuit design data, and the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; wherein, when constructing the device-level model, a TCAD tool is used to combine process parameters and device geometry information, and an accurate device physical model is constructed by considering quantum effects and stress effects; when constructing the unit-level model, a sensitivity analysis method is used to identify key parameters and establish a parameterized model; when constructing the chip-level model, a hierarchical wiring model and a timing model are used, combined with statistical static timing analysis technology, to establish a performance and reliability model within the entire chip;

[0071] In an optional embodiment,

[0072] The method further comprises:

[0073] The multi-level verification model is processed in parallel to generate a manufacturability prediction result, wherein the parallel processing includes:

[0074] Decompose the verification task into multiple independent subtasks, adopt the regional decomposition strategy for device-level models and unit-level models, and adopt the functional module decomposition strategy for chip-level models; use the dynamic load balancing algorithm to adjust the task allocation in real time according to the computational complexity and data dependency of each subtask;

[0075] A hybrid programming model of MPI and OpenMP is used to implement parallel computing, where MPI is used for inter-node communication and OpenMP is used for multi-threaded parallelism within a node. A data synchronization mechanism is designed to ensure data consistency between different computing nodes, and a hierarchical data integration method is used to combine the results of each subtask.

[0076] Based on the integrated data, manufacturability indicators are calculated, and the manufacturability indicators include process window, critical dimension variation and yield prediction; based on the manufacturability indicators, potential manufacturing defects are identified and optimization suggestions are generated; the optimization suggestions are applied to the integrated circuit design data to generate optimized design data; the steps of constructing a multi-level verification model, parallel computing and calculating manufacturability indicators are repeatedly executed on the optimized design data until the preset manufacturability requirements are met.

[0077] In an optional embodiment,

[0078] According to the manufacturability prediction results, potential manufacturing defects are identified, and the potential manufacturing defects include lithography hot spots, metal bridges, and via missing. Based on the potential manufacturing defects, optimization suggestions are automatically generated, and the optimization suggestions include layout modification solutions and process parameter adjustment solutions, including:

[0079] Receiving the manufacturability prediction results of the integrated circuit; identifying potential manufacturing defects using a multi-scale defect recognition algorithm, wherein the multi-scale defect recognition algorithm includes: using a machine learning-assisted lithography simulation method to identify lithography hotspots, wherein a fast lithography model is used to perform a preliminary scan of the entire chip, and high-precision lithography simulation is applied to areas where problems may exist, and a convolutional neural network model trained with a large amount of historical data is combined to accurately identify and classify lithography hotspots; using an electric field simulation-based method to detect metal bridging, wherein a three-dimensional electric field distribution simulation is performed on the metal layer, an adaptive threshold algorithm is used to identify high electric field intensity areas, and metal spacing and metal density are comprehensively evaluated in combination with layout design rule check results;

[0080] A multi-level approach is applied to analyze via missing components, including using topology analysis algorithms at the chip level to check the connectivity of critical signal paths, applying pattern matching techniques at the cell level to identify high-risk layout structures, and considering local stress distribution and material properties at the device level to evaluate the failure probability during via formation.

[0081] In an optional embodiment,

[0082] The method further comprises:

[0083] Based on the identified potential manufacturing defects, automatically generate optimization suggestions using an intelligent optimization system, the intelligent optimization system including a layout modification solution generator and a process parameter adjustment solution generator;

[0084] The layout modification scheme generator generates layout modification suggestions using rule-based and heuristic algorithms, and introduces a genetic algorithm to automatically explore multiple layout modification schemes while keeping the circuit function unchanged;

[0085] The process parameter adjustment scheme generator uses machine learning technology to establish a process-defect correlation model, and uses a Bayesian optimization algorithm to automatically search for the optimal process parameter combination under the condition of satisfying the process window constraints;

[0086] The optimization suggestion integration module combines the layout modification plan and the process parameter adjustment plan to generate comprehensive optimization suggestions, which considers the mutual influence between different optimization measures to ensure that the final optimization plan is the global optimal one.

[0087] Rapidly simulate and verify the generated comprehensive optimization suggestions to evaluate their effectiveness;

[0088] According to the results of rapid simulation verification, the comprehensive optimization suggestions are iteratively optimized until the preset manufacturability requirements are met;

[0089] Apply the final comprehensive optimization suggestions to the integrated circuit design to generate optimized integrated circuit design data;

[0090] The manufacturability prediction is re-performed on the optimized integrated circuit design data to verify the optimization effect.

[0091] Another embodiment of the present application is as follows:

[0092] The core of the software design of the integrated circuit manufacturability verification system is to build a multi-level verification model and perform parallel computing to generate reliable manufacturability prediction results. The implementation of this system involves multiple key steps, each of which is closely linked to form a complete technical solution.

[0093] First, the system receives the integrated circuit design data, including detailed layout data and process parameters. These data are the basis for all subsequent analysis and optimization. The layout data contains the geometric information of the chip, such as the pattern, size and position of each layer. The process parameters describe the key conditions in the manufacturing process, such as the lithography wavelength, etching time, etc.

[0094] Next, a multi-level verification model is built based on these input data. This model is divided into three levels: device level, unit level and chip level, each of which has its own specific modeling methods and concerns.

[0095] In device-level model construction, the system uses TCAD (Technology Computer-Aided Design) tools, combined with process parameters and device geometry information, to build an accurate device physical model. This model takes into account quantum effects and stress effects, and can accurately predict the behavior of devices at the nanoscale. For example, for FinFET devices at the 14nm process node, the model will consider the impact of channel stress on carrier mobility and the modulation of the threshold voltage by the quantum confinement effect.

[0096] The construction of the cell-level model adopts the sensitivity analysis method. The system first identifies the key parameters that affect the performance of the cell, such as transistor width-to-length ratio, parasitic capacitance, etc., and then builds a parameterized model. This method can greatly reduce the number of variables that need to be considered and improve modeling efficiency. For example, for a NAND gate in a standard cell library, the system may find that the drive strength and input capacitance are the two most critical parameters, and build a simplified but accurate model based on this.

[0097] The chip-level model is constructed using a hierarchical wiring model and a timing model, combined with statistical static timing analysis techniques. This allows the system to build performance and reliability models across the entire chip while taking into account the impact of process variation. For example, for a digital chip containing 1 million gates, the system can predict the maximum operating frequency distribution under different process corners.

[0098] After building the multi-level verification model, the system enters the parallel computing processing stage. The goal of this stage is to efficiently generate manufacturability prediction results. First, the system decomposes the verification task into multiple independent subtasks. For device-level and unit-level models, the regional decomposition strategy is adopted to divide the chip into multiple physical areas for parallel computing. For chip-level models, the functional module decomposition strategy is adopted to divide the tasks according to the designed functional blocks.

[0099] During the task allocation process, the system uses a dynamic load balancing algorithm to adjust the task allocation in real time according to the computational complexity and data dependencies of each subtask. This ensures efficient use of computing resources. For example, for an SoC design that includes a processor core, memory, and peripheral circuits, the system may dynamically allocate more computing resources to the verification task of the processor core based on the complexity of each part.

[0100] The implementation of parallel computing adopts a hybrid programming model of MPI (Message Passing Interface) and OpenMP. MPI is used for communication between different computing nodes, while OpenMP is used for multi-threaded parallelism within a node. This hybrid model fully utilizes the hardware characteristics of modern high-performance computing clusters. At the same time, the system has designed a special data synchronization mechanism to ensure data consistency between different computing nodes and avoid data inconsistency problems caused by parallel computing.

[0101] After the calculation is completed, the system uses a hierarchical data integration method to combine the results of each subtask. This process needs to consider the mutual influence between models at different levels to ensure the accuracy and consistency of the final result.

[0102] Based on the integrated data, the system calculates manufacturability indicators, including process window, critical dimension variation, and yield prediction. For example, the system may predict that under given process conditions, the chip yield is 98.5%, with a critical path timing margin of 15ps.

[0103] Based on these manufacturability indicators, the system further identifies potential manufacturing defects. A multi-scale defect recognition algorithm is used here, with different recognition methods for different types of defects.

[0104] For the identification of lithography hotspots, the system uses a lithography simulation method assisted by machine learning. First, a fast lithography model is used to perform a preliminary scan of the entire chip to identify areas where problems may exist. Then, high-precision lithography simulation is applied to these areas, combined with a convolutional neural network model trained with a large amount of historical data to accurately identify and classify lithography hotspots. For example, the system may identify 200 potential lithography hotspots in a 5nm process chip design and classify them into different types such as bridges and disconnections.

[0105] Metal bridging detection uses a method based on electric field simulation. The system simulates the three-dimensional electric field distribution of the metal layer and uses an adaptive threshold algorithm to identify areas with high electric field strength. Then, combined with the layout design rule check results, the metal spacing and metal density are comprehensively evaluated to determine whether there is a bridging risk. For example, in a high-density interconnect area, the system may find that the electric field strength between two adjacent metal lines exceeds the safety threshold, warning of possible bridging risks.

[0106] The analysis of via missing uses a multi-level approach. At the chip level, the system uses topology analysis algorithms to check the connectivity of critical signal paths. At the cell level, pattern matching techniques are applied to identify high-risk layout structures. At the device level, the failure probability during via formation is evaluated by considering local stress distribution and material properties. Through this multi-level analysis, the system can comprehensively evaluate the risk of via missing and provide precise location information.

[0107] Based on the potential manufacturing defects identified, the system automatically generates optimization suggestions using an intelligent optimization system that includes a layout modification solution generator and a process parameter adjustment solution generator.

[0108] The layout modification generator uses rule-based and heuristic algorithms to generate preliminary layout modification suggestions. Then, a genetic algorithm is introduced to automatically explore multiple layout modification solutions while keeping the circuit function unchanged. For example, for an identified lithography hotspot, the system may generate multiple alternative solutions, such as adjusting line width, adding auxiliary graphics, changing the graphic direction, etc.

[0109] The process parameter adjustment scheme generator uses machine learning technology to establish a process-defect correlation model. This model is based on a large amount of historical data and can accurately predict the impact of process parameter changes on defects. Then, the system uses the Bayesian optimization algorithm to automatically search for the optimal process parameter combination while meeting the process window constraints. For example, the system may recommend increasing the exposure dose by 2% and extending the etching time by 1 second to reduce the probability of a certain type of defect.

[0110] The generated layout modification plan and process parameter adjustment plan are organically combined through the optimization suggestion integration module to form a comprehensive optimization suggestion. This process takes into account the mutual influence between different optimization measures to ensure that the final optimization plan is the global optimal. For example, some layout modifications may affect the process window, and the system will weigh these factors and give a balanced solution.

[0111] The system conducts rapid simulation verification on the generated comprehensive optimization suggestions to evaluate their effectiveness. This process uses simplified models and intelligent sampling technology to provide a preliminary evaluation of the optimization effect in a short time. If the verification results do not meet the preset manufacturability requirements, the system will iteratively optimize the comprehensive optimization suggestions based on the verification results until the requirements are met.

[0112] The final comprehensive optimization suggestions are applied to the integrated circuit design to generate optimized design data. The system then re-predicts the manufacturability of these optimized design data to verify the optimization effect. This closed-loop process ensures the effectiveness and reliability of the optimization.

[0113] Through this series of closely linked steps, the integrated circuit manufacturability verification system software can comprehensively and accurately evaluate the manufacturability of the chip design and provide effective optimization suggestions.

[0114] Figure 2 FIG. 1 is a schematic diagram of the structure of the system software design system for integrated circuit manufacturability verification according to an embodiment of the present invention. Figure 2 As shown, the system comprises:

[0115] The first unit is used to receive integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters; based on the integrated circuit design data, construct a multi-level verification model, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; perform parallel computing processing on the multi-level verification model to generate a manufacturability prediction result, wherein the parallel computing processing adopts a distributed computing architecture to distribute the verification task to multiple computing nodes;

[0116] The second unit is used to identify potential manufacturing defects according to the manufacturability prediction result, wherein the potential manufacturing defects include lithography hot spots, metal bridges, and via missing; based on the potential manufacturing defects, automatically generate optimization suggestions, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; apply the optimization suggestions to the integrated circuit design data to generate optimized design data; iteratively verify the optimized design data until preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability, and performance parameters;

[0117] The third unit is used to generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and a final manufacturability evaluation result; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; and transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

[0118] According to a third aspect of the embodiments of the present invention,

[0119] An electronic device is provided, comprising:

[0120] processor;

[0121] a memory for storing processor-executable instructions;

[0122] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0123] A fourth aspect of the embodiments of the present invention is:

[0124] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0125] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system software design method for integrated circuit manufacturability verification, characterized in that: include: Receiving integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters; Based on the integrated circuit design data, a multi-level verification model is constructed, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; parallel computing is performed on the multi-level verification model to generate a manufacturability prediction result, wherein the parallel computing uses a distributed computing architecture to distribute the verification task to multiple computing nodes; According to the manufacturability prediction results, potential manufacturing defects are identified, wherein the potential manufacturing defects include photolithography hot spots, metal bridges, and via missing; based on the potential manufacturing defects, optimization suggestions are automatically generated, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; Applying the optimization suggestion to the integrated circuit design data to generate optimized design data; Iteratively verifying the optimized design data until the preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability and performance parameters; Generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and final manufacturability evaluation results; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

2. The method according to claim 1, characterized in that Based on the integrated circuit design data, construct a multi-level verification model, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; The multi-level verification model is processed in parallel to generate a manufacturability prediction result, including: Receiving integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters; A multi-level verification model is constructed based on the integrated circuit design data, and the multi-level verification model includes a device-level model, a unit-level model and a chip-level model; wherein, when constructing the device-level model, a TCAD tool is used to combine process parameters and device geometry information, and quantum effects and stress effects are considered to construct an accurate device physical model; when constructing the unit-level model, a sensitivity analysis method is used to identify key parameters and establish a parameterized model; when constructing the chip-level model, a hierarchical wiring model and a timing model are used, combined with statistical static timing analysis technology, to establish a performance and reliability model within the entire chip.

3. The method according to claim 2, characterized in that The method further comprises: The multi-level verification model is processed in parallel to generate a manufacturability prediction result, wherein the parallel processing includes: Decompose the verification task into multiple independent subtasks, adopt the regional decomposition strategy for device-level models and unit-level models, and adopt the functional module decomposition strategy for chip-level models; use the dynamic load balancing algorithm to adjust the task allocation in real time according to the computational complexity and data dependency of each subtask; A hybrid programming model of MPI and OpenMP is used to implement parallel computing, where MPI is used for inter-node communication and OpenMP is used for multi-threaded parallelism within a node. A data synchronization mechanism is designed to ensure data consistency between different computing nodes, and a hierarchical data integration method is used to combine the results of each subtask. Based on the integrated data, manufacturability indicators are calculated, and the manufacturability indicators include process window, critical dimension variation and yield prediction; based on the manufacturability indicators, potential manufacturing defects are identified and optimization suggestions are generated; the optimization suggestions are applied to the integrated circuit design data to generate optimized design data; the steps of constructing a multi-level verification model, parallel computing and calculating manufacturability indicators are repeatedly executed on the optimized design data until the preset manufacturability requirements are met.

4. The method according to claim 1, characterized in that: According to the manufacturability prediction result, identifying potential manufacturing defects, wherein the potential manufacturing defects include photolithography hot spots, metal bridges, and via missing; Based on the potential manufacturing defects, optimization suggestions are automatically generated, and the optimization suggestions include layout modification solutions and process parameter adjustment solutions including: Receiving the manufacturability prediction results of the integrated circuit; identifying potential manufacturing defects using a multi-scale defect recognition algorithm, wherein the multi-scale defect recognition algorithm includes: using a machine learning-assisted lithography simulation method to identify lithography hotspots, wherein a fast lithography model is used to perform a preliminary scan of the entire chip, and high-precision lithography simulation is applied to areas where problems may exist, and a convolutional neural network model trained with a large amount of historical data is combined to accurately identify and classify lithography hotspots; using an electric field simulation-based method to detect metal bridging, wherein a three-dimensional electric field distribution simulation is performed on the metal layer, an adaptive threshold algorithm is used to identify high electric field intensity areas, and metal spacing and metal density are comprehensively evaluated in combination with layout design rule check results; A multi-level approach is applied to analyze via missingness, including using topology analysis algorithms at the chip level to check the connectivity of critical signal paths, applying pattern matching techniques at the cell level to identify high-risk layout structures, and considering local stress distribution and material properties at the device level to evaluate the failure probability during via formation.

5. The method according to claim 4, characterized in that The method further comprises: Based on the identified potential manufacturing defects, automatically generate optimization suggestions using an intelligent optimization system, the intelligent optimization system including a layout modification solution generator and a process parameter adjustment solution generator; The layout modification scheme generator generates layout modification suggestions using rule-based and heuristic algorithms, and introduces a genetic algorithm to automatically explore multiple layout modification schemes while keeping the circuit function unchanged; The process parameter adjustment scheme generator uses machine learning technology to establish a process-defect correlation model, and uses a Bayesian optimization algorithm to automatically search for the optimal process parameter combination under the condition of satisfying the process window constraints; The optimization suggestion integration module combines the layout modification plan and the process parameter adjustment plan to generate comprehensive optimization suggestions, which considers the mutual influence between different optimization measures to ensure that the final optimization plan is the global optimal one. Rapidly simulate and verify the generated comprehensive optimization suggestions to evaluate their effectiveness; According to the results of rapid simulation verification, the comprehensive optimization suggestions are iteratively optimized until the preset manufacturability requirements are met; Apply the final comprehensive optimization suggestions to the integrated circuit design to generate optimized integrated circuit design data; The manufacturability prediction is re-performed on the optimized integrated circuit design data to verify the optimization effect.

6. A system software design system for integrated circuit manufacturability verification, used to implement the method according to any one of claims 1 to 5, characterized in that: include: A first unit is used to receive integrated circuit design data, wherein the integrated circuit design data includes layout data and process parameters; Based on the integrated circuit design data, a multi-level verification model is constructed, wherein the multi-level verification model includes a device-level model, a unit-level model, and a chip-level model; parallel computing is performed on the multi-level verification model to generate a manufacturability prediction result, wherein the parallel computing uses a distributed computing architecture to distribute the verification task to multiple computing nodes; The second unit is used to identify potential manufacturing defects according to the manufacturability prediction result, wherein the potential manufacturing defects include lithography hot spots, metal bridges and via missing; based on the potential manufacturing defects, automatically generate optimization suggestions, wherein the optimization suggestions include layout modification solutions and process parameter adjustment solutions; Applying the optimization suggestion to the integrated circuit design data to generate optimized design data; Iteratively verifying the optimized design data until the preset manufacturability indicators are met, wherein the manufacturability indicators include yield rate, reliability and performance parameters; The third unit is used to generate a manufacturability verification report, which includes a defect distribution map, optimization effect analysis and a final manufacturability evaluation result; integrate the manufacturability verification report with the optimized design data to form an integrated circuit manufacturing data package; and transmit the integrated circuit manufacturing data package to a manufacturing execution system for guiding the actual manufacturing process of the integrated circuit.

7. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 5.

8. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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