Data driver and control method thereof

Abstract

The present invention relates to a data driver and a control method thereof, in which a position of a pixel to which pixel data is written and a gradation change amount of the pixel data are determined, and a bias current applied to an output buffer is changed according to the position of the pixel and the gradation change amount of the pixel data, a data voltage corresponding to the pixel data is output from the output buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0101243, filed on August 2, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The invention relates to a data driver and a control method thereof. Background Art

[0004] A display device includes a data driver that provides data voltages to pixels on a display panel. Various studies are being conducted to reduce power consumption of the data driver. A method is needed to further reduce power consumption without reducing image quality of the display device. Summary of the invention

[0005] The object of the present invention is to solve the above-mentioned needs and / or problems.

[0006] The present invention provides a data driver and a control method thereof, which can reduce power consumption without reducing the image quality of a display device.

[0007] Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to one embodiment of the present invention, a data driver includes: an output buffer configured to output a data voltage corresponding to pixel data; and a bias current regulator configured to adjust a bias current applied to the output buffer according to a position of a pixel to be charged with the data voltage, and to adjust the bias current according to a swing width of the data voltage.

[0009] The data driver may further include a data comparator configured to compare grayscale differences of the pixel data varying with time.

[0010] The bias current regulator may change the bias current based on grayscale difference data input from the data comparator.

[0011] According to another embodiment of the present invention, a data driver includes: a first latch array, configured to latch pixel data; a second latch array, configured to latch the pixel data output from the first latch array; a digital-to-analog converter, configured to convert the pixel data output from the second latch array into a data voltage; an output buffer, configured to output the data voltage from the digital-to-analog converter; a data comparator, connected to the first latch array and the second latch array, and configured to compare first pixel data stored in the first latch array and second pixel data stored in the second latch array; and a bias current regulator, connected between the data comparator and the output buffer, and configured to change the bias current applied to the output buffer.

[0012] According to an embodiment of the present invention, the display driver can change the bias current applied to the output buffer of the data driver according to the position of the pixel, and also change the bias current according to the change of the swing width of the data voltage based on the grayscale difference of the pixel data, thereby improving the uniformity of image quality on the screen and minimizing power consumption.

[0013] The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0016] Figure 2 is a block diagram showing a configuration of a data driving section according to an embodiment of the present invention;

[0017] Figure 3 is a flow chart showing a bias current control method of a data driving unit according to an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram showing an example of a method for controlling a bias current based on a pixel position according to an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram showing an example of a method for controlling a bias current based on a grayscale difference of pixel data according to an embodiment of the present invention;

[0020] Figure 6 and Figure 7is a circuit diagram showing a grayscale difference-based bias current control circuit of a bias current regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] According to the embodiments described below and with reference to the accompanying drawings, the advantages and features of the present invention and their implementation methods will be more clearly understood. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms. However, these embodiments will make the disclosure of the present invention complete and allow those skilled in the art to fully understand the scope of the present invention. The present invention is limited only to the scope of the appended claims.

[0022] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments of the present invention are merely examples, and the present invention is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, when describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0023] Terms such as “including,” “comprising,” and “having” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may also include the plural unless explicitly stated otherwise.

[0024] Even if not explicitly stated, components are referred to as including ordinary margins of error.

[0025] When describing the position or interconnection relationship between two components, such as "on", "over", "below", "adjacent", "connected or coupled to", "crossing", "intersecting", etc., unless "immediately" or "directly" is used, one or more other components may be inserted between the two.

[0026] When describing a temporal relationship, such as "after", "after", "next", "before", etc., unless "immediately" or "directly" is used, the time may be discontinuous.

[0027] The terms “first”, “second”, etc. are used to distinguish elements from each other, but the function or structure of a component is not limited by an ordinal number preceding the component or the name of the component.

[0028] The following embodiments may be partially or completely combined or combined with each other, and may be connected and operated in various ways in technology. The embodiments may be performed independently of each other or in association with each other.

[0029] A transistor is a three-electrode element including a gate, a source and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction that flows from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. In the following description, the source and drain of a transistor are referred to as the first electrode and the second electrode.

[0030] In the following description of the embodiment, a pixel located at a greater distance from the data driving part is referred to as a “far pixel”, and a pixel closer to the data driving part is referred to as a “near pixel.” The near pixel may be referred to as a first pixel, and the far pixel may be referred to as a second pixel.

[0031] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0033] Reference Figure 1 , a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing source data into pixels in the display panel 100 .

[0034] The substrate in the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel 100 may be, but is not limited to, a panel having a rectangular structure having a length in a first direction X, a width in a second direction Y, and a thickness in a third direction Z.

[0035] In the case of a liquid crystal display device, a backlight unit (BLU) may be disposed under the display panel 100. In the case of a self-luminous display device such as an electroluminescent display device, a separate light source such as a backlight unit is not required.

[0036] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 103 crossing the data lines 102 , and pixels 101 connected to the data lines 102 and the gate lines 103 .

[0037] The pixel array includes a plurality of pixel rows. Each pixel row includes a row of pixels arranged in the pixel array of the display panel 100 along a first direction X. The pixels located on a row of pixels share a gate line 103. A column of sub-pixels arranged along a second direction Y share the same data line 102. One horizontal period may be a time obtained by dividing one frame period by the total number of pixel rows.

[0038] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel for presenting colors. Each pixel can also include a white sub-pixel. In a liquid crystal display device, a pixel includes a liquid crystal cell. In an electroluminescent display device, a pixel includes a light-emitting element, such as an organic light-emitting diode (OLED). Each sub-pixel includes a pixel circuit for driving a liquid crystal cell or a light-emitting element.

[0039] The display panel driving circuit writes pixel data (or source data) of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driving part 110 and a gate driving part 120 that convert pixel data into data voltages.

[0040] The display panel driving circuit may further include a touch sensor driving part for driving the touch sensor. Figure 1 The touch sensor driving part is omitted in FIG. The data driving part 110 and the touch sensor driving part may be integrated together in an integrated circuit (IC) of a data driver.

[0041] The data driving part 110 receives pixel data of an input image provided as a digital signal from the timing controller 130 and outputs a data voltage. The data driving part 110 may be referred to as a data driver. The data driving part 110 may convert the input digital signal into a grayscale voltage (or a gamma compensation voltage) using a digital-to-analog converter (hereinafter referred to as a DAC) and output the data voltage. For a liquid crystal display, the data driving part 110 may periodically reverse the polarity of the data voltage and output the data voltage in units of one horizontal period or two horizontal periods under the control of the timing controller 130.

[0042] The data driving section 110 may determine the position of a pixel where pixel data is written, a grayscale change amount (or grayscale difference) of the pixel data, and change a bias current applied to an output buffer based on the position of the pixel and the grayscale change amount of the pixel data.

[0043] The circuit of the gate driving unit 120 may be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a portion of the gate driving unit 120 may be disposed in the display area AA. The gate driving unit 120 may be integrated into an independent IC of a gate driver and electrically connected to the gate line 103 of the display panel 100.

[0044] The gate driving part 120 sequentially outputs gate pulses (or scan pulses) to the gate lines 103 under the control of the timing controller 130. The gate driving part 120 may shift the gate pulses using a shift register, thereby sequentially supplying the gate pulses to the gate lines 103.

[0045] The display device may further include a power supply which is omitted in the drawing. The power supply receives an input voltage applied from the host system 200 and outputs a constant voltage required to drive the pixels 101 of the display panel 100 and the display panel driving circuit.

[0046] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from an external host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock. By counting the data enable signal DE, the vertical period and the horizontal period can be known, so the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The period of the vertical synchronization signal Vsync is one frame period. The period of the horizontal synchronization signal Hsync and the data enable signal DE is one horizontal period (1H). The timing controller 130 can control the operation timing of the display panel drive circuits 110 and 120 based on the timing signals Vsync, HSync, and DE received from the host system 200.

[0047] The host system 200 may scale an image signal from a video source to match a resolution of the display panel 100 , and may transmit the image signal to the timing controller 130 together with a timing control signal.

[0048] Figure 2 is a block diagram showing a configuration of a data driving section according to an embodiment of the present invention.

[0049] refer to Figure 2 The data driving unit 110 may include a receiver 112, a logic controller 300, a shift register 113, a first latch array 114, a second latch array 115, a digital-to-analog converter (DAC) 116, an output buffer 117, a data comparator 510 and a bias current regulator 520.

[0050] The timing controller 130 may convert the clock and data into a low voltage differential signal and transmit the differential signal to the data driving section 110 through a high-speed serial interface. The receiver 112 receives the data DATA transmitted serially from the timing controller 130. The receiver 112 recovers the clock from the data DATA, samples the control data and the pixel data of the input image from the data DATA using the recovered clock, and provides them to the logic controller 300.

[0051] The logic controller 300 may send the pixel data of the input image provided by the receiver 112 to the shift register 113, and may control the output timing of the first latch array 114 and the second latch array 115 using the recovered clock and control data. The shift register 113, the first latch array 114, and the second latch array 115 convert the serial mode data into the parallel mode data. The shift register 113 sequentially outputs the pixel data input from the logic controller 300 to the latches in the first latch array 114. The first latch array 114 sequentially samples the pixel data of the input image input through the shift register 113 in response to the clock input from the logic controller 300, and when the pixel data has been latched in all latches, the latched pixel data is simultaneously output to the latches in the second latch array 115. The second latch array 115 latches the pixel data simultaneously received from the latches in the first latch array 114 , and simultaneously outputs the latched pixel data to the DAC 116 in response to an output enable signal from the logic controller 300 .

[0052] The DAC 116 converts the pixel data input as a digital signal from the second latch array 115 into a gamma compensation voltage to output a data voltage having a voltage level corresponding to the grayscale value of the pixel data. The data voltage output from the DAC 116 is output through the output buffer 117. The output buffer 117 can be Figure 7 The buffer circuit 74 shown in FIG. outputs the data voltage. The output buffer 117 may include (but is not limited to) Figure 7 The current regulator 526 and the buffer circuit 74 are shown in FIG.

[0053] A level shifter (not shown) may be provided between the second latch array 115 and the DAC 116. The level shifter may shift the voltage level of the output data from the second latch array 115 to an operable voltage of the DAC 116. A multiplexer may be connected to the output terminal of the output buffer 117. The multiplexer may selectively connect the data voltage output through the output buffer 117 to the data line. The output terminal of the data driving unit 110 may be controlled by the multiplexer to be in a high impedance state.

[0054] The data comparator 510 can compare the grayscale value changes on the time axis for the pixel data input to the data driving unit 110 to determine the grayscale difference (or grayscale change amount) between the pixel data. For example, the data comparator 510 can compare the pixel data written in the nth pixel row selected by the gate signal in the nth horizontal period (where n is a natural number) and the pixel data written in the n+1th pixel row selected by the gate signal in the n+1th horizontal period to determine the grayscale difference (or grayscale change amount) between the pixel data.

[0055] The data comparator 510 may compare the first pixel data of the n+1th pixel row (where n is a natural number) stored in the first latch array 114 with the second pixel data of the nth pixel row stored in the second latch array 115. The data comparator 510 outputs data related to the grayscale difference, which represents the grayscale change amount between the first pixel data and the second pixel data and the swing width of the data voltage. When comparing the first pixel data and the second pixel data, the data comparator 510 may compare the most significant bit (MSB) of the pixel data, such as the two most significant bits. The data voltage of the first pixel data and the data voltage of the second pixel data may be sequentially applied to the same data line through the same output channel. Therefore, when a grayscale difference is generated between the first pixel data and the second pixel data, the data voltage applied to the data line changes to generate a swing width. The swing width of the data voltage may increase in proportion to the grayscale difference of the pixel data.

[0056] The nth pixel row includes a plurality of pixels in which pixel data is written in the nth horizontal period. The n+1th pixel row includes a plurality of pixels in which pixel data is written in the n+1th horizontal period. After a data voltage corresponding to the data of the nth pixel row is applied to the data line, a data voltage corresponding to the data of the n+1th pixel row is applied. As the grayscale difference between the pixel data of the nth pixel row and the n+1th pixel row increases, the swing width of the data voltage applied to the data line increases.

[0057] The bias current regulator 520 may change the bias current applied to the output buffer 117 according to the distance between the data driving unit 110 and the pixel, and may change the bias current applied to the output buffer 117 according to the grayscale difference of the pixel data in response to the grayscale difference data input from the data comparator 510. The higher the bias current, the higher the slew rate of the data voltage, and the lower the bias current, the lower the slew rate of the data voltage. When the slew rate of the data voltage is low, the current flowing in the data driving unit 110 is reduced, which can reduce power consumption and reduce the heat generated.

[0058] The bias current regulator 520 or the logic controller 300 may determine the position of the pixel where the pixel data is written based on counting a timing signal (such as a clock) received by the receiver 112 or counting grayscale difference data input from the data comparator 510. The bias current regulator 520 may change the bias current Ib applied to the output buffer 117 according to the distance between the data driving part 110 and the pixel.

[0059] The bias current regulator 520 may reduce the bias current applied to the output buffer 117 when the data voltage to be charged in the near pixel is output through the output buffer 117, compared to the bias current applied to the output buffer 117 when the data voltage to be charged in the far pixel is output through the output buffer 117. As a result, during a scanning period in which pixel data is written to the near pixel, the current flowing in the data driving part 110 is reduced, so that power consumption can be reduced, and the generated heat can also be reduced.

[0060] Far pixels with large RC delay and large IR drop have lower data voltage charge, while near pixels with small RC delay and small IR drop have higher data voltage charge. When a difference in the charging rate of the data voltage of the pixel 101 is generated according to the position of the display panel 100, the brightness uniformity of the screen may decrease. The bias current regulator 520 can adjust the bias current applied to the output buffer 117 to be lower for the near pixel, and adjust the bias current applied to the output buffer 117 to be lower when the grayscale difference of the pixel data is small, thereby controlling the charging rate of the data voltage in all pixels in the same manner, and controlling the charging rate of the data voltage in all pixels with the same grayscale difference in the same manner, thereby improving image quality and reducing power consumption.

[0061] Figure 3 1 is a flow chart showing a bias current control method of a data driver according to an embodiment of the present invention. The bias current control method may be performed by the data comparator 510, the bias current regulator 520, and the output buffer 117.

[0062] Reference Figure 3 When pixel data is input to the data driving unit 110 (S1), the data driving unit 110 uses the logic controller 300 or the bias current regulator 520 to determine the position of the pixel where the pixel data is written in units of pixel rows (S2), and uses the data comparator 510 to determine the grayscale difference of the pixel data (S3).

[0063] The bias current regulator 520 determines the bias current value P based on the position of the pixel in units of pixel rows or pixel blocks, regardless of the grayscale difference of the pixel data (S4). The bias current regulator 520 determines the bias current value S based on the grayscale difference based on the grayscale difference of the pixel data in units of pixel rows or pixel blocks (S5). The bias current value S based on the grayscale difference can change according to the grayscale difference data output by the data comparator 510. The bias current value P based on the position can be referred to as the first current value, and the bias current value S based on the grayscale difference can be referred to as the second current value. The pixel block can include two or more pixel rows. The bias current value S based on the grayscale difference can be referred to as a scaling ratio, an increase / decrease ratio, an adjustment coefficient, etc.

[0064] The bias current regulator 520 can determine the final bias current value (S6) by multiplying the position-based bias current value P by the grayscale difference-based bias current value S. For example, assuming that the default current value is 100%, if it is determined that P=50% and S=50%, the bias current to be applied to the output buffer 117 will be adjusted to: 100%*50%*50%=25%.

[0065] The default current value may be determined according to the power option data PWRC sent by the timing controller 130 to the data driving section 110, and the default current value may be applied to all pixels at the same value regardless of the position or grayscale difference of the pixels. The power option data PWRC may be encoded in the control data sent to the data driving section 110. The default current value may be changed by the logic value of the power option data PWRC. For example, assuming that the default current value is reduced to 50% by the power option data PWRC, if P=50% and S=50%, the bias current applied to the output buffer 117 is reduced to: 50%*50%*50%=12.5%. The logic controller 300 may set the bias current in response to the power option data PWRC in units of one frame period.

[0066] The bias current applied to the output buffer 117 may vary with the position between the data driving unit 110 and the pixel, and may also vary with the grayscale difference of the pixel data. As the distance from the data driving unit 110 to the pixel position is closer and the grayscale difference of the pixel data is smaller, the bias current applied to the buffer 117 is reduced, thereby improving the effect of reducing power consumption.

[0067] Figure 4 is a schematic diagram showing an example of a method for controlling a bias current based on a pixel position according to an embodiment of the present invention. Figure 4 , the curve on the left is a waveform of a data voltage when a data voltage having the same grayscale difference is applied to pixels at different distances from the data driving part 110. In the curve graph on the left, the horizontal axis represents time and the vertical axis represents data voltage. Figure 4 , the right curve represents the bias current Ib that varies with the position of the pixel at different distances from the data driving unit 110. In the right curve graph, the horizontal axis represents the bias current, and the vertical axis represents the distance between the data driving unit 110 and the pixel.

[0068] refer to Figure 4, if the bias current applied to the output buffer is the same for all pixels regardless of the position of the pixel, the data voltage charged in the near pixel quickly reaches the target voltage due to the high slew rate of the data voltage applied to the near pixel, as shown by the dotted line, and the data voltage charged in the far pixel reaches the target voltage later due to the low slew rate of the data voltage applied to the far pixel. Generally, the data voltage applied to the pixel in the last pixel row farthest from the data driving unit 110 has the lowest slew rate.

[0069] The bias current regulator 520 reduces the bias current applied to the output buffer 117 as the distance between the data driving part 110 and the pixel 101 decreases, thereby regulating the slew rate to the same or similar level for all pixels on the display panel 100 as shown by the solid line.

[0070] The near pixels in the first pixel row closest to the data driving unit 110 can be scanned by gate signals during the first horizontal period to charge the data voltage of the pixel data. The far pixels in the mth pixel row (where m is a natural number greater than or equal to 2) farthest from the data driving unit 110 can be scanned by gate signals during the mth horizontal period to charge the data voltage of the pixel data. The bias current regulator 520 can set the bias current to be applied to the output buffer to a low value during the first horizontal period, and increase the bias current during the mth horizontal period. Through this pixel position-based bias current control method, the bias current applied to the output buffer 117 can be gradually or stepwise increased as time passes during a frame period. As a result, as the distance between the data driving unit 110 and the pixel decreases, the bias current applied to the output buffer 117 can be reduced, so for all pixels on the display panel 100, the slew rate can be controlled to the same or similar level as shown by the solid line.

[0071] For all pixels, the slew rate of the data voltage is controlled to be the same or similar level as the slew rate of the pixel having the lowest data voltage slew rate, thereby improving the brightness uniformity of the image reproduced on the display panel 100. In addition, when the data voltage to be charged in the near pixel is output, the bias current applied to the output buffer 117 is reduced, thereby reducing the power consumption and heat generation of the data driving part 110.

[0072] Figure 5 FIG. 1 is a schematic diagram showing an example of a method for controlling a bias current based on a grayscale difference of pixel data according to an embodiment of the present invention. Figure 5 , the top curve represents the data voltage Vdata when the pixel data has a larger grayscale difference ΔV1, and the bottom curve represents the data voltage Vdata when the pixel data has a smaller grayscale difference ΔV2.

[0073] Reference Figure 5, when the pixel data has a smaller gray value change and when the pixel data on the time axis has a smaller gray value than the previous gray value, the bias current applied to the output buffer 117 becomes smaller than when the pixel data has a larger gray value change. Therefore, when the gray value of the pixel data is smaller, the bias current may become smaller, and the slew rate of the data voltage output from the data driving part 110 may become lower.

[0074] When the grayscale difference ΔV1 of the pixel data is large, the swing width of the data voltage Vdata charged into the pixel increases. When the swing width of the data voltage Vdata is large, the slew rate of the data voltage Vdata charged into the pixel can be increased by increasing the bias current flowing into the output buffer 117. On the other hand, although the bias current flowing into the output buffer 117 decreases when the swing width of the data voltage Vdata is small, the slew rate does not decrease until the data voltage Vdata charged into the pixel reaches the target voltage, thereby reducing power consumption.

[0075] When the swing width of the data voltage Vdata is small, the bias current regulator 520 may reduce the bias current flowing into the output buffer 117. The slew rate of the data voltage Vdata when the swing width of the data voltage Vdata is small may be controlled to be the same as or similar to the slew rate of the data voltage Vdata when the swing width of the data voltage Vdata is large.

[0076] Figure 6 and Figure 7 1 is a circuit diagram showing a bias current regulator according to one embodiment of the present invention. Figure 6 In the figure, the circuit diagram on the left is the circuit of the decoder, and the table on the right is the truth table of the decoder.

[0077] refer to Figure 6 and Figure 7 , the bias current regulator 520 may include a decoder 522 , a reference current generator 524 , and a current regulator 526 .

[0078] The data comparator 510 may output two bits A and B of grayscale difference data indicating the grayscale difference of the pixel data. For example, but not limited to, when the pixel data has a grayscale difference of 0 to 64 or less, the bits A and B of the grayscale difference data are represented as AB=00, when the pixel data has a grayscale difference of 65 to 128, the bits A and B of the grayscale difference data are represented as AB=01, when the pixel data has a grayscale difference of 129 to 192, the bits A and B of the grayscale difference data are represented as AB=10, and when the pixel data has a grayscale difference of 193 to 255, the bits A and B of the grayscale difference data are represented as AB=11. The decoder 522 may be, but not limited to, a 2*4 decoder for receiving two bits A and B of grayscale difference data and outputting 4 bits of current control data, such as Figure 6 shown.

[0079] The 2*4 decoder may include first and second inverters INV1 and INV2 and first to fourth AND gates AND1 to AND4. The first inverter INV1 inverts the first input bit A and provides it to the first and second AND gates AND1 and AND2. The second inverter INV2 inverts the second input bit B and provides it to the first and third AND gates AND1 and AND3.

[0080] The first AND gate AND1 outputs the result of the logical AND operation of the inverted first input bit A and the inverted second input bit B. When A=0 and B=0, the output value D1 of the first AND gate AND1 is a logic high (HIGH=1), otherwise it is a logic low (LOW=0). The second AND gate AND2 outputs the result of the logical AND operation of the inverted first input bit A and the non-inverted second input bit B. If A=0 and B=1, the output value D2 of the second AND gate AND2 is a logic high (HIGH=1), otherwise it is a logic low (LOW=0). The third AND gate AND3 outputs the result of the logical AND operation of the non-inverted first input bit A and the inverted second input bit B. If A=1 and B=0, the output value D3 of the third AND gate AND3 is a logic high (HIGH=1), otherwise it is a logic low (LOW=0). The fourth AND gate AND4 outputs the result of the logical AND operation of the non-inverted first input bit A and the non-inverted second input bit B. If A=1 and B=1, the output value D4 of the fourth AND gate AND4 is logic high (HIGH=1), otherwise it is logic low (LOW=0).

[0081] The reference current generator 524 and the current regulator 526 may constitute a current mirror circuit. The reference current generator 524 includes a constant current source and a reference transistor Mr provided between a VDD node 71 and a gate node 72, and a driving voltage VDD is applied to the VDD node 71 to generate a reference current Iref. The reference transistor Mr includes a first electrode connected to a GND node to which a ground voltage GND is applied, a gate, and a second electrode connected to the gate node 72.

[0082] The current regulator 526 may include a plurality of transistors M01 to M04 and M11 to M14, which selectively output bias currents having different current values ​​obtained according to the reference current Iref. The values ​​of the channel ratios W / L of the transistors M01 to M04 and M11 to M14 may be set to be the same as or different from the channel ratios W / L of the reference transistors.

[0083] The 1-1 transistor M01 to the 1-4 transistor M04 may generate bias currents Ib1 to Ib4 that are duplicated by the reference current Iref. The 1-1 transistor M01 includes a first electrode connected to the GND node, a gate connected to the gate node 72, and a second electrode connected to the first electrode of the 2-1 transistor M11. The 1-2 transistor M02 includes a first electrode connected to the GND node, a gate connected to the gate node 72, and a second electrode connected to the first electrode of the 2-2 transistor M12. The 1-3 transistor M03 includes a first electrode connected to the GND node, a gate connected to the gate node 72, and a second electrode connected to the first electrode of the 2-3 transistor M13. The 1-4 transistor M04 includes a first electrode connected to the GND node, a gate connected to the gate node 72, and a second electrode connected to the first electrode of the 2-4 transistor M14.

[0084] The 2-1st to 2-4th transistors M11 to M14 are connected between the 1-1st to 1-4th transistors M01 to M04 and the buffer circuit 74 to adjust the bias currents Ib1 to Ib4 in response to the output data D1 to D4 of the decoder 522. The output data D1 to D4 from the decoder 522 may be multiplied by the bias current value P based on the position.

[0085] When the voltage D1 is a gate-on voltage, the 2-1 transistor M11 is turned on to allow the first bias current Ib1 to flow, and when the voltage D1 is a gate-off voltage, the 2-1 transistor M11 is turned off. The 2-1 transistor M11 includes a first electrode connected to the second electrode of the 1-1 transistor M01, a gate to which the voltage D1 is applied, and a second electrode connected to the buffer circuit 74. The buffer circuit 74 outputs the data voltage Vdata output from the DAC 116 to the output terminal of the data driving part 110. The slew rate of the data voltage Vdata output from the buffer circuit 74 can be controlled by the bias currents Ib1 to Ib4, and the bias current regulator 520 changes the bias currents Ib1 to Ib4 based on the pixel position and the grayscale difference data of the pixel data.

[0086] When the voltage D2 is a gate-on voltage, the 2-2 transistor M12 is turned on to allow the second bias current Ib2 to flow, and when the voltage D2 is a gate-off voltage, the 2-2 transistor M12 is turned off. The 2-2 transistor M12 includes a first electrode connected to the second electrode of the 1-2 transistor M02, a gate to which the voltage D2 is applied, and a second electrode connected to the buffer circuit 74.

[0087] When the voltage D3 is a gate-on voltage, the 2-3rd transistor M13 is turned on to allow the third bias current Ib3 to flow, and when the voltage D3 is a gate-off voltage, the 2-3rd transistor M13 is turned off. The 2-3rd transistor M13 includes a first electrode connected to the second electrode of the 1-3rd transistor M03, a gate to which the voltage D3 is applied, and a second electrode connected to the buffer circuit 74.

[0088] When the voltage D4 is a gate-on voltage, the 2-4th transistor M14 is turned on to allow the fourth bias current Ib4 to flow, and when the voltage D4 is a gate-off voltage, the 2-4th transistor M14 is turned off. The 2-4th transistor M14 includes a first electrode connected to the second electrode of the 1-4th transistor M04, a gate to which the voltage D4 is applied, and a second electrode connected to the buffer circuit 74.

[0089] As described above, the values ​​of the output data D1 to D4 from the decoder 522 can be determined according to the grayscale difference between the pixel data, and the current value can be selected according to the output data D1 to D4, thereby changing the bias current. The slew rate of the data voltage Vdata output from the buffer circuit 74 decreases as the bias current becomes lower, and the slew rate of the data voltage Vdata output from the buffer circuit 74 increases as the bias current becomes higher.

[0090] The objects to be achieved by the present invention, means for achieving the objects, and effects of the present invention described above do not define essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present invention.

[0091] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided for illustrative purposes only and are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present invention.

Claims

1. A data driver, comprising: an output buffer configured to output a data voltage corresponding to pixel data; as well as The bias current regulator is configured to regulate the bias current applied to the output buffer according to the position of the pixel to be charged with the data voltage, and to regulate the bias current according to the swing width of the data voltage.

2. The data driver according to claim 1, further comprising: a data comparator configured to compare grayscale differences of the pixel data that vary with time, The bias current regulator is configured to change the bias current based on grayscale difference data input from the data comparator.

3. The data driver according to claim 2, wherein: The bias current is smaller when the pixel data has a smaller grayscale value change than when the pixel data has a larger grayscale value change.

4. The data driver according to claim 2, wherein: The bias current regulator is configured to gradually or stepwise increase the bias current as time passes during a frame period.

5. The data driver according to any one of claims 1 to 4, further comprising: The logic controller is configured to set the bias current in units of one frame period in response to option data received from the outside.

6. A data driver comprising: a first latch array configured to latch pixel data; a second latch array configured to latch the pixel data output from the first latch array; a digital-to-analog converter configured to convert the pixel data output from the second latch array into a data voltage; an output buffer configured to output the data voltage from the digital-to-analog converter; a data comparator connected to the first latch array and the second latch array and configured to compare first pixel data stored in the first latch array with second pixel data stored in the second latch array; as well as A bias current regulator is connected between the data comparator and the output buffer and is configured to change a bias current applied to the output buffer.

7. The data driver according to claim 6, wherein: The first pixel data is pixel data to be written into the pixel in the n+1th pixel row, the second pixel data is pixel data to be written into the pixel in the nth pixel row, n is a natural number, The data comparator is configured to compare two most significant bits of the first pixel data with two most significant bits of the second pixel data to output grayscale difference data indicating a grayscale change amount between the first pixel data and the second pixel data.

8. The data driver according to claim 7, wherein: The bias current regulator is configured to change the bias current in response to the grayscale difference data.

9. The data driver according to claim 7, wherein: The bias current regulator is configured to change the bias current based on a position of a pixel where the pixel data is written and a grayscale difference of the pixel data.

10. A method for controlling a data driver, comprising: Determine the position of the pixel where the pixel data is written; Determining a grayscale change amount of the pixel data; as well as A bias current applied to an output buffer is changed according to a position of the pixel and a grayscale change amount of the pixel data, and a data voltage corresponding to the pixel data is output from the output buffer.

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