Double-layer capacitor and manufacturing method thereof

Abstract

The invention provides a double-layer capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a groove in the insulating layer on the second metal wire to expose the second metal wire; a double-layer capacitor is formed on the insulating layer on the periphery of the groove and in the groove, a part of the surfaces of the second electrode and the third electrode are exposed, and the first electrode is electrically connected with the second metal wire; forming a third dielectric layer to cover the double-layer capacitor, and forming a first through hole to expose the second electrode and the third electrode; forming a second through hole in the insulating layer to expose the first metal wire and the third metal wire; and forming a fourth metal wire to connect the first metal wire and the second electrode and a fifth metal wire to connect the third metal wire and the third electrode. In the invention, the three electrodes of the double-layer capacitor are led out downwards by using the first metal wire, the second metal wire and the third metal wire in the substrate, so that the process integration difficulty is reduced, and the capacitance density and the design freedom degree of the double-layer capacitor can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a double-layer capacitor and a manufacturing method thereof. Background Art

[0002] Capacitors are a common passive component widely used in the field of integrated circuits. In some special applications, capacitors with large unit capacitance are needed to improve product performance, such as storing signals, reducing noise, and reducing coupling. Single-layer capacitors require a large area to obtain large capacitance, which will sacrifice design area. For this reason, double-layer capacitors become the best choice for large capacitance.

[0003] For existing double-layer capacitors, not only can their capacitance density be further improved, but their manufacturing process can also be further optimized. Summary of the invention

[0004] The object of the present invention is to provide a double-layer capacitor and a manufacturing method thereof, so as to improve the capacitance density thereof and optimize the manufacturing process thereof.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a double-layer capacitor, comprising:

[0006] Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate;

[0007] forming a trench in the insulating layer on the second metal line to expose the second metal line;

[0008] A first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode are sequentially conformally formed on the insulating layer around the groove and in the groove to form a double-layer capacitor, and the surface of the third electrode and a portion of the second electrode are exposed, and the first electrode is electrically connected to the second metal line;

[0009] forming a third dielectric layer to cover the double-layer capacitor, and forming a plurality of first through holes in the third dielectric layer on both sides of the second metal line to expose the second electrode and the third electrode respectively;

[0010] Forming a plurality of second through holes in the insulating layer to expose the first metal line and the third metal line respectively;

[0011] The first through hole and the second through hole are used to form a fourth metal wire to connect the first metal wire and the second electrode, and a fifth metal wire to connect the third metal wire and the third electrode.

[0012] Optionally, a dielectric barrier layer is further provided between the first to third metal wires and the insulating layer.

[0013] Optionally, the step of forming the double-layer capacitor includes:

[0014] forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove;

[0015] Performing a patterning process on the first electrode material layer to form an insulating layer where the first electrode covers the inner wall of the trench and the periphery of the trench;

[0016] Conformally forming a first dielectric material layer, a second electrode material layer, a second dielectric material layer and a third electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode;

[0017] Performing a patterning process on the third electrode material layer and the second dielectric material layer to form the third electrode and the second dielectric layer, and exposing the second electrode material layer;

[0018] A patterning process is performed on the second electrode material layer and the first dielectric material layer to form the second electrode and the first dielectric layer, and a portion of the second electrode is exposed.

[0019] Optionally, the material of the first electrode, the second electrode and the third electrode includes one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

[0020] Optionally, the dielectric constants of the first dielectric layer and the second dielectric layer are greater than or equal to 3.9.

[0021] Optionally, a material of the third dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.

[0022] Optionally, the edges of the second electrode and the third electrode form a step shape, the edge of the second electrode is located at the lower step surface, and the edge of the third electrode is located at the upper step surface. A patterning process is performed on the third dielectric layer to synchronously form the first through holes, which are respectively located on both sides of the second metal line, and the first through holes on one side expose the lower step surface, and the through holes on the other side expose the upper step surface.

[0023] Optionally, the step of forming the fourth metal line and the fifth metal line includes:

[0024] Forming a metal material layer to cover the surface of the insulating layer, the surface of the third dielectric layer, and the inner walls of the first through hole and the second through hole;

[0025] A patterning process is performed on the metal material layer to form a fourth metal line connecting the first metal line and the second electrode and a fifth metal line connecting the third metal line and the third electrode.

[0026] Optionally, when the patterning process is performed on the metal material layer, a metal pad is also simultaneously formed on the surface of the insulating layer for connection with an external circuit.

[0027] According to another aspect of the present invention, a double-layer capacitor is provided, comprising:

[0028] substrate;

[0029] First to third metal wires are arranged in the same layer in the substrate;

[0030] an insulating layer, covering the first to third metal wires and having a groove formed in the insulating layer to expose the second metal wire and a plurality of second through holes to expose the first metal wire and the third metal wire respectively;

[0031] A double-layer capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode formed conformally in sequence, wherein the first electrode is electrically connected to the second metal line;

[0032] A third dielectric layer covers the double-layer capacitor, and a plurality of first through holes are formed in the third dielectric layer to expose the second electrode and the third electrode respectively;

[0033] The fourth metal wire and the fifth metal wire utilize the first through hole and the second through hole. The fourth metal wire electrically connects the first metal wire and the second electrode, and the fifth metal wire electrically connects the third metal wire and the third electrode.

[0034] In summary, the present invention forms a groove in the insulating layer on the second metal wire to expose the second metal wire, and forms a double-layer capacitor on the insulating layer in the groove and around the groove, the first electrode of the double-layer capacitor is connected to the second metal wire at the bottom of the groove, the second electrode and the third electrode of the double-layer capacitor are both exposed upward, and then a third dielectric layer is formed to cover the double-layer capacitor, and a first through hole is formed in the third dielectric layer to expose the second electrode and the third electrode respectively, and a fourth metal wire electrically connecting the second electrode and the first metal wire and a fifth metal wire electrically connecting the third electrode and the third metal wire are formed by using the second through hole in the insulating layer formed on the first metal wire and the second metal wire respectively, thereby the three electrodes of the double-layer capacitor are led downward by using the first to third metal wires in the substrate, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are completed without adding additional process steps, which reduces the difficulty of process integration and is conducive to improving the capacitance density and design freedom of the double-layer capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0036] Figure 1 is a flow chart of a method for manufacturing a double-layer capacitor provided in Example 1;

[0037] Figure 2a to Figure 3e A schematic structural diagram corresponding to corresponding steps of the method for manufacturing a double-layer capacitor provided in Example 1;

[0038] Figure 4 This is a schematic diagram of the first through hole provided in the second embodiment.

[0039] In the attached figure:

[0040] 10-substrate; 11-first metal wire; 12-second metal wire; 13-third metal wire; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-first electrode material layer; 24a-first electrode; 25-first dielectric material layer; 26-second electrode material layer; 27-second dielectric material layer; 28-third electrode material layer; 28a-third electrode; 27a-second dielectric layer; 26a-second electrode; 25a-first dielectric layer; 31-third dielectric layer; 32-first through hole; 33-second through hole; 34-metal material layer; 35-fourth metal wire; 36-fifth metal wire. DETAILED DESCRIPTION

[0041] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0042] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0043] Embodiment 1

[0044] Figure 1 4 is a flow chart of a method for manufacturing a double-layer capacitor provided in Example 1.

[0045] like Figure 1 As shown, the manufacturing method of the double-layer capacitor provided in this embodiment includes:

[0046] S01: providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate;

[0047] S02: forming a groove in the insulating layer on the second metal line to expose the second metal line;

[0048] S03: conformally forming a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode in sequence on the insulating layer around the trench and in the trench to form a double-layer capacitor, wherein the first electrode is electrically connected to the second metal line;

[0049] S04: forming a third dielectric layer to cover the double-layer capacitor, and forming a plurality of first through holes in the third dielectric layer on both sides of the second metal line to expose the second electrode and the third electrode respectively;

[0050] S05: forming a plurality of second through holes in the insulating layer to expose the first metal line and the third metal line respectively;

[0051] S06: using the first through hole and the second through hole to form a fourth metal wire electrically connecting the first metal wire and the second electrode, and a fifth metal wire electrically connecting the third metal wire and the third electrode.

[0052] Figure 2a to Figure 3e The schematic diagram of the structure corresponding to the corresponding steps of the manufacturing method of the double-layer capacitor provided in this embodiment, and then Figure 2a to Figure 3e The method for manufacturing the double-layer capacitor will be described in detail.

[0053] First, please refer to Figure 2a , performing step S01, providing a substrate 10, in which first to third metal wires 11-13 arranged in the same layer and an insulating layer 22 covering the first to third metal wires 11-13 are formed.

[0054] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0055] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed by a Damascus process. Among them, the first to third metal wires 11-13 can be three metal wirings arranged at intervals in the Nth layer (N is greater than or equal to 1) in the interconnection layer, and the second metal wire 12 is located between the first metal wire 11 and the third metal wire 13. The materials of the three can include, for example, copper. In this embodiment, the first to third metal wires 11-13 can be three top-layer metal wirings arranged at intervals. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first to third metal wires 11-13. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serve as an etching stop layer during etching. Its material can include, for example, silicon nitride or silicon carbonitride, etc. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and it can include, for example, silicon oxide or silicon oxynitride, etc.

[0056] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11, multiple second metal wires 12 and multiple third metal wires 13 may be provided, and multiple identical metal wires are connected in parallel.

[0057] Next, please refer to Figure 2b , performing step S02 , forming a plurality of grooves 23 in the insulating layer 22 on the second metal line 12 to expose the second metal line 12 .

[0058] Specifically, a photolithography process can be used to define a groove area (not shown) on the insulating layer 22 on the second metal line 12, that is, the area where the subsequent double-layer capacitor is located, and then a dry etching process is used to sequentially etch the insulating layer 22 and the dielectric barrier layer 21 to form a plurality of spaced grooves 23 and expose the second metal line 12.

[0059] In practice, the lateral width of the trench region may be greater than the lateral width of a number of second metal lines 12 , that is, part of the trench 23 is located above the insulating layer 22 around the second metal line 12 (not directly above it).

[0060] Next, step S03 is performed to conformally form a first electrode 24a, a first dielectric layer 25a, a second electrode 26a, a second dielectric layer 27a and a third electrode 28a on the insulating layer 22 around the trench 23 and in the trench 23 to form a double-layer capacitor. The first electrode 24a is electrically connected to the second metal line 12.

[0061] For details, please refer to Figure 2c, forming a first electrode material layer 24 to conformally cover the surface of the insulating layer 22 and the inner wall of the groove 23. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 24, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride. Its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the first electrode material layer 24 may have a relatively thin thickness to form a double-layer trench capacitor, and its thickness may be, for example, 100 angstroms to 400 angstroms.

[0062] Please refer to Figure 2d , a patterning process is performed on the first electrode material layer 24 to form a first electrode 24a covering the inner wall of the groove 23 and the insulating layer 22 around the groove 23. A mask can be formed to cover a number of grooves 23 and the insulating layer 22 between the grooves 23, and then the remaining first electrode material layer 24 on the insulating layer 22 is removed, and then the mask is removed, and the first electrode material layer 24 covering the inner wall of the groove 23 and the insulating layer 22 between the grooves 23 is used as the first electrode 24a, and the first electrode 24a is electrically connected to the second metal wire 12 at the bottom of the groove 23, so as to use the second metal wire 12 to lead out the first electrode 24a. In addition, the first electrode 24a can also extend to cover the insulating layer 22 located around the outermost groove 23, so as to facilitate the positioning of the boundary of the mask, which is conducive to performing the patterning process.

[0063] Please refer to Figure 2e , a first dielectric material layer 25, a second electrode material layer 26, a second dielectric material layer 27 and a third electrode material layer 28 are sequentially conformally formed to cover the surface of the insulating layer 22 and the first electrode 24a, and the third electrode material layer 28 fills the groove 23 to form a top that is approximately flat. The material of the first dielectric material layer 25 and / or the second dielectric material layer 27 may be a dielectric material with a relatively high dielectric constant, whose dielectric constant may be, for example, greater than or equal to 3.9, and the material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide; the material of the second electrode material layer 26 and the third electrode material layer 28 may be similar to that of the first electrode material layer 24.

[0064] Please refer to Figure 2f, a patterning process is performed on the third electrode material layer 28 and the second dielectric material layer 27 to form a third electrode 28a and a second dielectric layer 27a, and the second electrode material layer 26 is exposed. A mask can be formed to cover the area corresponding to the first electrode 24a, that is, the groove 23 and the area corresponding to the periphery of the groove 23, and the exposed third electrode material layer 28 and the second dielectric material layer 27 are removed, and then the mask is removed, and the remaining third electrode material layer 28 is used as the third electrode 28a, and the remaining second dielectric material layer 27 is used as the second dielectric layer 27a. Among them, the third electrode 28a and the second dielectric layer 27a have a similar area, and its area is larger than the area of ​​the first electrode 24a, so as to provide a sufficient facing area between the electrodes, thereby increasing the capacitance value.

[0065] Please refer to Figure 2g , a patterning process is performed on the second electrode material layer 26 and the first dielectric material layer 25 to form the second electrode 26a and the first dielectric layer 25a, and a portion of the second electrode 26a is exposed. A masked third electrode 28a and a portion of the second electrode material layer 26 can be formed, that is, the coverage area thereof is slightly larger than the corresponding area of ​​the third electrode 28a, the exposed third electrode material layer 28 and the second dielectric material layer 27 are removed, and then the mask is removed, and the remaining second electrode material layer 26 is used as the second electrode 26a, and the remaining first dielectric material layer 25 is used as the first dielectric layer 25a. Among them, the area of ​​the second electrode 26a is larger than the area of ​​the third electrode 28a, that is, the edges of the second electrode 26a and the third electrode 28a form a step shape, including a lower step surface and an upper step surface (two steps), the edge of the second electrode 26a is located on the lower step surface, and the edge of the third electrode 28a is located on the upper step surface.

[0066] Thus, a double-layer trench capacitor consisting of a first electrode 24a, a first dielectric layer 25a, a second electrode 26a, a second dielectric layer 27a and a third electrode 28a is formed on the insulating layer 22 in the trench 23 and on the periphery of the trench 23 to increase the capacitance value (capacitance density) on the same substrate 10 area.

[0067] Next, step S04 is performed to form a third dielectric layer 31 to cover the surface of the double-layer capacitor, and to form a plurality of first through holes 32 in the third dielectric layer 31 on both sides of the second metal line 12 to expose the second electrode 26a and the third electrode 28a respectively.

[0068] For details, please refer to Figure 3a, forming a third dielectric layer 31 to cover the surface of the double-layer capacitor, including the third electrode 28a and the exposed second electrode 26a, and the third dielectric layer 31 can also extend to cover the insulating layer 22 outside the double-layer capacitor. The third dielectric layer 31 is used as a covering layer of the double-layer capacitor to electrically isolate the second electrode 26a and the third electrode 28a, and to form a contact hole for leading out the second electrode 26a and the third electrode 28a. The third dielectric layer 31 can be a single-layer dielectric or a multi-layer dielectric, and its material can include one or any of silicon oxide, silicon nitride, silicon carbonitride or silicon oxynitride, and can be formed by a suitable process including chemical vapor deposition or atomic layer deposition.

[0069] Please refer to Figure 3b , a plurality of first through holes 32 are formed in the third dielectric layer 31 on both sides of the second metal line 12 to expose the second electrode 26a and the third electrode 28a respectively. A mask may be formed to cover the surface of the third dielectric layer 31, and a plurality of openings are provided on the side close to the first metal line 11 to expose the third dielectric layer 31 on the lower step surface, and a plurality of openings are provided on the side close to the third metal line 13 to expose the third dielectric layer 31 on the upper step surface, and then a dry etching process is performed using the mask to remove the exposed third dielectric layer 31 to form a plurality of first through holes 32 to expose the third electrode 28a and the second electrode 26a respectively, that is, the first through holes 32 located on one side of the second metal line 12 and close to the first metal line 11 expose the second electrode 26a (lower step surface), and the plurality of first through holes 32 located on the other side of the second metal line 12 and close to the third metal line 13 expose the third electrode 28a (upper step surface). In addition, the number of first through holes 32 exposing the corresponding electrodes may also be greater than or equal to two rows.

[0070] Next, please refer to Figure 3c , step S05 is performed to form a plurality of second through holes 33 in the insulating layer 22 to expose the first metal wire 11 and the third metal wire 13 respectively.

[0071] Specifically, a patterning process may be performed to form a plurality of second through holes 33 in the dielectric barrier layer 21, the insulating layer 22, and the third dielectric layer 31 on the first metal line 11 to expose the first metal line 11, and to form a plurality of second through holes 33 in the dielectric barrier layer 21, the insulating layer 22, and the third dielectric layer 31 on the third metal line 13 to expose the third metal line 13. Since the second through holes 33 are deeper, the opening size of the second through holes 33 may be larger than the opening size of the first through holes 32, so as to facilitate the subsequent filling of metal in the second through holes 33.

[0072] Next, step S06 is performed to form a fourth metal wire 35 electrically connecting the first metal wire 11 and the second electrode 26 a , and a fifth metal wire 36 electrically connecting the third metal wire 13 and the third electrode 28 a , by using the first through hole 32 and the second through hole 33 .

[0073] For details, please refer to Figure 3d , a metal material layer 34 is formed to cover the surface of the third dielectric layer 31, the inner wall of the first through hole 32 and the second through hole 33, thereby connecting the first metal wire 11, the third metal wire 13, the second electrode 26a and the third electrode 28a. If the third dielectric layer 31 is not covered on part of the insulating layer 22, the metal material layer 34 can also cover the exposed insulating layer 22. Among them, the metal material layer 34 can be a metal material suitable for connection with an external circuit, such as aluminum or aluminum alloy. In this embodiment, the material of the first to third metal wires 11-13 includes copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence conformally. In practice, since the size (depth and opening width) of the first through hole 32 is small and the size of the second through hole 33 is large, the metal material layer 34 can fill the first through hole 32, and the metal material layer 34 can only cover the inner wall of the second through hole 33 without filling the second through hole 33.

[0074] Please refer to Figure 3e , a patterning process is performed on the metal material layer 34 to form a fourth metal line 35 connecting the first metal line 11 and the second electrode 26a and a fifth metal line 36 connecting the third metal line 13 and the third electrode 28a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two first through holes 32, using the metal material layer 34 close to the first metal line 11 and connecting the first metal line 11 and the second electrode 26a as the fourth metal line 35, and using the metal material layer 34 close to the third metal line 13 and connecting the third metal line 13 and the third electrode 28a as the fifth metal line 36.

[0075] In addition, during the patterning process of the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the insulating layer 22 (or the third dielectric layer 31), and other top-layer metal lines are electrically led out to the metal pad for connection with an external circuit.

[0076] Embodiment 2

[0077] Embodiment 2 provides a method for manufacturing a double-layer capacitor.

[0078] The manufacturing method of the double-layer capacitor provided in this embodiment is similar to the method provided in the first embodiment, and the difference lies mainly in that the fourth metal wire 35 in the second embodiment electrically connects the first metal wire and the third electrode, and the fifth metal wire electrically connects the third metal wire and the second electrode (i.e., a structure similar to the left-right symmetry of the capacitor in the first embodiment is formed). The steps in the second embodiment that are different from the first embodiment specifically include: in step S04, as Figure 4As shown, when a plurality of first through holes 32 are formed in the third dielectric layer 31 on both sides of the second metal line 12 to expose the second electrode 26a and the third electrode 28a respectively, and a plurality of first through holes 32 close to the first metal line 11 expose the third electrode 28a (upper step surface), while a plurality of first through holes 32 close to the third metal line 13 expose the second electrode 26a (lower step surface); thus, in step S06, when a patterning process is performed on the metal material layer 34 to form the fourth metal line 35 and the fifth metal line 36, the fourth metal line 35 electrically connecting the first metal line 11 and the third electrode 28a and the fifth metal line 36 electrically connecting the third metal line 13 and the second electrode 26a can be formed.

[0079] Embodiment 3

[0080] Embodiment 3 provides a double-layer capacitor.

[0081] Figure 3e This is a schematic diagram of the structure of a double-layer capacitor provided in Example 3.

[0082] The double-layer capacitor provided in the third embodiment can be formed by the method provided in the first or second embodiment. Figure 3e As shown, the double-layer capacitor may include a substrate 10, first to third metal wires 11-13, an insulating layer 22, a double-layer capacitor, a third dielectric layer 31, a fourth metal wire 35 and a fifth metal wire 36. The first to third metal wires 11-13 are arranged in the same layer in the substrate 10; the insulating layer 22 covers the first to third metal wires 11-13 and a plurality of grooves 23 are formed in the insulating layer 22 to expose the second metal wire 12 and a plurality of second through holes 33 are formed to expose the first metal wire 11 and the third metal wire 13 respectively; the double-layer capacitor is formed on the insulating layer 22 in the groove 23 and its surroundings, and includes a first electrode 24a, a first dielectric layer 25a, a second electrode 26a, a second dielectric layer 25a, which are sequentially conformally formed. 7a and the third electrode 28a, the first electrode 24a is electrically connected to the second metal wire 12; the third dielectric layer 31 covers the double-layer capacitor, and a plurality of first through holes 32 are formed in the third dielectric layer 31 to expose the second electrode 26a and the third electrode 28a respectively; the fourth metal wire 35 utilizes the first through hole 32 and the second through hole 33 to electrically connect the first metal wire 11 and the second electrode 26a, and the fifth metal wire 36 utilizes the first through hole 32 and the second through hole 33 to electrically connect the third metal wire 13 and the third electrode 28a.

[0083] In addition, in other examples of this embodiment (refer to the manufacturing method provided in the second embodiment), the fourth metal wire 35 can also utilize the first through hole 32 and the second through hole 33 to electrically connect the first metal wire 11 and the third electrode 28a, and the fifth metal wire 36 utilizes the first through hole 32 and the second through hole 33 to electrically connect the third metal wire 13 and the second electrode 26a.

[0084] In summary, the present invention forms a groove in the insulating layer on the second metal wire to expose the second metal wire, and forms a double-layer capacitor on the insulating layer in the groove and around the groove, the first electrode of the double-layer capacitor is connected to the second metal wire at the bottom of the groove, the second electrode and the third electrode of the double-layer capacitor are both exposed upward, and then a third dielectric layer is formed to cover the double-layer capacitor, and a first through hole is formed in the third dielectric layer to expose the second electrode and the third electrode respectively, and a fourth metal wire connecting the second electrode and the first metal wire and a fifth metal wire connecting the third electrode and the third metal wire are formed by using the second through hole in the insulating layer formed on the first metal wire and the second metal wire respectively, thereby the three electrodes of the double-layer capacitor are led out downward by using the first to third metal wires in the substrate, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are completed without adding additional process steps, which reduces the difficulty of process integration and is conducive to improving the capacitance density and design freedom of the double-layer capacitor.

[0085] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a double-layer capacitor, characterized in that: include: Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate; forming a trench in the insulating layer on the second metal line to expose the second metal line; A first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode are sequentially conformally formed on the insulating layer around the groove and in the groove to form a double-layer capacitor, and the surface of the third electrode and a portion of the second electrode are exposed, and the first electrode is electrically connected to the second metal line; forming a third dielectric layer to cover the double-layer capacitor, and forming a plurality of first through holes in the third dielectric layer on both sides of the second metal line to expose the second electrode and the third electrode respectively; Forming a plurality of second through holes in the insulating layer to expose the first metal line and the third metal line respectively; The first through hole and the second through hole are used to form a fourth metal wire to connect the first metal wire and the second electrode, and a fifth metal wire to connect the third metal wire and the third electrode.

2. The method for manufacturing a double-layer capacitor according to claim 1, wherein: A dielectric barrier layer is also provided between the first to third metal wires and the insulating layer.

3. The method for manufacturing a double-layer capacitor according to claim 1, wherein: The steps of forming the double layer capacitor include: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove; Performing a patterning process on the first electrode material layer to form an insulating layer where the first electrode covers the inner wall of the trench and the periphery of the trench; Conformally forming a first dielectric material layer, a second electrode material layer, a second dielectric material layer and a third electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; Performing a patterning process on the third electrode material layer and the second dielectric material layer to form the third electrode and the second dielectric layer, and exposing the second electrode material layer; A patterning process is performed on the second electrode material layer and the first dielectric material layer to form the second electrode and the first dielectric layer, and a portion of the second electrode is exposed.

4. The method for manufacturing a double-layer capacitor according to claim 3, characterized in that: The materials of the first electrode, the second electrode and the third electrode include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

5. The method for manufacturing a double-layer capacitor according to claim 3, characterized in that: The dielectric constants of the first dielectric layer and the second dielectric layer are greater than or equal to 3.

9.

6. The method for manufacturing a double-layer capacitor according to claim 3, characterized in that: The material of the third dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.

7. The method for manufacturing a double-layer capacitor according to claim 3, characterized in that: The edges of the second electrode and the third electrode form a step shape, the edge of the second electrode is located at the lower step surface, and the edge of the third electrode is located at the upper step surface. The third dielectric layer is subjected to a patterning process to synchronously form the first through holes, which are respectively located on both sides of the second metal line, and the first through holes on one side expose the lower step surface, and the through holes on the other side expose the upper step surface.

8. The method for manufacturing a double-layer capacitor according to claim 1, wherein: The steps of forming the fourth metal line and the fifth metal line include: Forming a metal material layer to cover the surface of the insulating layer, the surface of the third dielectric layer, and the inner walls of the first through hole and the second through hole; A patterning process is performed on the metal material layer to form a fourth metal line connecting the first metal line and the second electrode and a fifth metal line connecting the third metal line and the third electrode.

9. The method for manufacturing a double-layer capacitor according to claim 1, wherein: When the metal material layer is patterned, a metal pad is also formed on the surface of the insulating layer simultaneously for connection with an external circuit.

10. A double layer capacitor, characterized in that: include: substrate; First to third metal wires are arranged in the same layer in the substrate; an insulating layer, covering the first to third metal wires and having a groove formed in the insulating layer to expose the second metal wire and a plurality of second through holes to expose the first metal wire and the third metal wire respectively; A double-layer capacitor is formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode which are sequentially formed conformally, wherein the first electrode is electrically connected to the second metal line; A third dielectric layer covers the double-layer capacitor, and a plurality of first through holes are formed in the third dielectric layer to expose the second electrode and the third electrode respectively; The fourth metal wire and the fifth metal wire utilize the first through hole and the second through hole. The fourth metal wire electrically connects the first metal wire and the second electrode, and the fifth metal wire electrically connects the third metal wire and the third electrode.

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