Non-volatile memory

Abstract

The invention discloses a non-volatile memory. The nonvolatile memory comprises: a storage module comprising a plurality of first storage units and a first data storage path; the redundant storage module comprises a plurality of second storage units and a second data storage path, and the structure of the second data storage path is consistent with that of the first data storage path; when at least part of the structure of the first data storage path has defects and / or at least one of the plurality of first storage units connected with the same first data storage path has defects, storing the first data storage path; and activating the corresponding second data storage path and a plurality of second storage units connected with the second data storage path so as to write / read the corresponding numerical value of each first storage unit connected with the first data storage path. The product yield of the nonvolatile memory is improved by taking the first data storage path and the plurality of first storage units connected to the first data path as minimum replacement units.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a non-volatile memory. Background Art

[0002] Non-volatile memory (NVM) is a type of memory that can retain stored information even after power is turned off. It is widely used in many electronic systems that require long-term data storage, such as computer systems and mobile devices.

[0003] Non-volatile memory implements data writing or reading through a large number of memory cells arranged in an array. During the production or use of non-volatile memory, some memory cells may be damaged due to various factors. In the prior art, in order to prevent these damaged memory cells from affecting the reliability of the non-volatile memory, redundant memory cells are set to replace damaged memory cells during the design of non-volatile memory.

[0004] However, when non-volatile memory is working, it requires multiple functional circuits to cooperate with each other rather than relying on a single storage unit. Therefore, simply replacing the storage unit may not eliminate the defects of non-volatile memory, nor improve the product yield in the production process or increase the service life of the product during use. Summary of the invention

[0005] In view of the above problems, the purpose of the present application is to provide a non-volatile memory, which uses a data storage path as the minimum unit to be replaced, thereby improving the reliability of the non-volatile memory.

[0006] According to one aspect of the present application, a non-volatile memory is provided, which includes: a storage module, including multiple first storage units and a first data storage path, the first data storage path is connected to the multiple first storage units to write / read the values ​​of corresponding data bits in the storage data, the first data storage path includes a decoding module, the decoding module is used to select the corresponding first storage unit for read / write operation according to address information; and a redundant storage module, including multiple second storage units and a second data storage path, the second data storage path is connected to the multiple second storage units to perform read / write operations on each second storage unit via the second data storage path, the structure of the second data storage path is consistent with the structure of the first data storage path, wherein, when at least part of the structure of the first data storage path is defective and / or at least one of the multiple first storage units connected to the same first data storage path is defective, the corresponding second data storage path and the multiple second storage units connected to the second data storage path are activated to write / read the corresponding values ​​of each first storage unit connected to the first data storage path.

[0007] Optionally, the first data storage path also includes multiple bit lines, each of the first storage units is connected to the first data storage path via the corresponding bit line, and the decoding module includes multiple first-level multiplexers, and the corresponding first-level multiplexer selects the corresponding bit line according to the address information to perform read / write operations on the corresponding first storage unit.

[0008] Optionally, the multiple first storage units form multiple storage arrays, the first-level multiplexers corresponding to each storage array form a first-level decoder corresponding to the storage array, and the decoding module also includes a second-level decoder composed of multiple second-level multiplexers, and the second-level decoder selects the corresponding first-level decoder according to the address information to select the corresponding storage array.

[0009] Optionally, the first data storage path further includes a comparator, and the comparator is used to obtain a value of the corresponding first storage unit according to a comparison result between the bit line current and the reference current.

[0010] Optionally, the non-volatile memory also includes: a selection unit, which provides a selection signal to activate the corresponding second data storage path and the corresponding second storage unit when the address information falls into the address range corresponding to the replacement information; and a data processing unit, which is respectively connected to the selection unit, the storage module and the redundant storage module, and during a read operation, the data processing unit reads the corresponding second storage unit via the second data storage path activated by the selection signal to obtain the value of the data bit corresponding to the corresponding address information; during a write operation, the data processing unit provides the value of the corresponding data bit to the corresponding second storage unit via the second data storage path corresponding to the selection signal.

[0011] Optionally, the selection unit includes: a storage module for storing the replacement information, wherein at least a partial structure of the first data storage path corresponding to the address range of the replacement information is defective and / or at least one of the multiple first storage units connected to the first data storage path is defective; and a comparison module for comparing the address information and the replacement information to provide the selection signal when the address information falls within the address range corresponding to the replacement information.

[0012] Optionally, the storage module is a non-volatile storage module, and the selection unit further includes a register module, which is connected between the storage module and the comparison module, and is used to pre-read the replacement information after the non-volatile memory is powered on.

[0013] Optionally, the replacement information includes: an enable signal, indicating whether the current replacement information is valid; a storage array address, used to indicate the storage array corresponding to the replaced first-level storage unit; a first-level decoding address, used to indicate the replaced first storage unit; a second-level decoding address, used to indicate the replaced first-level decoder; a comparator address, used to indicate the comparator corresponding to the replaced first data storage path; and data bit information, used to indicate the data bit corresponding to the replaced first data storage path in the stored data.

[0014] Optionally, when replacing multiple primary data storage paths at the same time, each group of replacement information also includes: a primary decoding address bit width, used to indicate a matching range of the primary decoding address; and a secondary decoding address bit width, used to indicate a matching range of the secondary decoding address.

[0015] Optionally, the replacement information further includes a storage array replacement quantity, which is used to indicate the quantity and range of the replaced storage arrays corresponding to the replacement information.

[0016] Optionally, the replacement information pre-stored in the storage module is acquired during factory inspection of the non-volatile memory.

[0017] According to the non-volatile memory provided by the present application, a redundant storage module having the same structure as the storage module is provided to provide a second storage unit and a second data storage path for replacing the first storage unit and the first data storage path. By taking the first data storage path and the plurality of first storage units connected to the first data path as the smallest replacement unit, the influence on the reliability of the non-volatile memory when there is a defect in the first data storage path and / or at least one of the plurality of first storage units connected to the first data storage path is defective can be avoided, thereby improving the product yield of the non-volatile memory during the production process and improving the service life of the non-volatile memory during use.

[0018] Furthermore, since the replacement information includes data such as the first-level decoding address bit width, the second-level decoding address bit width, the number of storage array replacements, etc., the corresponding replacement information can be configured according to the specific defect situation of the data storage unit and the impact scope of the defect, thereby reducing the overhead required to adapt the replacement information and facilitating cost savings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic structural block diagram of a non-volatile memory in the prior art is shown;

[0021] Figure 2 A schematic structural block diagram of a non-volatile memory according to an embodiment of the present application is shown;

[0022] Figure 3 Show Figure 2 A schematic structural block diagram of a storage module and a redundant storage module is shown;

[0023] Figure 4 Show Figure 2 A schematic structural block diagram of the selection unit shown;

[0024] Figure 5 A schematic diagram showing the composition structure of replacement information. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0027] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0028] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0029] Figure 1 FIG. 1 shows a schematic structural block diagram of a non-volatile memory in the prior art. Figure 1 As shown, the non-volatile memory 100 includes a timing control unit 110 , a row decoder 120 , a column decoder 130 and a storage module 140 .

[0030] The timing control unit 110 provides a corresponding timing control signal according to the externally provided clock signal CLK and the command signal CMD. It should be understood that the timing control signal is a general term for a type of signal rather than a single signal. For example, see Figure 1 The timing control signal includes a word selection signal WLP and a column selection signal BLP.

[0031] The row decoder 120 decodes the row address WADD to generate a decoded row address DW, and provides the decoded row address DW to the memory module 140 during the active level period of the word selection signal WLP.

[0032] The column decoder 130 decodes the column address BADD to generate a decoded column address DB, and provides the decoded column address DB to the memory module 140 during the active level period of the column selection signal BLP.

[0033] The storage module 140 includes a storage array 141, a decoding module 142, a comparator module 143 and a redundant storage array 144. The storage array 141 includes a plurality of storage cells MC arranged in an array, the decoding module 142 includes a plurality of multiplexers, and the comparator module 143 includes a plurality of comparators ( Figure 1 The multiplexer and comparator are not shown).

[0034] Each memory cell MC includes a transistor as a switching element and a capacitor that holds data as a charge. Each memory cell MC is connected to the row decoder 120 via a corresponding word line WL. Each memory cell MC is also connected to a corresponding data storage path to write / read the value of the corresponding data bit in the stored data. Specifically, each data storage path includes a bit line BL connected to the corresponding memory cell MC and connected to the multiplexer and comparator corresponding to the memory cell MC, thereby forming multiple data storage paths in the storage module 140.

[0035] Taking the memory cells MC in the same row sharing a word line WL and the memory cells MC in the same column sharing a bit line BL as an example, that is to say, multiple memory cells MC in the same column are connected to the same data storage path. When performing a read / write operation, the decoding module 142 receives the decoded column address DB to activate the corresponding data storage path. The memory cells MC corresponding to the decoded row address DW among the multiple memory cells MC on the data storage path are selected in sequence, thereby changing the connectivity state of the capacitors in these memory cells. When the capacitor is connected / disconnected, the current on the corresponding bit line changes. The comparator on the data storage path senses the current on the bit line and compares it with the reference current Iref to obtain the value stored in the corresponding memory cell MC (that is, the value of the corresponding data bit in the stored data).

[0036] The redundant memory array 144 includes a plurality of redundant memory cells (not shown) arranged in an array. The structure of the redundant memory cells is, for example, the same as the structure of the memory cells MC in the memory array 141. These redundant memory cells are used to replace defective memory cells MC to improve the reliability of stored data.

[0037] However, in the production and use of non-volatile memory, in addition to the possible defects of the memory cell MC (such as damage, failure of a single memory cell or crosstalk between multiple memory cells, etc.), the bit line (or other connection line), multiplexer and comparator on the data storage path connected to the memory cell MC may also have defects (such as single bit line breakage, short circuit of adjacent bit lines, damage of multiplexer, damage of comparator, etc.). Therefore, only by setting up a redundant memory array 144 to replace the defective memory cell MC, it is impossible to eliminate the defects of the corresponding data storage path, and it is also impossible to improve the product yield in the production process or increase the service life of the product in the use process.

[0038] The present application provides a non-volatile memory, which provides a plurality of second storage units and a second data storage path by setting a redundant storage module corresponding to a storage module. When at least part of the structure of the first data storage path is defective and / or at least one of the plurality of first storage units connected to the same first data storage path is defective, the corresponding second data storage path and the plurality of second storage units connected to the second data storage path are activated to write / read the corresponding values ​​of the first storage units connected to the first data storage path, thereby improving the reliability of the non-volatile memory.

[0039] Figure 2 A schematic structural block diagram of a non-volatile memory according to an embodiment of the present application is shown; Figure 3 Show Figure 2 A schematic structural block diagram of a storage module and a redundant storage module is shown; Figure 4 Show Figure 2 The schematic structural block diagram of the selection unit is shown below. Figures 2 to 4 The non-volatile memory provided in this application is further described.

[0040] like Figure 2 As shown, the non-volatile memory 200 includes a timing control unit 210 , a row decoder 220 , a column decoder 230 , a storage module 240 , a redundant storage module 250 , a selection unit 260 and a data processing unit 270 .

[0041] The timing control unit 210 provides a corresponding timing control signal according to the externally provided clock signal CLK and the command signal CMD. It should be understood that the timing control signal is a general term for a type of signal rather than a single signal. For example, see Figure 2 The timing control signal includes a word selection signal WLP and a column selection signal BLP.

[0042] The row decoder 220 decodes the row address WADD to generate a decoded row address DW, and provides the decoded row address DW to the memory module 240 during the active level period of the word selection signal WLP.

[0043] The column decoder 230 decodes the column address BADD to generate a decoded column address DB, and provides the decoded column address DB to the memory module 240 during the active level period of the column selection signal BLP.

[0044] The storage module 240 includes a storage array 241 , a decoding module 10 and a comparator module 244 .

[0045] The storage array 241 includes a plurality of first storage cells MC arranged in an array. The decoding module 10 includes a plurality of multiplexers, and the comparator module 244 includes a plurality of comparators (the multiplexers and comparators are not shown in the figure).

[0046] Each first storage cell MC includes a transistor as a switching element and a capacitor that holds data as an electric charge. Each first storage cell MC is connected to a row decoder 220 via a corresponding word line WL. Each first storage cell MC is also connected to a corresponding first data storage path to write / read the value of a corresponding data bit in the stored data. Specifically, each first data storage path includes a bit line BL connected to the corresponding first storage cell MC and a multiplexer and a comparator connected to the first storage cell MC via the bit line BL. In other words, each first data storage path includes a decoding module 10 (i.e., a corresponding multiplexer) and a comparator module (i.e., a corresponding comparator).

[0047] Taking the first storage cells MC in the same row sharing a word line WL and the first storage cells MC in the same column sharing a bit line BL as an example, that is to say, multiple first storage cells MC in the same column are connected to the same first data storage path. When performing read and write operations, the decoding module 10 receives the decoded column address DB to select and activate the corresponding first data storage path. The first storage cells MC corresponding to the decoded row address DW among the multiple first storage cells MC on the first data storage path are selected in sequence, thereby changing the connectivity state of the capacitors in these first storage cells MC. When the capacitor is connected / disconnected, the current on the corresponding bit line changes. The comparator on the first data storage path senses the current on the bit line and compares it with the reference current Iref to obtain the value stored in the corresponding first storage cell MC on the first data storage path (that is, the value of the corresponding data bit in the stored data).

[0048] The structure of the redundant storage module 250 is consistent with the composition structure of the storage module 240, thereby providing a plurality of second storage units SMC and a plurality of second data storage paths consistent with the first data storage path structure.

[0049] Specifically, the redundant storage module 250 includes a redundant storage array 251 , a redundant decoding module 20 , and a redundant comparator module 254 .

[0050] The redundant storage array 251 includes a plurality of second storage units SMC arranged in an array. The structures of the redundant decoding module 20 and the redundant comparator module 254 are respectively consistent with the composition structures of the decoding module 10 and the comparator module 244. Among them, the redundant decoding module 20 includes a plurality of redundant multiplexers, and the redundant comparator module 254 includes a plurality of redundant comparators (the redundant multiplexers and the redundant comparators are not shown in the figure).

[0051] It should be noted that the consistency of the structure of the redundant storage module 250 and the storage module 240 should be understood as the consistency of the composition structure or connection relationship rather than the consistency of the number. For example, the redundant storage array 251 of the storage array 241 with the same structure can be understood as the number and connection method of the first storage units connected to the same first data storage path being consistent with the number and connection method of the second storage units connected to the same second data storage path, rather than the number of the first storage unit MC and the second storage unit SMC being consistent. In addition, since the second storage unit SMC and the second data storage path provided by the redundant storage module 250 are used as backup for the first storage unit MC and the first data storage path, the number of the second storage unit SMC in the redundant storage array 251, the number of the redundant multiplexers in the redundant decoding module 20, and the number of the redundant comparators in the redundant comparator module 254 are usually smaller than the number of the first storage units in the storage array 241, the number of the multiplexers in the decoding module 10, and the number of the comparators in the comparator module 244.

[0052] Each second storage cell SMC is connected to the row decoder 120 via a corresponding redundant word line (not shown in the figure). Each second storage cell SMC is also connected to a corresponding second data storage path to write / read the value of the corresponding data bit in the storage data. Specifically, each second data storage path includes a redundant bit line SBL connected to the corresponding second storage cell SMC and a redundant multiplexer and a redundant comparator connected to the second storage cell SMC via the redundant bit line SBL. In other words, each second data storage path includes a redundant decoding module (i.e., a corresponding redundant multiplexer) and a redundant comparator module (i.e., a corresponding redundant comparator).

[0053] Taking the second storage cells SMC in the same row sharing a redundant word line and the second storage cells SMC in the same column sharing a redundant bit line SBL as an example, that is, multiple second storage cells SMC in the same column share a second data storage path. In addition, the number of second storage cells SMC sharing the same redundant bit line SBL is consistent with the number of storage cells MC sharing the same bit line BL. When performing read and write operations, the redundant decoding module 20 receives the selection signal SS (described in detail below) provided by the selection unit 260 and activates the corresponding second data storage path. The second storage cells SMC corresponding to the decoded row address DW among the multiple second storage cells SMC on the second data storage path are selected in sequence, thereby changing the connection state of the capacitors in these second storage cells SMC. When the capacitor is connected / disconnected, the current on the corresponding redundant bit line SBL changes. The redundant comparator on the second data storage path senses the current on the redundant bit line and compares it with the reference current Iref to obtain the value stored in the corresponding second storage cell SMC on the second data storage path.

[0054] Furthermore, in some embodiments, in order to improve the storage performance of the non-volatile memory, multiple storage arrays 241 (for example, Figure 3 In other words, the first storage cells MC corresponding to the first data storage paths in the storage module 240 form a plurality of storage arrays 241 .

[0055] Accordingly, the second storage units SMC corresponding to the second data storage paths in the redundant storage module 250 form a plurality of redundant storage arrays 251 (for example, Figure 3 Two redundant storage arrays 251 are shown in FIG. 1 ). Each storage array 241 has its corresponding redundant storage array 251.

[0056] Furthermore, the multiplexer in the decoding module 10 includes a primary multiplexer and a secondary multiplexer (not shown in the figure), and the primary multiplexer corresponding to each storage array 241 constitutes a primary decoder 242 corresponding to the storage array, and the secondary multiplexer corresponding to each primary decoder constitutes a secondary decoder 243 of the storage module. That is, the decoding module 10 includes a primary decoder 242 corresponding to each storage array 241 and a secondary decoder 243 shared by each primary decoder 242. The design of multi-stage decoding is more conducive to reducing the area of ​​the decoding module 10, and can also reduce decoding delay and improve the performance of the non-volatile memory.

[0057] Correspondingly, the redundant multiplexers in the redundant decoding module 20 include a redundant primary multiplexer and a redundant secondary multiplexer (not shown in the figure), the redundant primary multiplexer corresponding to each redundant storage array 251 constitutes a redundant primary decoder 252 corresponding to the redundant storage array, and the redundant secondary multiplexers corresponding to each redundant primary decoder 252 constitute a redundant secondary decoder 253. That is, the redundant decoding module 20 includes a redundant primary decoder 252 corresponding to each redundant storage array 251 and a redundant secondary decoder 253 shared by each redundant primary decoder 252.

[0058] The selection unit 260 is used to provide a selection signal SS to activate the corresponding second data storage path and the corresponding second storage cell SMC when the address information (the decoded column address DB) falls into the address range corresponding to the replacement information. In other words, the selection unit 260 provides a selection signal to activate the corresponding second data storage path and the corresponding second storage cell SMC when at least part of the structure of the first storage path corresponding to the address information is defective and / or at least one of the multiple first storage cells MC connected to the same first data storage path is defective.

[0059] like Figure 4 As shown, the selection unit 260 includes a storage module 261 , a register module 262 and a comparison module 263 .

[0060] The storage module 261 stores replacement information RI, and the replacement information RI corresponds to that at least part of the structure of the first data storage path in the address range is defective and / or at least one of the plurality of first storage cells MC connected to the first data storage path is defective.

[0061] Figure 5 FIG. 1 shows a schematic diagram of the composition structure of the replacement information RI. Figure 3 The non-volatile memory having multiple storage arrays and a decoding module 10 having two-stage decoding is shown, as Figure 5 As shown, the replacement information RI includes:

[0062] Enable signal, indicating whether the current replacement information RI is valid.

[0063] The storage array address is used to indicate the storage array corresponding to the first storage unit to be replaced.

[0064] The decoding address is used to indicate the replaced first data storage path and the first storage unit, and specifically includes a secondary decoding address for indicating the replaced primary decoder and a primary decoding address for indicating the replaced first storage unit.

[0065] The comparator address is used to indicate the comparator corresponding to the replaced first data storage path.

[0066] The data bit information is used to indicate the data bit corresponding to the replaced first data storage path in the stored data. For example, when the stored data includes X data bits (X is a positive integer), the data bit information is used to indicate which of the X data bits the value stored in the replaced data storage path is.

[0067] Further, in some embodiments, a defective first storage unit and / or first data storage path may affect the first storage unit and / or first data storage path adjacent thereto. In order to eliminate these defects, it is necessary to simultaneously replace multiple first data storage paths and multiple first storage units connected to these first data storage paths. Therefore, the replacement information RI may also include a first-level decoding address bit width for indicating a first-level decoding address matching range and a second-level decoding address bit width for indicating a second-level decoding address matching range.

[0068] Specifically, for the first-level decoding address A[k:j], if only one first data storage path needs to be replaced, then the first-level decoding address of the first data storage path needs to match A[k:j]; if multiple first data storage paths need to be replaced, then the first-level decoding address bit width also needs to indicate which addresses in A[k:j] do not need to be matched; if all first-level data storage paths need to be replaced, then the first-level decoding address bit width also needs to indicate that all addresses of A[k:j] do not need to be matched.

[0069] Similarly, for the secondary decoding address A[e:l], if only one first data storage path needs to be replaced, then the secondary decoding address of the first data storage path needs to match A[e:l]; if multiple first data storage paths need to be replaced, then the secondary decoding address bit width needs to indicate which addresses in A[e:l] do not need to be matched; if all first data storage paths need to be replaced, then the secondary decoding address bit width needs to indicate that all addresses of A[e:l] do not need to be matched.

[0070] By setting the decoding address bit width, corresponding replacement information RI can be configured according to the impact of the defective data path on the surrounding data paths. In addition, multiple first data storage paths can be replaced by one set of replacement information RI, which greatly saves the storage space and corresponding calculation overhead required for the replacement information RI.

[0071] In some embodiments, when the storage module 240 includes multiple storage arrays 241, the arrangement of the storage cells MC in each storage array 241 is often exactly the same, and the address information corresponding to the storage cells MC at corresponding positions in different storage arrays may be slightly different. Therefore, in order to further save the corresponding calculation overhead and required storage space, the replacement information RI also includes the number of storage array replacements to indicate the number and range of storage arrays that are replaced at the same time.

[0072] For example, for the address A[n:m] of a storage array, if only one storage array needs to be replaced, then the address of the storage array needs to completely match A[n:m]; if part of multiple storage arrays needs to be replaced, then the storage array replacement number needs to indicate which addresses in A[n:m] do not need to be matched; if all storage arrays need to be replaced, then the storage array replacement number needs to indicate that all addresses in A[n:m] do not need to be matched.

[0073] Further, in some embodiments, during the test process of the non-volatile memory before delivery, the corresponding replacement information RI is configured according to the test results and pre-stored in the storage module 261. Therefore, in order to store the replacement information RI for a long time, the storage module 261 needs to use a non-volatile storage module.

[0074] In addition, in some embodiments, during the use of the non-volatile memory, the replacement information RI in the storage module 261 is also regularly updated according to the use of the non-volatile memory.

[0075] The comparison module 263 compares the address information and the replacement information to provide a selection signal SS when the address information falls within an address range corresponding to the replacement information.

[0076] Furthermore, in order to improve the response speed of the selection unit 260, a register module 262 connected between the storage module 261 and the comparison module 263 may be provided. When the non-volatile memory is powered on, the replacement information RI stored in the storage module 261 is pre-read through the register module 262 (including a plurality of registers). Therefore, when the comparison module 263 receives the address information, the corresponding replacement information RI can be provided immediately.

[0077] The data processing unit 270 is respectively connected to the selection unit 260, the storage module 240 and the redundant storage module 250. During a read operation, the data processing unit reads the corresponding second storage unit via the second data storage path activated by the selection signal to obtain the value of the data bit corresponding to the corresponding address information; during a write operation, the data processing unit provides the value of the corresponding data bit to the corresponding second storage unit via the second data storage path corresponding to the selection signal.

[0078] Taking the read operation as an example, for the decoded column address DB, the storage module 240 selects the corresponding Y first data storage paths to read out the corresponding storage data Data. At the same time, the selection unit 260 determines that Z of the Y first data storage paths are defective, and provides the selection signal SS to the redundant storage module 250 to activate the corresponding Z second data storage paths (Z is a positive integer and Z≤Y) to read out the corresponding replacement data S-Data. The data processing unit 270 replaces the data bit values ​​of the replacement data S-Data with the corresponding data bits of the data Data read out by the storage module 240 according to the selection signal SS, thereby obtaining the storage data Data' read out by the non-volatile memory.

[0079] According to the non-volatile memory provided by the present application, a redundant storage module having the same structure as the storage module is provided to provide a second storage unit and a second data storage path for replacing the first storage unit and the first data storage path. By taking the first data storage path and the plurality of first storage units connected to the first data path as the smallest replacement unit, the influence on the reliability of the non-volatile memory when there is a defect in the first data storage path and / or at least one of the plurality of first storage units connected to the first data storage path is defective can be avoided, thereby improving the product yield of the non-volatile memory during the production process and improving the service life of the non-volatile memory during use.

[0080] Furthermore, since the replacement information includes data such as the first-level decoding address bit width, the second-level decoding address bit width, the number of storage array replacements, etc., the corresponding replacement information can be configured according to the specific defect situation of the data storage unit and the impact scope of the defect, thereby reducing the overhead required to adapt the replacement information and facilitating cost savings.

[0081] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A non-volatile memory, wherein: include: A storage module, comprising a plurality of first storage units and a first data storage path, wherein the first data storage path is connected to the plurality of first storage units to write / read values ​​of corresponding data bits in the stored data, and the first data storage path comprises a decoding module, wherein the decoding module is used to select the corresponding first storage unit for read / write operation according to address information; as well as A redundant storage module comprises a plurality of second storage units and a second data storage path, wherein the second data storage path is connected to the plurality of second storage units so as to perform a read / write operation on each of the second storage units via the second data storage path, and the structure of the second data storage path is consistent with the structure of the first data storage path. In which, when at least part of the structure of the first data storage path is defective and / or at least one of the multiple first storage units connected to the same first data storage path is defective, the corresponding second data storage path and the multiple second storage units connected to the second data storage path are activated to write / read the corresponding values ​​of each of the first storage units connected to the first data storage path.

2. The nonvolatile memory according to claim 1, wherein: The first data storage path further includes a plurality of bit lines, and each of the first storage units is connected to the first data storage path via a corresponding bit line. The decoding module includes a plurality of first-level multiplexers, and a corresponding first-level multiplexer selects a corresponding bit line according to the address information to perform a read / write operation on the corresponding first storage unit.

3. The nonvolatile memory according to claim 2, wherein: The plurality of first storage units form a plurality of storage arrays, and the first-level multiplexer corresponding to each storage array forms a first-level decoder corresponding to the storage array. The decoding module also includes a secondary decoder composed of a plurality of secondary multiplexers, and the secondary decoder selects the corresponding primary decoder according to the address information to select the corresponding storage array.

4. The nonvolatile memory according to claim 3, wherein: The first data storage path further includes a comparator, which is used to obtain a value of the corresponding first storage unit according to a comparison result between a bit line current and a reference current.

5. The nonvolatile memory according to claim 4, wherein: The non-volatile memory further comprises: a selection unit, providing a selection signal to activate the corresponding second data storage path and the corresponding second storage unit when the address information falls within the address range corresponding to the replacement information; and a data processing unit, wherein the data processing unit is connected to the selection unit, the storage module and the redundant storage module respectively; During a read operation, the data processing unit reads the corresponding second storage unit via the second data storage path activated by the selection signal to obtain a value of a data bit corresponding to the corresponding address information; During a write operation, the data processing unit provides the value of the corresponding data bit to the corresponding second storage unit via the second data storage path corresponding to the selection signal.

6. The nonvolatile memory according to claim 5, wherein: The selection unit comprises: a storage module, configured to store the replacement information, wherein the replacement information indicates that at least a partial structure of the first data storage path corresponding to the address range is defective and / or at least one of the plurality of first storage units connected to the first data storage path is defective; and A comparison module compares the address information and the replacement information to provide the selection signal when the address information falls within an address range corresponding to the replacement information.

7. The nonvolatile memory according to claim 6, wherein: The storage module is a non-volatile storage module. The selection unit further includes a register module, which is connected between the storage module and the comparison module, and is used to pre-read the replacement information after the non-volatile memory is powered on.

8. The nonvolatile memory according to claim 6, wherein: The replacement information includes: An enable signal, indicating whether the current replacement information is valid; A storage array address, used to indicate the storage array corresponding to the replaced primary storage unit; A first level decoding address, used to indicate a first storage unit to be replaced; A secondary decoding address, used to indicate the primary decoder to be replaced; a comparator address, used to indicate the comparator corresponding to the first data storage path to be replaced; and The data bit information is used to indicate the data bit corresponding to the first data storage path being replaced in the storage data.

9. The nonvolatile memory according to claim 8, wherein: When multiple primary data storage paths are replaced simultaneously, each set of replacement information further includes: A first-level decoding address bit width, used to indicate a matching range of the first-level decoding address; and The secondary decoding address bit width is used to indicate the matching range of the secondary decoding address.

10. The nonvolatile memory according to claim 9, wherein: The replacement information also includes a storage array replacement quantity, which is used to indicate the quantity and range of the replaced storage arrays corresponding to the replacement information.

11. The nonvolatile memory according to claim 5, wherein: The replacement information pre-stored in the storage module is obtained during factory inspection of the non-volatile memory.

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