Photoelectric co-packaging structure and preparation method thereof

Abstract

According to the photoelectric co-packaging structure and the preparation method thereof provided by the invention, in the packaging process, the fan-out process is used for completing the connection of the micro solder bumps at the bonding pad region of the optical chip and the image sensor, so that the large-scale and high-density photoelectric co-packaging of the optical chip and the image sensor is realized; the distance between the image area of the image sensor and the grating coupling-out area of the optical chip is controlled to be within 30 microns, so that the image sensor and the optical chip can be ensured to be attached at a short distance to receive optical signals of the optical chip, and electric signals of the image sensor can be ensured to be led out to the substrate through the second lead. Therefore, the difficulty of signal transmission between the optical chip and the image sensor as well as between the optical chip and other devices is effectively reduced, in addition, the photoelectric co-packaging structure is relatively simple and relatively low in preparation cost, so that the yield of a finished product of the photoelectric co-packaging structure can be improved, and the service life of the finished product of the photoelectric co-packaging structure can be prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an optoelectronic co-packaging structure and a preparation method thereof. Background Art

[0002] As the core component of photoelectric conversion, image sensors play an important role in machine vision, communication, medical and other fields. As the key component of light source or optical signal processing, the integration of optical chips with image sensors has become the key to improving system performance. However, during the integration of image sensors and optical chips, the problem of electrical signal introduction has become increasingly prominent.

[0003] The image sensor designs on the market currently generally adopt a layout with a high degree of integration, that is, the image area and the electrical signal window are set on the same plane. This design is relatively simple to manufacture and relatively low in cost, so it has been widely used in many application fields. However, with the continuous advancement of technology and the increasing diversification of application needs, this design has gradually exposed some limitations. In particular, when it is necessary to fit the image sensor to the optical chip to receive the optical signal emitted by the optical chip at a close distance, the problem is particularly prominent. Since the image area and the electrical signal window are located in the same plane, when the two are closely fitted, the lead-out path of the electrical signal will be severely restricted. When the distance between the two is far, the number of pixels occupied by the spot imaging increases, the noise is large, and the adjacent spots will overlap, causing crosstalk between channels. In addition, it may also cause signal interference and attenuation, which seriously affects the performance and stability of the image sensor.

[0004] Therefore, it is necessary to improve the existing image sensor and optical chip bonding packaging process.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, an object of the present invention is to provide an optoelectronic co-packaging structure and a preparation method thereof, so as to solve the problem in the prior art that the image sensor and the optical chip are bonded and co-packaged, and the lead-out path of the electrical signal is severely restricted when the optical signal emitted by the optical chip is received at a close distance, thereby increasing the difficulty of signal transmission, and possibly causing signal interference and attenuation, which seriously affects the performance of the image sensor.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an optoelectronic co-packaging structure, the preparation method comprising the following steps:

[0008] Providing an optical chip, wherein a surface of the optical chip has a grating in-coupling region and a grating out-coupling region;

[0009] A first electrical pin and a second electrical pin are formed on the surface of the optical chip, wherein the first electrical pin and the second electrical pin are connected via a first lead wire;

[0010] Forming a solder resist layer on the surface of the optical chip, wherein the solder resist layer exposes the grating coupling-in region, the grating coupling-out region, the first electrical pin and the second electrical pin;

[0011] An image sensor is provided, wherein the image sensor has an image area located at a central position and pad areas distributed along the circumference of the image area, and the pad areas are electrically connected to the optical chip;

[0012] A substrate is provided, a first gap is formed between the optical chip and the substrate, the first gap is filled with curing glue, and the curing glue is cured and heated at a high temperature to achieve connection and fixation between the optical chip and the substrate;

[0013] A cover plate is provided, on which a light window is arranged, the light window is directly opposite to the grating coupling-in area, and the cover plate is fixed on the substrate to complete the packaging of the optical chip and the image sensor.

[0014] Optionally, a micro solder bump is formed between the pad area of ​​the image sensor and the first electrical pin to achieve electrical connection between the optical chip and the image sensor through the micro solder bump, and the formation process of the micro solder bump includes one of laser ball planting technology, ultrasonic welding ball planting technology or solder paste printing ball planting technology.

[0015] Optionally, the micro solder bump is in a shape of a sphere, a cylinder, a cone, a truncated cone, or a cuboid.

[0016] Optionally, the first electrical pins are distributed circumferentially along an edge of the grating out-coupling region, and the second electrical pins are distributed circumferentially along an edge of the optical chip.

[0017] Optionally, a second lead wire insensitive to material thermal mismatch is provided between the substrate and the second electrical pin, so as to realize electrical connection between the optical chip and the substrate by welding.

[0018] Optionally, the substrate includes one of a glass substrate, a semiconductor substrate, a polymer substrate or a ceramic substrate that is thermally compatible with the optical chip.

[0019] The present invention also provides an optoelectronic co-packaging structure, the optoelectronic co-packaging structure comprising:

[0020] The substrate is located at the bottom layer of the co-package structure and is used to provide mechanical strength support;

[0021] A cover plate, wherein a light window is provided on the cover plate, and the cover plate is connected to the base plate and encloses a receiving space with the base plate;

[0022] An optical chip, wherein the optical chip is located in the accommodation space and forms a first gap with the substrate, and a surface of the optical chip has a grating coupling-in region and a grating coupling-out region, and the grating coupling-in region is arranged opposite to the optical window;

[0023] Curing glue, the curing glue is filled in the first gap to ensure a fixed connection between the optical chip and the substrate;

[0024] A solder resist layer, the solder resist layer being located on the optical chip, the solder resist layer exposing the grating coupling-in region and the grating coupling-out region;

[0025] An image sensor is located above the optical chip and is electrically connected to the optical chip. The image sensor has an image area located at a central position and a pad area distributed circumferentially along the image area. The image area is arranged opposite to the grating coupling-out area.

[0026] Optionally, a first electrical pin and a second electrical pin are further provided on the surface of the optical chip, the first electrical pin is distributed circumferentially along the edge of the grating out-coupling region, the second electrical pin is distributed circumferentially along the edge of the optical chip, and the first electrical pin and the second electrical pin are connected by a first lead.

[0027] Optionally, the solder resist layer also exposes the first electrical pin and the second electrical pin, and a micro solder bump is provided between the first electrical pin and the pad area of ​​the image sensor to achieve electrical connection between the optical chip and the image sensor, and a second lead is provided between the second electrical pin and the substrate to achieve electrical connection between the optical chip and the substrate.

[0028] Optionally, the micro solder bumps include one of gold balls, copper balls, tin balls or tin-silver-copper alloy solder balls, and the diameter of the micro solder bumps ranges from 18 to 30 μm.

[0029] As described above, the optoelectronic co-packaging structure and preparation method thereof of the present invention have the following beneficial effects compared with the prior art: the fan-out process is used to complete the solder ball connection between the optical chip and the image sensor, thereby realizing large-scale and high-density optoelectronic co-packaging of the optical chip and the image sensor, and being able to control the distance between the image area of ​​the image sensor and the grating coupling area of ​​the optical chip to be within 30 μm, thereby ensuring that the image sensor and the optical chip are in close contact to receive the optical signal of the optical chip, while the electrical signal of the image sensor can also be led out to the substrate through the second lead, effectively reducing the difficulty of signal transmission between the optical chip and the image sensor and other devices. In addition, the optoelectronic co-packaging structure is relatively simple, has a low preparation cost, and can improve the yield and service life of the finished optoelectronic co-packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shown is a process flow chart of the method for preparing the optoelectronic co-packaging structure of the present invention.

[0031] Figure 2 Shown is a schematic diagram of the top view of the optical chip in the optoelectronic co-packaging structure of the present invention.

[0032] Figure 3 It is a schematic diagram of a top view of the structure of forming a first electrical pin and a second electrical pin in the optoelectronic co-packaging structure of the present invention.

[0033] Figure 4 It is a schematic diagram of the top view of the structure after the solder resist layer is formed in the optoelectronic co-packaging structure of the present invention.

[0034] Figure 5 Shown is a schematic diagram of the top view of the image sensor in the optoelectronic co-packaging structure of the present invention.

[0035] Figure 6 It shows a cross-sectional structural schematic diagram of the coupling between the image sensor and the optical chip in the optoelectronic co-packaging structure of the present invention.

[0036] Figure 7 It shows a schematic diagram of the structure of coupling the optical chip and the substrate in the optoelectronic co-packaging structure of the present invention.

[0037] Figure 8 Shown is a schematic cross-sectional structure diagram of the optoelectronic co-packaging structure formed by the present invention.

[0038] Component number description

[0039] 10. Optical chip; 101. Grating coupling-in region; 102. Grating coupling-out region; 11. First electrical pin; 12. Second electrical pin; 13. First lead; 14. Image sensor; 141. Image region; 142. Micro solder bump; 15. Substrate; 16. Second lead; 17. Curing glue; 18. Cover; 181. Light window; 19. Solder mask; S1 to S6, steps. DETAILED DESCRIPTION

[0040] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0041] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] See also Figures 1 to 8 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle", "first", "second", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0043] Embodiment 1

[0044] This embodiment provides a method for preparing an optoelectronic co-packaging structure. Figure 1 As shown, it is shown as a preparation process flow chart of the preparation method, comprising the following steps:

[0045] S1: providing an optical chip 10, wherein a surface of the optical chip 10 has a grating in-coupling region 101 and a grating out-coupling region 102;

[0046] S2: forming a first electrical pin 11 and a second electrical pin 12 on the surface of the optical chip 10, wherein the first electrical pin 11 and the second electrical pin 12 are connected via a first lead 13;

[0047] S3: forming a solder resist layer 19 on the surface of the optical chip 10, wherein the solder resist layer 19 exposes the grating coupling-in region 101, the grating coupling-out region 102, the first electrical pin 11 and the second electrical pin 12;

[0048] S4: providing an image sensor 14, wherein the image sensor 14 has an image area 141 located at a central position and pad areas distributed circumferentially along the image area 141, wherein the pad areas are electrically connected to the optical chip 10;

[0049] S5: providing a substrate 15, wherein a first gap is formed between the optical chip 10 and the substrate 15, wherein the first gap is filled with a curing adhesive 17, and the curing adhesive 17 is cured and heated at a high temperature to achieve connection and fixation between the optical chip 10 and the substrate 15;

[0050] S6: providing a cover plate 18 , on which a light window 181 is disposed, the light window 181 is directly opposite to the grating coupling region 101 , and the cover plate 18 is fixed on the substrate 15 to complete the packaging of the optical chip 10 and the image sensor 14 .

[0051] The following is a further introduction to the preparation method of the optoelectronic co-packaging structure in conjunction with the accompanying drawings, as follows:

[0052] In step S1, see Figure 1 and Figure 2 , an optical chip 10 is provided, wherein a surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102 .

[0053] In this embodiment, the semiconductor wafer is cut along the scribe line area on the semiconductor wafer, and several optical chip 10 areas are separated to form several individual optical chips 10. In the above process, the individual separation of the optical chips 10 is achieved and it can be ensured that the optical chips 10 will not be contaminated by pollutants generated during the cutting process, and the integrity and reliability of the circuit functions of the optical chips 10 can be ensured.

[0054] Specifically, Figure 2As shown, it is a schematic diagram of a top view of the optical chip 10, wherein the surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102, wherein the grating coupling-in region 101 is used to couple light into the optical chip 10, and the grating coupling-out region 102 is used to couple image light conducted in the optical chip 10 out to the image sensor 14, and an optical waveguide formed by optical bonding technology is arranged between the grating coupling-in region 101 and the grating coupling-out region 102, so that the signal transmission path between the adjacent grating coupling-in region 101 and the grating coupling-out region 102 is no longer metal, but an optical waveguide. Optionally, the shape of the optical waveguide can be a straight line, an arc, or other shapes.

[0055] In step S2, see Figure 1 and Figure 3 A first electrical pin 11 and a second electrical pin 12 are formed on the surface of the optical chip 10 , and the first electrical pin 11 and the second electrical pin 12 are connected via a first lead 13 .

[0056] Specifically, Figure 3 As shown, in this embodiment, a first electrical pin 11 and a second electrical pin 12 adapted to be electrically connected to the first electrical pin 11 are formed on the surface of the optical chip 10, wherein the first electrical pin 11 and the second electrical pin 12 are both made by thin film technology, and the first electrical pin 11 and the second electrical pin 12 are provided with a first lead 13, and the first electrical pin 11 and the second electrical pin 12 are electrically connected by the first lead 13, and the electrical connection between the first electrical pin 11 and the second electrical pin 12 is realized by the first lead 13. On the one hand, the wire bonding technology is mature and can save packaging costs, and on the other hand, the packaging problem caused by thermal mismatch of the packaging structure can be avoided. Optionally, the material of the first electrical pin 11 and the second electrical pin 12 is a material with excellent electrical conductivity. In this embodiment, the material of the first electrical pin 11 and the second electrical pin 12 is a copper alloy. Of course, in other embodiments, the material of the first electrical pin 11 and the second electrical pin 12 can also be selected from other suitable metal materials.

[0057] In other embodiments, the first electrical pins 11 are distributed circumferentially along the edge of the grating outcoupling region 102, and the second electrical pins 12 are distributed circumferentially along the edge of the optical chip 10. Through the above arrangement, when the image sensor 14 is bonded in the subsequent process, the distance between the pad area of ​​the image sensor 14 and the first electrical pin 11 of the optical chip 10 can be shortened, thereby improving the signal transmission speed and reducing the volume of the packaging structure.

[0058] In step S3, see Figure 1 and Figure 4A solder resist layer 19 is formed on the surface of the optical chip 10 , and the solder resist layer 19 exposes the grating coupling-in region 101 , the grating coupling-out region 102 , the first electrical pin 11 and the second electrical pin 12 .

[0059] like Figure 4 As shown, a solder resist layer 19 is formed on the surface of the optical chip 10, and the solder resist layer 19 reveals the grating coupling-in region 101, the grating coupling-out region 102, the first electrical pin 11, and the second electrical pin 12. In this embodiment, the process of forming the solder resist layer 19 includes one of a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process; the solder resist layer 19 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer. Optionally, after forming the solder resist layer 19, the process also includes a process of flattening the solder resist layer 19. The flattening process can maintain a suitable thickness of the packaging structure, which is beneficial to reducing the volume of the packaging structure and improving the packaging quality.

[0060] Specifically, in this embodiment, the process of forming the solder resist layer 19 is as follows: after silk-screening the solder resist ink on the surface of the optical chip 10, it is sequentially subjected to pre-curing, exposure, development and thermal curing treatments to solidify the solder resist ink into the solder resist layer 19, thereby coating a layer on the circuits and pins that do not require soldering to prevent bridging between circuits during soldering, provide a permanent electrical environment and a protective layer against chemical corrosion, and at the same time beautify the appearance.

[0061] In step S4, see Figure 1 , Figure 5 and Figure 6 , an image sensor 14 is provided, wherein the image sensor 14 has an image area 141 located at a central position and a pad area distributed circumferentially along the image area 141 , and the pad area is electrically connected to the optical chip 10 .

[0062] Specifically, Figure 5 As shown, it is a schematic diagram of a top view of the image sensor 14. The surface of the image sensor 14 has an image area 141 and a pad area. After packaging, the image area 141 is arranged opposite to the grating out-coupling area 102, so that the image sensor 14 can receive the image light received from the grating in-coupling area 101 and transmitted to the grating out-coupling area 102. The image area 141 is located at the center of the image sensor 14, and the pad area is distributed circumferentially along the image area 141 and is arranged corresponding to the position of the first pin. Micro solder bumps 142 are formed on the pad area by laser ball planting technology, ultrasonic welding ball planting technology or solder paste printing ball planting technology. After all the micro solder bumps 142 are formed, as shown in FIG. Figure 6As shown, the pad area is electrically connected to the first electrical pin 11 through the micro solder bump 142 , thereby achieving electrical connection between the optical chip 10 and the image sensor 14 .

[0063] As an example, the shape of the micro solder bump 142 is spherical, cylindrical, conical, truncated cone, or rectangular.

[0064] Specifically, Figure 6 As shown, the shape of the micro solder bump 142 formed on the pad area can be spherical, cylindrical, conical, truncated cone, or rectangular. By making various special-shaped bumps, a structural basis is provided for researching and developing new bonding methods between the optical chip 10 and the image sensor 14.

[0065] In step S5, refer to Figure 1 and Figure 7 , a substrate 15 is provided, a first gap is formed between the optical chip 10 and the substrate 15 , the first gap is filled with a curing adhesive 17 , and the curing adhesive 17 is cured and heated at a high temperature to achieve the connection and fixation of the optical chip 10 and the substrate 15 .

[0066] As an example, the substrate 15 includes one of a glass substrate 15 , a semiconductor substrate 15 , a polymer substrate 15 or a ceramic substrate 15 thermally adapted to the optical chip 10 .

[0067] Specifically, Figure 7 As shown, the substrate 15 can be a glass substrate 15, a semiconductor substrate 15, a polymer substrate 15 or a ceramic substrate 15, and the present invention does not specifically limit its material, properties or internal structure. Preferably, in this embodiment, the substrate 15 is a ceramic substrate 15 that is thermally compatible with the optical chip 10. The accommodation space formed by the substrate 15 and the cover plate 18 can protect the packaging structure, prevent the packaging structure from being affected by the external environment during use, prevent damage to the packaging structure, and increase the service life of the packaging structure.

[0068] like Figure 7 As shown, in the process of bonding the optical chip 10 and the substrate 15, a first gap will be formed between the optical chip 10 and the substrate 15. In order to improve the strength of the packaging structure, it is necessary to fill the first gap with curing glue 17, and perform high-temperature curing and heating on the curing glue 17. The technical principle of high-temperature curing and heating is to use high-temperature hot air to heat the curing glue 17, so that the curing glue 17 in the first gap is fused under the action of the high-temperature hot air, thereby forming a larger contact area to achieve the connection and fixation between the optical chip 10 and the substrate 15.

[0069] As an example, a second lead 16 that is insensitive to material thermal mismatch is provided between the substrate 15 and the second electrical pin 12 so as to realize electrical connection between the optical chip 10 and the substrate 15 by welding.

[0070] Specifically, in order to lead the electrical signal of the image sensor 14 to an external device, a second lead 16 is required to be provided between the substrate 15 and the second electrical pin 12, wherein the second lead 16 is made of a material that is insensitive to material thermal mismatch. Then, one end of the second lead 16 is welded to the second electrical pin 12 by welding, and the other end of the second lead 16 is welded to the substrate 15, so as to realize the electrical connection between the optical chip 10 and the substrate 15 and avoid thermal mismatch problems in the packaging structure.

[0071] In step S6, refer to Figure 1 and Figure 8 A cover plate 18 is provided, on which a light window 181 is provided. The light window 181 is opposite to the grating coupling region 101 . The cover plate 18 is fixed on the substrate 15 to complete the packaging of the optical chip 10 and the image sensor 14 .

[0072] Specifically, Figure 8 As shown, a light window 181 is provided on the cover plate 18, and the light window 181 is arranged opposite to the grating coupling area 101, so that light can be coupled into the grating coupling area 101 of the optical chip 10 through the light window 181. After the optical chip 10 and the substrate 15 are bonded, the cover plate 18 is fixed on the substrate 15, thereby completing the optoelectronic co-packaging of the optical chip 10 and the image sensor 14.

[0073] In a method for preparing an optoelectronic co-packaging structure of the present embodiment, a fan-out process is used to complete the connection between the micro solder bumps 142 of the optical chip 10 and the image sensor 14, thereby realizing large-scale and high-density optoelectronic co-packaging of the optical chip 10 and the image sensor 14, and being able to control the distance between the image area 141 of the image sensor 14 and the grating coupling area 102 of the optical chip 10, so as to ensure that the image sensor 14 and the optical chip 10 are in close proximity to receive the optical signal of the optical chip 10, and also ensure that the electrical signal of the image sensor 14 is led out to the substrate 15 through the second lead 16, thereby effectively reducing the difficulty of signal transmission between the optical chip 10 and the image sensor 14 and other devices.

[0074] Embodiment 2

[0075] This embodiment provides an optoelectronic co-packaging structure including: Figure 8As shown, it is a schematic diagram of the cross-sectional structure of an optoelectronic co-packaging structure, and the optoelectronic co-packaging structure includes: a substrate 15, which is located at the bottom layer of the co-packaging structure and is used to provide mechanical strength support; a cover plate 18, on which a light window 181 is provided, and the cover plate 18 is connected to the substrate 15 and encloses a receiving space with the substrate 15; an optical chip 10, which is located in the receiving space and forms a first gap with the substrate 15, and the surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102, and the grating coupling-in region 101 is arranged opposite to the light window 181; a curing glue 17, which is provided on the optical chip 10; and a curing glue 18, which is provided on the optical chip 10. The curing glue 17 is filled in the first gap to ensure a fixed connection between the optical chip 10 and the substrate 15; a solder resist layer 19, the solder resist layer 19 is located on the optical chip 10, and the solder resist layer 19 exposes the grating coupling-in area 101 and the grating coupling-out area 102; an image sensor 14, the image sensor 14 is located above the optical chip 10 and is electrically connected to the optical chip 10, and the image sensor 14 has an image area 141 located at the center and a pad area distributed circumferentially along the image area 141, and the image area 141 is arranged opposite to the grating coupling-out area 102.

[0076] As an example, a first electrical pin 11 and a second electrical pin 12 are also provided on the surface of the optical chip 10, the first electrical pin 11 is distributed circumferentially along the edge of the grating coupling-out region 102, the second electrical pin 12 is distributed circumferentially along the edge of the optical chip 10, and the first electrical pin 11 and the second electrical pin 12 are connected by a first lead 13.

[0077] Optionally, the material of the first electrical pin 11 and the second electrical pin 12 is a material with excellent electrical conductivity. In this embodiment, the material of the first electrical pin 11 and the second electrical pin 12 is a copper alloy. Of course, in other embodiments, the material of the first electrical pin 11 and the second electrical pin 12 can also be other suitable metal materials.

[0078] In this embodiment, the first electrical pins 11 are distributed along the circumferential edge of the grating outcoupling region 102, and the second electrical pins 12 are distributed along the circumferential edge of the optical chip 10. Through the above arrangement, when the image sensor 14 is bonded in the subsequent process, the distance between the pad area of ​​the image sensor 14 and the first electrical pin 11 of the optical chip 10 can be shortened, thereby improving the signal transmission speed and reducing the volume of the packaging structure.

[0079] As an example, the solder resist layer 19 also exposes the first electrical pin 11 and the second electrical pin 12, and a micro solder bump 142 is provided between the first electrical pin 11 and the pad area of ​​the image sensor 14 to realize the electrical connection between the optical chip 10 and the image sensor 14, and a second lead 16 is provided between the second electrical pin 12 and the substrate 15 to realize the electrical connection between the optical chip 10 and the substrate 15.

[0080] Specifically, in addition to exposing the grating coupling-in region 101 and the grating coupling-out region 102, the solder resist layer 19 also exposes the first electrical pin 11 and the second electrical pin 12, so that the first electrical pin 11 can be electrically connected to the pad region of the image sensor 14. The flattened solder resist layer 19 can also maintain a suitable thickness of the package structure, which is beneficial to reducing the volume of the package structure and improving the package quality. Micro solder bumps 142 are also provided on the pad region to electrically connect the image sensor 14 to the optical chip 10 through the micro solder bumps 142. In order to lead the electrical signal of the image sensor 14 to an external device, a second lead 16 is required to be provided between the substrate 15 and the second electrical pin 12, wherein the second lead 16 is made of a material that is insensitive to material thermal mismatch. Then, one end of the second lead 16 is welded to the second electrical pin 12 by welding, and the other end of the second lead 16 is welded to the substrate 15, so as to realize the electrical connection between the optical chip 10 and the substrate 15 and avoid thermal mismatch problems in the packaging structure.

[0081] As an example, the micro solder bump 142 includes a gold ball, a copper ball, a tin ball or a tin-silver-copper alloy solder ball, and the diameter of the tin-silver-copper alloy solder ball ranges from 18 to 30 μm.

[0082] Specifically, in the present embodiment, the micro solder bump 142 formed on the pad area is spherical in shape, and its diameter ranges from 18 to 30 μm, for example: 18 μm, 24 μm or 30 μm, and the micro solder bump 142 includes one of a gold ball, a copper ball, a tin ball or a tin-silver-copper alloy solder ball to achieve better electrical connection between the first electrical pin 11 and the pad area.

[0083] In summary, compared with the prior art, the optoelectronic co-packaging structure and preparation method of the present invention use a fan-out process to complete the micro solder bump connection at the pad area of ​​the optical chip and the image sensor during the packaging process, thereby realizing large-scale and high-density optoelectronic co-packaging of the optical chip and the image sensor, and controlling the distance between the image area of ​​the image sensor and the grating coupling area of ​​the optical chip to be within 30 μm. This can ensure that the image sensor and the optical chip are in close contact to receive the optical signal of the optical chip, and can also ensure that the electrical signal of the image sensor is led out to the substrate through the second lead, thereby effectively reducing the difficulty of signal transmission between the optical chip and the image sensor and other devices. In addition, the optoelectronic co-packaging structure is relatively simple and has a low preparation cost, thereby improving the yield and service life of the finished optoelectronic co-packaging structure. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an optoelectronic co-packaging structure, characterized in that: The preparation method comprises the following steps: Providing an optical chip, wherein a surface of the optical chip has a grating in-coupling region and a grating out-coupling region; A first electrical pin and a second electrical pin are formed on the surface of the optical chip, wherein the first electrical pin and the second electrical pin are connected via a first lead wire; Forming a solder resist layer on the surface of the optical chip, wherein the solder resist layer exposes the grating coupling-in region, the grating coupling-out region, the first electrical pin and the second electrical pin; An image sensor is provided, wherein the image sensor has an image area located at a central position and pad areas distributed along the circumference of the image area, and the pad areas are electrically connected to the optical chip; A substrate is provided, a first gap is formed between the optical chip and the substrate, the first gap is filled with curing glue, and the curing glue is cured and heated at a high temperature to achieve connection and fixation between the optical chip and the substrate; A cover plate is provided, on which a light window is arranged, the light window is directly opposite to the grating coupling-in area, and the cover plate is fixed on the substrate to complete the packaging of the optical chip and the image sensor.

2. The method for preparing the optoelectronic co-packaging structure according to claim 1, characterized in that: A micro solder bump is formed between the pad area of ​​the image sensor and the first electrical pin to achieve electrical connection between the optical chip and the image sensor through the micro solder bump. The formation process of the micro solder bump includes one of laser ball planting technology, ultrasonic welding ball planting technology or solder paste printing ball planting technology.

3. The method for preparing the optoelectronic co-packaging structure according to claim 2, characterized in that: The shape of the micro solder bump is one of sphere, cylinder, cone, truncated cone and cuboid.

4. The method for preparing the optoelectronic co-packaging structure according to claim 1, characterized in that: The first electrical pins are distributed along the circumference of the edge of the grating out-coupling region, and the second electrical pins are distributed along the circumference of the edge of the optical chip.

5. The method for preparing the optoelectronic co-packaging structure according to claim 1, characterized in that: A second lead wire which is insensitive to thermal mismatch of materials is provided between the substrate and the second electrical pin, so as to realize electrical connection between the optical chip and the substrate by welding.

6. The method for preparing the optoelectronic co-packaging structure according to claim 1, characterized in that: The substrate includes one of a glass substrate, a semiconductor substrate, a polymer substrate or a ceramic substrate thermally matched with the optical chip.

7. An optoelectronic co-packaging structure, characterized in that: The optoelectronic co-packaging structure comprises: The substrate is located at the bottom layer of the co-package structure and is used to provide mechanical strength support; A cover plate, wherein a light window is provided on the cover plate, and the cover plate is connected to the base plate and encloses a receiving space with the base plate; An optical chip, wherein the optical chip is located in the accommodation space and forms a first gap with the substrate, and a surface of the optical chip has a grating coupling-in region and a grating coupling-out region, and the grating coupling-in region is arranged opposite to the optical window; Curing glue, the curing glue is filled in the first gap to ensure a fixed connection between the optical chip and the substrate; A solder resist layer, the solder resist layer being located on the optical chip, the solder resist layer exposing the grating coupling-in region and the grating coupling-out region; An image sensor is located above the optical chip and is electrically connected to the optical chip. The image sensor has an image area located at a central position and a pad area distributed circumferentially along the image area. The image area is arranged opposite to the grating coupling-out area.

8. The optoelectronic co-packaging structure according to claim 7, characterized in that: A first electrical pin and a second electrical pin are also provided on the surface of the optical chip. The first electrical pin is distributed circumferentially along the edge of the grating outcoupling area, and the second electrical pin is distributed circumferentially along the edge of the optical chip. The first electrical pin and the second electrical pin are connected by a first lead.

9. The optoelectronic co-packaging structure according to claim 8, characterized in that: The solder resist layer also exposes the first electrical pin and the second electrical pin, and a micro solder bump is provided between the first electrical pin and the pad area of ​​the image sensor to achieve electrical connection between the optical chip and the image sensor, and a second lead is provided between the second electrical pin and the substrate to achieve electrical connection between the optical chip and the substrate.

10. The optoelectronic co-packaging structure according to claim 9, characterized in that: The micro solder bumps include one of gold balls, copper balls, tin balls or tin-silver-copper alloy solder balls, and the diameter of the micro solder bumps ranges from 18 to 30 μm.

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