Drive circuit for frequency converter load

Abstract

The invention provides a drive circuit for a frequency converter load, and relates to the technical field of frequency converters. Comprising a control module, a driving module, a power supply module, a signal acquisition and processing module and a load matching module, and the load matching module has impedance matching, tuning matching and shaping filtering functions and has universal adaptive driving capability for most types of motors and ultrasonic transducers; the power supply module adopts a high-speed MOS tube, the driving module adopts a high-speed driving chip to adapt to the high-speed MOS tube, the frequency application range is large, the DDS waveform generation module is adopted to realize PWM wave output of different frequencies, the change step length of the frequency is extremely low, and the change is smooth; a variable step size algorithm and an LADRC algorithm are combined, and the working resonant frequency of the variable frequency load can be automatically and accurately locked within a certain frequency range. A linear LADRC algorithm is adopted, behaviors of a driving circuit are adjusted through real-time measurement and estimation, and the method can adapt to changes and uncertainty of a motor and an ultrasonic transducer in a complex working environment.

Description

Technical Field

[0001] The invention belongs to the technical field of frequency converters, and in particular relates to a drive circuit for a frequency converter load. Background Art

[0002] The power consumption of variable frequency loads changes with the driving frequency. This feature is often used in the motor field and ultrasonic field. In the application, the motor can adjust the torque and speed of the motor by changing the power supply frequency, so that the motor works at the optimal power point. As the main component that enables the ultrasonic vibrator to generate ultrasonic waves, the ultrasonic transducer uses the inverse piezoelectric effect of piezoelectric ceramics to convert electrical energy into mechanical energy. When the ultrasonic vibrator works near its resonant frequency, its working efficiency is the highest. When it is affected by external working conditions and other factors, its resonant frequency will change, thereby greatly reducing the working efficiency. Existing driving power supplies often use the maximum current method or phase comparison method to adjust the output frequency. These methods have different disadvantages when used alone. The maximum current method will cause problems such as heating and power supply noise under conditions where the load changes frequently, causing the performance of the transducer to deteriorate or even damage. When the phase comparison method faces a frequency converter with multiple resonance points, it will mistakenly track other unwanted resonance points and cannot achieve the ideal frequency tracking effect. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention provides a drive circuit for a frequency converter load, which can automatically adjust the frequency of the output drive signal and realize automatic frequency scanning and frequency chasing within a wider frequency range, so as to match with motors or ultrasonic transducers of different models, thereby realizing the operation of the motor at an optimal speed and torque, and also enabling the ultrasonic transducer to operate smoothly at its resonant frequency, thereby solving the deficiencies of the existing variable frequency load drive circuits and frequency chasing methods.

[0004] A drive circuit for a frequency converter load, comprising: a control module, a drive module, a power module, a signal acquisition and processing module and a load matching module;

[0005] The control module communicates with the driving module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the driving frequency according to the output information, and outputs a control signal to the driving module according to the driving frequency to drive the power module, so as to realize that the inverter load always keeps working at its resonant frequency; the output information includes phase difference information and peak current information;

[0006] The driving module is used to isolate the control module and the power module to prevent the control module from being damaged by a large current, and at the same time receives a control signal sent by the control module and performs level conversion on the control signal to realize driving of the power module;

[0007] The power supply module is used to provide adaptive voltages for the control module, the drive module, and the signal acquisition and processing module through different voltage conversion circuits, and at the same time convert the 220V, 50Hz mains electricity into an AC voltage with adjustable frequency and peak value and output it to the inverter load through the load matching module to meet the drive requirements of the inverter load;

[0008] The signal acquisition and processing module is used to collect the current signal and voltage signal on both sides of the inverter load, filter and amplify the current signal and voltage signal, obtain the phase difference information of the amplified current signal and voltage signal and output it to the control module in the form of PWM wave duty cycle, and obtain the peak current information and output it to the control module in the form of high level;

[0009] The load matching module is used to achieve tuning matching and impedance matching between the power module and the inverter load;

[0010] Furthermore, the control module includes an MCU main control chip and a DDS waveform generation module;

[0011] The MCU main control chip is used to receive the phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through the LADRC algorithm and the variable step size algorithm, and output it to the DDS waveform generation module, and is also used to control the switch of the relay in the load matching module, thereby controlling the selection of the matching inductor and the matching capacitor in the load matching module;

[0012] The DDS waveform generation module is used to generate a control signal according to the driving frequency calculated by the MCU main control chip and output it to the driving module; the control signal is a square wave;

[0013] Furthermore, the driving frequency is calculated using a variable step size algorithm and a LADRC algorithm. Specifically, the optimal driving frequency is firstly determined using a variable step size algorithm based on the peak current information, and then the degree of deviation of the inverter load frequency is determined based on the phase difference information collected in real time, and the LADRC algorithm is used to calculate the change in the driving frequency that needs to be adjusted, thereby determining the current optimal driving frequency;

[0014] Furthermore, the power supply module includes a rectifier filter circuit, a Buck step-down circuit, an inverter circuit and a peripheral power supply circuit;

[0015] The rectifier filter circuit is used to convert the AC voltage into a pulsating DC voltage through a rectifier bridge composed of four diodes, and then provide additional current to compensate for the ripple in the DC voltage through the process of storing and releasing charges in the filter capacitor and input it into the Buck step-down circuit;

[0016] The Buck step-down circuit is used to control the conduction time of the MOS tube so that the input DC voltage is regulated and filtered through the inductor and capacitor under the control of the MOS tube, thereby reducing the voltage value of the DC voltage output by the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage;

[0017] The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into an AC voltage and output it to the load matching module;

[0018] The peripheral power supply circuit is used to provide the control module and the driving module with the driving voltage required for enabling, and the negative voltage required by the operational amplifier in the signal acquisition and processing module through the conversion circuit;

[0019] Furthermore, the driving module includes two parts, namely, a Buck driving circuit and an inverter driving circuit. The Buck driving circuit and the inverter driving circuit are used to drive the Buck step-down circuit in the power module and the MOS tube in the inverter circuit respectively. The Buck driving circuit and the inverter driving circuit both include an optocoupler isolation part and a MOS tube driving part. The optocoupler isolation part is used to isolate the control module from the power module. The MOS tube driving part converts the control signal output by the control module into a level suitable for driving the MOS tube in the power module.

[0020] The signal acquisition and processing module includes a sampling circuit, a bandpass filtering circuit, a signal amplification-peak monitoring circuit and a phase detection circuit;

[0021] The sampling circuit includes a plurality of sampling resistors for collecting current signals and voltage signals at both ends of the inverter load and transmitting them to the bandpass filter circuit;

[0022] The bandpass filter circuit is used to remove interfering harmonics in the collected current signal and voltage signal and input the filtered current signal and voltage signal into the signal amplification circuit;

[0023] Further, the bandpass filter circuit is a SK active bandpass filter, which includes a SK second-order active low-pass filter and a SK second-order active high-pass filter;

[0024] The signal amplification-peak monitoring circuit comprises a signal amplification circuit and a peak detection circuit;

[0025] The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit;

[0026] The peak detection circuit includes a rectifier diode, an energy storage capacitor and a discharge resistor, which are used to obtain peak current information and transmit it to the control module for analysis;

[0027] The phase detection circuit includes a voltage follower, a zero-crossing comparator, a D flip-flop and an XOR gate, which are used to obtain the lead-lag relationship between the voltage signal and the current signal and the phase difference information between the two, thereby completing the digital phase detection function;

[0028] The load matching module includes a tuning matching module and an impedance matching module;

[0029] The tuning and matching module selects the LC matching mode, and realizes the tuning and matching by controlling the opening and closing of different relays and switching the matching inductor and the matching capacitor;

[0030] The impedance matching module selects a transformer matching mode and performs impedance transformation by changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer to achieve impedance matching.

[0031] Beneficial effects of the present invention:

[0032] (1) The load matching module of the present invention has impedance matching, tuning matching and shaping filtering functions, and has a universally adaptable driving capability for most types of motors and ultrasonic transducers.

[0033] (2) The power module of the present invention adopts a high-speed MOS tube, and the driving module adopts a high-speed driving chip to adapt to the high-speed MOS tube. The frequency application range is large, and a DDS waveform generation module is used to realize PWM wave output of different frequencies. The frequency change step is extremely low and the change is smooth.

[0034] (3) The present invention combines the variable step size algorithm and the LADRC algorithm, which can automatically and accurately lock the working resonant frequency of the variable frequency load within a certain frequency range.

[0035] (4) The linear LADRC algorithm adopted in the present invention does not rely on an accurate system model, but adjusts the behavior of the driving circuit through real-time measurement and estimation. It can adapt to the changes and uncertainties in the complex working environment of the motor and ultrasonic transducer, including changes in their own parameters and the influence of external factors. It is simple to implement and easy to debug and optimize. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 1 is a general design diagram of a drive circuit for a frequency converter load in an embodiment of the present invention;

[0037] Figure 2 Flow chart of the variable step size algorithm in an embodiment of the present invention;

[0038] Figure 3 It is a structural diagram of the LADRC controller in an embodiment of the present invention;

[0039] Figure 4is a circuit design diagram of a control module in an embodiment of the present invention;

[0040] Figure 5 is a circuit design diagram of a driving module in an embodiment of the present invention;

[0041] Figure 6 is a circuit design diagram of a power module in an embodiment of the present invention;

[0042] Figure 7 The circuit design diagram of the signal acquisition and processing module in the embodiment of the present invention;

[0043] Figure 8 It is an overall design diagram of the load matching module in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0045] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0046] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0047] like Figure 1 As shown, a driving circuit for a frequency converter load includes: a control module, a driving module, a power module, a signal acquisition and processing module and a load matching module, to realize frequency sweeping and automatic frequency tracking test of the load;

[0048] In this embodiment, the driving module, the power module and the signal acquisition and processing module are integrated into a PCB board, and the control module and the load matching module are inserted into the PCB board through pin headers and connected with other modules.

[0049] The control module communicates with the drive module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the drive frequency according to the output information, and outputs a control signal to the drive module according to the drive frequency to drive the power module, and then passes through the load matching module to keep the variable frequency load motor at the optimal power or the transducer running smoothly at the maximum active power mode at the series resonant frequency. The output information includes phase difference information and peak current information.

[0050] In this embodiment, the present invention includes two functions, namely, the peak signal frequency sweep based on the variable step length algorithm and the frequency chasing function of the phase detection frequency locking algorithm of the LADRC algorithm. The variable step length algorithm can lock the resonance point where the peak current signal is the largest in a relatively far frequency range, and can perform frequency sweep at an initial set frequency far from the resonance frequency; after completing the initial frequency sweep, the drive circuit automatically performs the frequency chasing function, and judges the frequency deviation degree of the transducer during operation by real-time detection of the current and voltage phase difference of the inverter load, and calculates the frequency change amount that needs to be adjusted according to the LADRC algorithm, so that the motor and transducer always remain at the resonance point and operate at maximum power.

[0051] Variable step size algorithm, such as Figure 2 As shown, it includes two modes: large-step frequency sweep and small-step frequency sweep. First, determine the range of the frequency sweep, that is, the upper and lower limits of the frequency. The program first enters the state of state = 1 (large-step frequency sweep mode), collects the peak current information transmitted by the signal acquisition and processing module, and if the peak current information is less than the first target threshold, increases the frequency of the output control signal with a large step; if the peak current information is greater than the first target threshold, enters the state of state = 2 (small-step frequency sweep mode), continues to read the peak current information, if the collected peak current information is higher than the peak current information collected last time, takes the frequency of the higher peak current information as the pre-selected frequency, and increases the frequency of the output control signal with a small step; If the collected peak current information is lower than the peak current information collected last time, the preselected frequency remains unchanged and the program enters state = 3; the difference between the peak current information corresponding to the preselected frequency and the peak current information when entering state = 3 is compared with the second target threshold. If the difference between the peak current information corresponding to the preselected frequency and the peak current information when entering state = 3 is higher than the second target threshold, the program ends, and the preselected frequency is the optimal frequency of the inverter load, and its corresponding peak current information is the maximum value within the sweep frequency range. Otherwise, the frequency of the control signal continues to be adjusted using the large step sweep frequency and small step sweep frequency modes.

[0052] Compared with the traditional PI algorithm, the LADRC algorithm has the characteristics of small overshoot, high accuracy, strong anti-interference ability, and is not heavily dependent on the model. It contains three modules: linear tracking differentiator (LTD), linear state observer (LESO) and linear state error feedback (LSEF). First, the desired input signal is input into the LTD for smoothing and a transition process is designed to obtain the tracking signal and generate the differential signal of the desired signal. At the same time, LESO uses the modeling information of the controlled object and the external disturbance to convert and expand the internal and external disturbances of the controlled object into a new high-order state variable to extract the high-order disturbance signal. Finally, LSEF receives the tracking signal from LTD and the observed state variables of each order obtained by LESO for calculation. The linear function is then used to compensate the total disturbance to the controlled object in real time to achieve precise control. Such as Figure 3 As shown, the phase detection first-order LADRC controller is as follows:

[0053]

[0054] In the formula, e is the error between the detected value and the observed value, z1 and z2 are the observed values ​​of the state quantity, and β 01 and β 02 is the feedback gain coefficient of the linear state observer, is the output of the controlled object, Δf is the control quantity output of the LADRC controller, b0 is the estimated value of the system gain, u0 is the control quantity output of the LSEF, and K p is the bandwidth of the LADRC controller, x1 is the state quantity of the phase difference, is the rate of change of the observed value of the state quantity;

[0055] The control module includes an MCU main control chip and a DDS waveform generation module;

[0056] The MCU main control chip is used to receive the phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through the variable step size algorithm and the LADRC algorithm, and output it to the DDS waveform generation module to ensure that it outputs a control signal of a suitable frequency. It is also used to control the switch of the relay in the load matching module, thereby controlling the selection of the matching inductor and the matching capacitor in the load matching module;

[0057] The DDS waveform generation module is composed of a digital-to-analog converter, a high-speed comparator and a programmable system, and is used to generate a control signal with a pure spectrum and programmable frequency according to the driving frequency calculated by the MCU main control chip and output it to the driving module; the control signal is a square wave;

[0058] like Figure 4As shown, in this embodiment, the MCU main control chip selects STM32F407. Compared with ordinary single-chip microcomputer chips, this chip has strong computing power and better performance. Its main frequency is 168MHz, and it has 100 pins, three 12-bit ADCs, two DACs, one RTC and fourteen general timers, and also has communication interfaces such as USART; the DDS waveform generation module adopts the AD9850 chip, whose maximum operating frequency is 125MHz, and uses a 32-bit frequency control word. The maximum frequency resolution is 0.0291Hz, which can meet the accuracy requirements of frequency tracking.

[0059] The driving module is used to isolate the control module and the power module to prevent the control module from being damaged by a large current, and at the same time receives a control signal sent by the control module and performs level conversion on the control signal to realize driving of the power module;

[0060] like Figure 5 As shown, the driving module includes two parts, a Buck driving circuit and an inverter driving circuit. The Buck driving circuit and the inverter driving circuit are used to drive the MOS tubes in the Buck step-down circuit and the inverter circuit respectively. The Buck driving circuit and the inverter driving circuit both include an optocoupler isolation part and a MOS tube driving part. In this embodiment, the optocoupler isolation chip used in the optocoupler isolation part is HCPL-2630, which integrates a light-emitting diode and a phototransistor, and has a power supply voltage of 5V. It can effectively isolate the input and output circuits to prevent electrical noise, high voltage or other interference at the input end from affecting the output end, thereby improving the stability and safety of the driving circuit for the inverter load. It has two channels, and the Buck driving circuit receives a PWM signal and uses one of the channels; the MOS tube driving chip used in the MOS tube driving part is IR2113S, which can withstand a voltage of up to 600V, has a fast rise and fall time, a limit frequency of 500kHz, a power supply voltage of 12V, and includes two logic input pins for receiving the signal output by the optocoupler isolation chip. The Buck drive circuit uses the high-side output of an IR2113S to control the opening and closing of one MOS tube, and the inverter circuit uses the high and low test pins of two IR2113S to control the opening and closing of four MOS tubes. Therefore, the drive circuit module can amplify the weak control signal of the control module into an effective signal that can drive the power module.

[0061] The power supply module is used to provide adaptive voltages for the control module, the drive module, and the signal acquisition and processing module through different voltage conversion circuits, and at the same time convert the 220V, 50Hz mains electricity into an AC voltage with adjustable frequency and peak value and output it to the inverter load through the load matching module to meet the drive requirements of the inverter load;

[0062] like Figure 6As shown, the power supply module includes a rectifier and filter circuit, a Buck step-down circuit, an inverter circuit and a peripheral power supply circuit;

[0063] The rectifier filter circuit is used to convert the AC voltage into a roughly pulsating DC voltage through a rectifier bridge composed of four diodes, and then provide additional current to compensate for the ripple in the DC voltage through the process of storing and releasing charges in the filter capacitor and input it into the Buck step-down circuit to ensure that the inverter load obtains a stable DC voltage;

[0064] The Buck step-down circuit is used to control the conduction time of the MOS tube so that the input DC voltage is regulated and filtered through the inductor and capacitor under the control of the MOS tube, thereby reducing the voltage value of the DC voltage output by the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage;

[0065] The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into a frequency-controllable AC voltage and output it to the load matching module;

[0066] Specifically, it consists of four MOSFETs and four anti-parallel diodes. The MOSFETs are arranged in a bridge connection to form two pairs of symmetrical switches, each pair has two tubes, one in the upper half bridge and the other in the lower half bridge. The anti-parallel diode is used to provide a path for the current to continue to flow when the switch tube is turned off, protecting the switch tube and ensuring the normal operation of the circuit.

[0067] The peripheral power supply circuit is used to provide the control module and the drive module with the driving voltages of 12V and 5V required for enabling, and the negative voltages of -5V and -12V required by the operational amplifier in the signal acquisition and processing module through the conversion circuit;

[0068] In this embodiment, the rectifier filter circuit adopts GBJ5010 rectifier bridge, with a withstand voltage of 1kV, and has the advantages of high integration and high current load. It is composed of four diodes, which are used to provide a path so that the current continues to flow when the switch tube is turned off, ensuring the stability and efficiency of the circuit. By controlling the conduction and cutoff of the diode, the negative half cycle of the alternating current is converted into a positive half cycle to obtain a voltage close to direct current. An electrolytic capacitor is connected after the rectifier bridge to store charge and smooth the output DC voltage to reduce ripple. The electrolytic capacitor selects 680uF / 450V, which can meet the needs of higher power; the Buck step-down circuit selects STP33N60M6-VB as the switch tube, with a conduction frequency of 500kHz, low on-resistance, high current bearing capacity, and high temperature resistance, which is suitable for higher power application scenarios. When the MOS tube is turned on, the voltage source is charged through the inductor element; when the MOS tube is turned off, the energy stored in the inductor is released to the load through the diode, thereby achieving a stable step-down effect. Similarly, the full-bridge inverter part also selects STP33N60M6-VB as the switch tube, and connects a resistor and capacitor in parallel to form an absorption buffer circuit to suppress the turn-off peak of the switch tube. The diode is used to prevent the reverse electromotive force from being too high, which plays a protective role. At the same time, it allows the circuit to conduct and continue current when the switch tube is turned off.

[0069] The signal acquisition and processing module is used to collect weak current signals and weak voltage signals on both sides of the inverter load, filter and amplify the weak current signals and weak voltage signals, obtain the phase difference information of the amplified current signal and voltage signal and output it to the control module in the form of PWM wave duty cycle, and simultaneously obtain the peak current information and output it to the control module in the form of high level;

[0070] The signal acquisition and processing module includes a sampling circuit, a bandpass filtering circuit, a signal amplification-peak monitoring circuit and a phase detection circuit;

[0071] The sampling circuit includes a plurality of sampling resistors for collecting current signals and voltage signals at both ends of the inverter load and transmitting them to the bandpass filter circuit;

[0072] like Figure 7 As shown, in this embodiment, the sampling circuit adopts the resistance sampling method to ensure the accuracy of current and voltage phase acquisition. A resistor with a resistance value of 10MΩ and a resistor with a resistance value of 100kΩ are selected to be connected in parallel with the inverter load, and the voltage value across the 100kΩ is used as the load voltage signal; a resistor with a resistance value of 1 ohm is selected to be connected in series with the inverter load, and the voltage value across the resistor can be used to represent the current signal of the branch where the load is located. While acquiring accurate phase information, it avoids affecting the load power.

[0073] The bandpass filter circuit is used to remove interfering harmonics in the collected current signal and voltage signal and input the filtered current signal and voltage signal into the signal amplification circuit;

[0074] Furthermore, the bandpass filter circuit is an SK active bandpass filter, which includes an SK second-order active low-pass filter and an SK second-order active high-pass filter, and the cut-off frequency is determined by the values ​​of two resistors and a capacitor respectively.

[0075] like Figure 7 As shown, the bandpass filter circuit in this embodiment is composed of two operational amplifiers, using LM358A-SR chip and two groups of resistors and capacitors to form two active SK type second-order filters. The capacitor and resistor values ​​of the high-pass filter are C 20 =C 21 =C 24 =C 25 =1nF,R 33 =R 37 =11.2kΩ, R 34 =R 38 =5.6kΩ, cut-off frequency is 20kHz. The capacitor and resistor values ​​selected for the low-pass filter are C 18 =C 22 =1nF,C 19 =C 23 =6.8nF,R 31 =R 35 =1.5kΩ, R 32 =R 36 =1kΩ, cut-off frequency is 65kHz.

[0076] The cut-off frequency of the SK second-order active high-pass filter is:

[0077]

[0078] Where f is the cutoff frequency, R 33 ,R 35 is the resistance of the high-pass filter, C 20 ,C 21 is the capacitance of the high-pass filter;

[0079] The cut-off frequency of the SK second-order active low-pass filter is:

[0080]

[0081] In the formula, R 31 ,R 32 is the resistance of the low-pass filter, C 18 ,C 19 is the capacitance of the low-pass filter;

[0082] The signal amplification-peak monitoring circuit comprises a signal amplification circuit and a peak detection circuit;

[0083] The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit;

[0084] The proportional amplifier circuit and the differential amplifier circuit include an operational amplifier and a resistor;

[0085] In this embodiment, since the sampling circuit outputs a small signal value, the amplifier circuit needs to amplify the signal accordingly to achieve the subsequent peak detection and phase detection functions. The operational amplifier chip is LM358-SR chip, which has the advantages of low cost and strong anti-interference ability. The dual channels can be used to amplify voltage and current signals. The voltage signal is amplified in the same phase ratio. The circuit is composed of an operational amplifier and related resistor devices. 23 For R 24 and R 25 Select R 24 =35kΩ, R 25 =5kΩ, R 23 is 4.3kΩ, and the amplification factor is 8 times; the current signal is amplified by a differential amplifier circuit, which is composed of an operational amplifier and related resistor devices. 29 =R 26 =5kΩ, R 28 =R 27 =50kΩ, the amplification factor is 10 times.

[0086] The amplification ratio formula of the proportional amplification circuit is:

[0087]

[0088] Where Vout is the output voltage, Vin is the input voltage, and R 24 , R 25 Amplifier resistor.

[0089] The output value of the differential amplifier circuit is:

[0090]

[0091] In the formula, V2 and V1 are the two input signals of the operational amplifier, R 28 , R 29 Amplifier resistor.

[0092] The peak detection circuit includes a rectifier diode, an energy storage capacitor and a discharge resistor. The current signal passes through the rectifier diode. Since the rectifier diode only allows the positive half cycle of the signal to pass, the current signal becomes a pulse sequence containing the peak value of the input signal. This pulse signal passes through an energy storage capacitor. Since the energy storage capacitor is transparent to DC signals and has a barrier to AC signals, the peak value is therefore retained on the energy storage capacitor, and the peak current information is obtained and transmitted to the control module for analysis; the discharge resistor is used to release the charge on the energy storage capacitor;

[0093] The phase detection circuit described in this embodiment includes a voltage follower, a zero-crossing comparator, a D flip-flop and an XOR gate. The voltage follower uses a high-precision AD8672 operational amplifier chip to keep the voltage of the input signal unchanged, maintain the waveform stable, and can also isolate the front and rear circuits. The zero-crossing comparator is composed of an LM339 operational amplifier chip and a peripheral circuit to convert the input signal into a binary signal for subsequent processing. The D flip-flop 74LS74 and the XOR gate 74LS86 convert the two processed signals into signals that can be recognized by the main control chip. The D flip-flop outputs the state information of the phase difference. When the voltage leads the current, the output signal is set to 1; when the current leads the voltage, the output signal is set to 0. The XOR gate outputs the phase difference information, and the high-level duty cycle of the output PWM wave is the current-voltage phase difference.

[0094] The load matching module is used to achieve tuning matching and impedance matching between the power module and the inverter load, including a tuning matching module and an impedance matching module;

[0095] Tuning and matching refers to the control module controlling the opening and closing of different relays of the tuning and matching module according to the different electrical characteristics of the load, switching the matching inductor and matching capacitor to achieve appropriate values, reducing the error between the lowest impedance point and the pure resistance point of the load, and is composed of programmable inductors and programmable capacitors to improve the power factor and power efficiency. Impedance matching refers to the control of the total impedance of the circuit during the matching process to avoid excessive total impedance to ensure the output power of the power supply. For ultrasonic vibration units, a good matching system can ensure a good vibration state and increase the stability of the ultrasonic power supply.

[0096] Furthermore, the tuning and matching module selects the LC matching method, and the ultrasonic transducer is connected in series with a matching inductor and a matching capacitor. When the transducer operates at the series resonant frequency, the transducer can be equivalent to a circuit in which a resistor and a capacitor are connected in series. Therefore, a series matching inductor is required to eliminate the capacitive component of the series resonant frequency; the static capacitance may change with temperature, working time, etc., which has an adverse effect on tuning. Therefore, a matching capacitor is connected in parallel with the static capacitance to offset the impact of the static capacitance change.

[0097] like Figure 8As shown, the load matching circuit in this embodiment is composed of a programmable inductor and a programmable capacitor. In practice, a matching capacitor C1 with a value ten times that of the load equivalent static capacitance C0 is selected and connected in parallel with the load. The calculation formula of the matching inductor L1 is:

[0098]

[0099] Where L1 is the matching inductor, C0 is the static capacitance of the load, and C1 is the matching capacitor; R m is the dynamic resistance of the load, ω is the angular frequency, which indicates how fast the current and voltage signals change over time. The seven series inductance values ​​designed by the present invention are L0=1mH, L1=2mH, L2=3mH, L3=3mH, L4=3mH, L5=3mH, and L6=3mH. They can be connected in any combination, and can provide an inductance value from 0-18mH with an adjustment accuracy of 1mH; the seven parallel capacitance values ​​are C0=0.1uF, C1=0.2uF, C2=0.3uF, C3=0.4uF, C4=0.5uF, C5=0.6uF, and C6=0.7uF, which can be connected in any combination, and can provide a capacitance value from 0-0.28uF with an adjustment accuracy of 0.1uF. The combination of the two can enable the present invention to meet the needs of dynamic matching of different loads.

[0100] The impedance matching module selects the transformer matching method. When the resistance of the resistive load is equal to the internal resistance of the power supply, the load can obtain the maximum power. By changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer, the load can obtain the maximum power.

Claims

1. A drive circuit for a frequency converter load, characterized in that: It includes a control module, a drive module, a power module, a signal acquisition and processing module and a load matching module; The control module communicates with the driving module and the signal acquisition and processing module, analyzes the output information of the signal acquisition and processing module, calculates the driving frequency according to the output information, and outputs a control signal to the driving module according to the driving frequency to drive the power module, so as to realize that the inverter load always keeps working at its resonant frequency; the output information includes phase difference information and peak current information; The driving module is used to isolate the control module and the power module to prevent the control module from being damaged by a large current, and at the same time receives a control signal sent by the control module and performs level conversion on the control signal to realize driving of the power module; The power supply module is used to provide adaptive voltages for the control module, the drive module, and the signal acquisition and processing module through different voltage conversion circuits, and at the same time convert the 220V, 50Hz mains electricity into an AC voltage with adjustable frequency and peak value and output it to the inverter load through the load matching module to meet the drive requirements of the inverter load; The signal acquisition and processing module is used to collect the current signal and voltage signal on both sides of the inverter load, filter and amplify the current signal and voltage signal, obtain the phase difference information of the amplified current signal and voltage signal and output it to the control module in the form of PWM wave duty cycle, and obtain the peak current information and output it to the control module in the form of high level; The load matching module is used to achieve tuning matching and impedance matching between the power module and the inverter load.

2. A drive circuit for a frequency converter load according to claim 1, characterized in that: The driving frequency is calculated using a variable step size algorithm and a LADRC algorithm. Specifically, the variable step size algorithm is first used to preliminarily determine the optimal driving frequency based on the peak current information, and then the degree of deviation of the inverter load frequency is determined based on the phase difference information collected in real time, and the LADRC algorithm is used to calculate the change in the driving frequency that needs to be adjusted, thereby determining the current optimal driving frequency.

3. A drive circuit for a frequency converter load according to claim 1, characterized in that: The control module includes an MCU main control chip and a DDS waveform generation module; The MCU main control chip is used to receive the phase difference information and peak current information output by the signal acquisition and processing module, calculate the driving frequency through the LADRC algorithm and the variable step size algorithm, and output it to the DDS waveform generation module, and is also used to control the switch of the relay in the load matching module, thereby controlling the selection of the matching inductor and the matching capacitor in the load matching module; The DDS waveform generation module is used to generate a control signal according to the driving frequency calculated by the MCU main control chip and output it to the driving module; the control signal is a square wave.

4. A drive circuit for a frequency converter load according to claim 1, characterized in that: The power supply module includes a rectifier filter circuit, a Buck step-down circuit, an inverter circuit and a peripheral power supply circuit; The rectifier filter circuit is used to convert the AC voltage into a pulsating DC voltage through a rectifier bridge composed of four diodes, and then provide additional current to compensate for the ripple in the DC voltage through the process of storing and releasing charges in the filter capacitor and input it into the Buck step-down circuit; The Buck step-down circuit is used to control the conduction time of the MOS tube so that the input DC voltage is regulated and filtered through the inductor and capacitor under the control of the MOS tube, thereby reducing the voltage value of the DC voltage output by the rectifier and filter circuit, adjusting the output power, and outputting the stepped-down DC voltage; The inverter circuit is used to convert the DC voltage stepped down by the Buck step-down circuit into an AC voltage and output it to the load matching module; The peripheral power supply circuit is used to provide the control module and the driving module with the driving voltage required for enabling, and the negative voltage required by the operational amplifier in the signal acquisition and processing module through the conversion circuit.

5. A drive circuit for a frequency converter load according to claim 1, characterized in that: The driving module includes two parts, namely, a Buck driving circuit and an inverter driving circuit. The Buck driving circuit and the inverter driving circuit are respectively used to drive the Buck step-down circuit in the power module and the MOS tube in the inverter circuit. The Buck driving circuit and the inverter driving circuit both include an optocoupler isolation part and a MOS tube driving part. The optocoupler isolation part is used to isolate the control module from the power module; the MOS tube driving part converts the control signal output by the control module into a level suitable for driving the MOS tube in the power module.

6. A drive circuit for a frequency converter load according to claim 1, characterized in that: The signal acquisition and processing module includes a sampling circuit, a bandpass filtering circuit, a signal amplification-peak monitoring circuit and a phase detection circuit; The sampling circuit includes a plurality of sampling resistors for collecting current signals and voltage signals at both ends of the inverter load and transmitting them to the bandpass filter circuit; The bandpass filter circuit is used to remove interfering harmonics in the collected current signal and voltage signal and input the filtered current signal and voltage signal into the signal amplification circuit; The signal amplification-peak monitoring circuit comprises a signal amplification circuit and a peak detection circuit; The amplifier circuit amplifies the filtered voltage signal through a proportional amplifier circuit and outputs it to the phase detection circuit, and amplifies the filtered current signal through a differential amplifier circuit and outputs it to the peak detection circuit and the phase detection circuit; The peak detection circuit includes a rectifier diode, an energy storage capacitor and a discharge resistor, which are used to obtain peak current information and transmit it to the control module for analysis; The phase detection circuit includes a voltage follower, a zero-crossing comparator, a D flip-flop and an XOR gate, and is used to obtain the lead-lag relationship between the voltage signal and the current signal and the phase difference information between the two, thereby completing the digital phase detection function.

7. A drive circuit for a frequency converter load according to claim 6, characterized in that: The bandpass filter circuit is an SK active bandpass filter, which includes an SK second-order active low-pass filter and an SK second-order active high-pass filter.

8. A drive circuit for a frequency converter load according to claim 1, characterized in that: The load matching module includes a tuning matching module and an impedance matching module; The tuning and matching module selects the LC matching mode, and realizes the tuning and matching by controlling the opening and closing of different relays and switching the matching inductor and the matching capacitor; The impedance matching module selects a transformer matching mode and performs impedance transformation by changing the turns ratio n1 / n2 of the primary and secondary coils of the transformer to achieve impedance matching.

Images