Analog-to-digital converter and analog-to-digital conversion method

Abstract

The invention discloses an analog-to-digital converter and an analog-to-digital conversion method, the analog-to-digital converter comprises a capacitor array circuit, a comparison circuit and a logic circuit, an Nth-level capacitor array unit in the capacitor array circuit comprises a first capacitor, a first switch unit, a second capacitor and a second switch unit, the movable end of the first switch unit is selectively connected with a power supply voltage, a second reference voltage and a ground end, and the second end of the first switch unit is coupled with the first end of the first capacitor; the movable end of the second switch unit is selectively connected with the power supply voltage, the second reference voltage and the ground end; the second input end of the comparison circuit inputs first reference voltage, and the output end of the comparison circuit is coupled with the logic circuit; and the logic circuit is suitable for converting an output result of the comparison circuit into a corresponding digital signal. According to the scheme, the precision of the analog-to-digital conversion value output by the analog-to-digital converter can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to an analog-to-digital converter and an analog-to-digital conversion method. Background Art

[0002] Analog to Digital Converter (ADC) is an important component in communication systems that can convert analog signals into digital signals.

[0003] The analog-to-digital converter usually includes a sampling and holding circuit, a capacitor array circuit, a comparison circuit, a logic circuit, etc. The capacitor array circuit is usually composed of N-level capacitor array units. The analog-to-digital converter in the prior art can only output an N+1-bit analog-to-digital conversion value, and the output accuracy of the analog-to-digital converter is low. Summary of the invention

[0004] The present invention aims at providing at least an analog-to-digital converter and an analog-to-digital conversion method, which can improve the output accuracy of the analog-to-digital converter.

[0005] In a first aspect, the present invention provides an analog-to-digital converter, which is suitable for converting an input target voltage into an N+2-bit analog-to-digital conversion value and outputting it; the analog-to-digital converter comprises: a capacitor array circuit, a comparison circuit and a logic circuit, the capacitor array circuit comprises N-level capacitor array units; wherein: the i-th level capacitor array unit in the N-level capacitor array unit comprises 2 N-i unit capacitors; the i-th capacitor array unit is coupled to the output end of the capacitor array circuit; i is a positive integer and 1≤i≤N-1; the N-th capacitor array unit in the N-th capacitor array unit includes a first subunit and a second subunit, wherein: the first subunit includes a first capacitor and a first switch unit, the movable end of the first switch unit can be selectively connected to a power supply voltage, a second reference voltage and a ground end, and the second end of the first switch unit is coupled to the first end of the first capacitor; the second end of the first capacitor is coupled to the output end of the capacitor array circuit; the second subunit includes a second capacitor and a second switch unit, the movable end of the second switch unit can be selectively connected to the power supply voltage, the second reference voltage and the ground end, and the second end of the second switch unit is coupled to the first end of the second capacitor; the second end of the second capacitor is coupled to the output end of the capacitor array circuit; the comparison circuit, whose second input end inputs the first reference voltage, and whose output end is coupled to the logic circuit; the logic circuit is suitable for converting the output result of the comparison circuit into a corresponding digital signal.

[0006] Optionally, the i-th level capacitor array unit includes a first subunit and a second subunit, the first subunit includes a first capacitor array and a first switch unit, the second subunit includes a second capacitor array and a second switch unit, wherein: the first switch unit, the moving end of which is selectively connected to the power supply voltage and the ground end, and the fixed end of which is coupled to the first end of the first capacitor array; the second end of the first capacitor array is coupled to the output end of the capacitor array circuit, including 2 N-i-1 The second switch unit has a moving end that can be selectively connected to the power supply voltage and the ground end, and a fixed end that is coupled to the first end of the second capacitor array; the second capacitor array has a second end that is coupled to the output end of the capacitor array circuit, including 2 N-i-1 A unit capacitor.

[0007] Optionally, in the sampling and holding state of the capacitor array circuit, the active end of the first comparison unit of any one of the N-level capacitor array units is connected to the power supply voltage, and the active end of the second comparison unit of any one of the N-level capacitor array units is connected to the ground.

[0008] Optionally, the power supply voltage is twice the first reference voltage.

[0009] Optionally, the second reference voltage is associated with the first reference voltage, that is, the second reference voltage can be determined by the first reference voltage. Specifically, the second reference voltage can be taken from any voltage value within a preset voltage range, the minimum value of the voltage range is the difference between the first reference voltage and a preset threshold value, and the maximum value of the voltage range is the sum of the first reference voltage and the preset threshold value.

[0010] In a second aspect, the present invention provides an analog-to-digital conversion method, which is suitable for controlling the above-mentioned analog-to-digital converter to perform analog-to-digital conversion on an input target voltage; the method comprises: comparing the output voltage of the capacitor array circuit with the first reference voltage for the jth time, and determining the value of the jth bit in the analog-to-digital conversion value based on the jth comparison result; 1≤j≤N; after comparing the output voltage of the capacitor array circuit with the first reference voltage for the Nth time, updating the output voltage of the capacitor array circuit to a first voltage; comparing the first voltage with the first reference voltage, and determining the value of the N+1th bit in the analog-to-digital conversion value based on the comparison result of the first voltage with the first reference voltage, and updating the output voltage of the capacitor array circuit to a second voltage; comparing the second voltage with the first reference voltage, and determining the value of the N+2th bit in the analog-to-digital conversion value based on the comparison result of the second voltage with the first reference voltage.

[0011] Optionally, updating the output voltage of the capacitor array circuit to a first voltage includes: if the output voltage of the capacitor array circuit after the Nth comparison is greater than the first reference voltage, connecting the active end of the first switch unit of the Nth level capacitor array unit to a second reference voltage; if the output voltage of the capacitor array circuit after the Nth comparison is less than the first reference voltage, connecting the active end of the second switch unit of the Nth level capacitor array unit to the second reference voltage.

[0012] Optionally, updating the output voltage of the capacitor array circuit to a second voltage includes: if the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the first switch unit of the Nth-level capacitor array unit to the second reference voltage; if the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the second switch unit of the Nth-level capacitor array unit to the second reference voltage; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the second switch unit of the Nth-level capacitor array unit to the ground; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the first switch unit of the Nth-level capacitor array unit to the second reference voltage.

[0013] Compared with the prior art, the technical solution provided by the present invention has at least the following beneficial effects:

[0014] By setting the second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined to connect the moving end of the first switch unit / the moving end of the second switch unit of the Nth capacitor array unit to the second reference voltage. Then, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the moving end of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Further, the second voltage is compared with the first reference voltage to obtain the N+2th bit in the analog-to-digital conversion value. By using a capacitor array circuit including N-level capacitor array units, the output of the N+2-bit analog-to-digital conversion value is realized, thereby improving the accuracy of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of an analog-to-digital converter in an embodiment of the present invention;

[0016] Figure 2 is a flow chart of an analog-to-digital conversion method in an embodiment of the present invention;

[0017] Figure 3 is a structural schematic diagram of a capacitor array circuit in an embodiment of the present invention;

[0018] Figure 4 Schematic diagram of a P portion layout of a capacitor array circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In the prior art, a capacitor array circuit in an analog-to-digital converter may include N levels of capacitor array units, and may output an N+1-bit analog-to-digital conversion value. The accuracy of the existing analog-to-digital converter is relatively low.

[0020] In an embodiment of the present invention, by setting a second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined to connect the moving end of the first switch unit / the moving end of the second switch unit of the Nth level capacitor array unit to the second reference voltage. Then, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the moving end of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Further, the second voltage is compared with the first reference voltage to obtain the N+2th bit in the analog-to-digital conversion value. By using a capacitor array circuit including N-level capacitor array units, the output of the N+2-bit analog-to-digital conversion value is achieved, thereby improving the accuracy of the analog-to-digital converter.

[0021] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] An embodiment of the present invention provides an analog-to-digital converter, which is suitable for converting an input target voltage into an N+2-bit analog-to-digital conversion value and outputting the value.

[0023] In an embodiment of the present invention, the analog-to-digital converter may include a capacitor array circuit, a comparison circuit, and a logic circuit.

[0024] In a specific implementation, the capacitor array circuit may include N levels of capacitor array units. For the i-th level of capacitor array units in the N levels of capacitor array units, the capacitor array circuit may include 2 N-i The i-th capacitor array unit is coupled to the output end of the capacitor array circuit; i is a positive integer and 1≤i≤N-1.

[0025] That is, the first-level capacitor array unit includes 2 N-1The second-level capacitor array includes 2 N-2 Unit capacitors, and so on, the N-1th level capacitor array unit includes 2 unit capacitors.

[0026] That is to say, the equivalent capacitance value of the i-th capacitor array unit is twice the equivalent capacitance value of the (i+1)-th capacitor array unit.

[0027] like Figure 1 As shown, in the capacitor array circuit, the first-level capacitor array unit is located at the leftmost side of the capacitor array circuit, and the second-level capacitor array unit is adjacent to the first-level capacitor array unit and is located on the right side of the first-level capacitor array unit. Similarly, the Nth-level capacitor array unit is located at the rightmost side of the capacitor array circuit.

[0028] The i-th level capacitor array unit may include a first subunit and a second subunit, the first subunit includes a first switch unit and a first capacitor array, and the second subunit includes a second switch unit and a second capacitor array.

[0029] Specifically, in the i-th level capacitor array unit, the moving end of the first switch unit is selectively connected to the power supply voltage VDD and the ground end GND, and the fixed end of the first switch unit is coupled to the first end of the first capacitor array; the first capacitor array includes 2 N-i-1 unit capacitors, and the second end of the first capacitor array is coupled to the output end of the capacitor array circuit;

[0030] The moving end of the second switch unit can be selectively connected to the power supply voltage VDD and the ground end GND, and the fixed end of the second switch unit is coupled to the first end of the second capacitor array; the second capacitor array includes 2 N-i-1 The total number of capacitors of the first capacitor and the second capacitor array is 2. N-i A unit capacitor.

[0031] For example, N=11, then the first-level capacitor array unit includes 1024 unit capacitors. In the first-level capacitor array unit, the first capacitor array and the second capacitor array each include 512 unit capacitors.

[0032] In the embodiment of the present invention, the Nth level capacitor array unit also includes a first sub-unit and a second sub-unit, wherein:

[0033] The first subunit in the N-th level capacitor array unit includes a first capacitor and a first switch unit; the active end of the first switch unit is selectively connected to a power supply voltage VDD, a second reference voltage Vref2 and a ground terminal GND, the second end of the first switch unit is coupled to the first end of the first capacitor; the second end of the first capacitor is coupled to the output end of the capacitor array circuit;

[0034] The second subunit in the N-th level capacitor array unit includes a second capacitor and a second switch unit; the active end of the second switch unit is selectively connected to the power supply voltage VDD, the second reference voltage Vref2 and the ground terminal GND, the second end of the second switch unit is coupled to the first end of the second capacitor; the second end of the second capacitor is coupled to the output end of the capacitor array circuit. The first capacitor and the second capacitor are both unit capacitors.

[0035] In a specific implementation, the first reference voltage Vref1 may be 1 / 2 of the power supply voltage VDD, that is, Vref1 = 1 / 2×VDD.

[0036] The second reference voltage Vref2 can be determined based on the first reference voltage Vref1. In other words, the second reference voltage Vref2 is associated with the first reference voltage Vref1. The second reference voltage Vref2 can be less than the first reference voltage Vref1, or greater than the first reference voltage Vref1, or equal to Vref1. Both the first reference voltage Vref1 and the second reference voltage Vref2 are less than the power supply voltage VDD.

[0037] In some embodiments, the second reference voltage can be any voltage value within a preset voltage range, the minimum value of the voltage range is the difference between the first reference voltage and the preset threshold, and the maximum value of the voltage range is the sum of the first reference voltage and the preset threshold.

[0038] For example, if the power supply voltage VDD is set to 1.2V, the first reference voltage Vref1 is 0.6V. If the preset threshold is 0.3V, the value of the second reference voltage Vref2 can be between 0.3V and 0.9V.

[0039] In an embodiment of the present invention, a first input terminal of the comparison circuit is coupled to an output terminal of the capacitor array circuit. The analog-to-digital converter may further include a sample-and-hold circuit to sample and hold an input target voltage. A first reference voltage Vref1 may be input to a second input terminal of the comparator. The comparator may compare the first reference voltage Vref1 with the output voltage of the capacitor array circuit, and output a comparison result between the first reference voltage Vref1 and the output voltage of the capacitor array circuit to the logic circuit.

[0040] The logic circuit may convert the comparison result between the first reference voltage Vref1 and the output voltage of the capacitor array circuit into a corresponding digital signal, thereby obtaining an N+2-bit analog-to-digital conversion value.

[0041] In a specific implementation, the specific circuit structures and working processes of the above-mentioned sampling and holding circuit, comparison circuit, and logic circuit can refer to the existing analog-to-digital converter, and will not be described in detail here.

[0042] In an embodiment of the present invention, after the sampling and holding circuit completes the sampling and holding, in the sampling and holding state of the capacitor array circuit, for any one level of capacitor array units in the N levels of capacitor array units: the active end of the first comparison unit therein is connected to the power supply voltage VDD, and the active end of the second comparison unit therein is connected to the ground GND.

[0043] The working process of the analog-to-digital converter provided above is described below. Figure 2 , a flowchart of an analog-to-digital conversion method in an embodiment of the present invention is given. Figure 2 The analog-to-digital conversion method provided in can control the analog-to-digital converter provided above.

[0044] In a specific implementation, the following steps 201 to 204 may be performed by a controller. The controller may be independent of the analog-to-digital converter, or located in the analog-to-digital converter.

[0045] Step 201 : compare the output voltage of the capacitor array circuit with the first reference voltage for the jth time, and determine the value of the jth bit in the analog-to-digital conversion value based on the jth comparison result.

[0046] In a specific implementation, j is a positive integer and 1≤j≤N.

[0047] In an embodiment of the present invention, the controller can control the comparison between the output voltage of the capacitor array circuit and the first reference voltage. After the j-th comparison of the output voltage of the capacitor array circuit is performed, the j-th comparison result can be obtained, and then the value of the j-th bit in the analog-to-digital conversion value can be determined based on the j-th comparison result.

[0048] When the output voltage of the capacitor array circuit is compared with the first reference voltage for the jth time, the output voltage of the capacitor array circuit is Vout j. When the output voltage of the capacitor array circuit is compared with the first reference voltage for the j+1th time, the output voltage of the capacitor array circuit is Vout j+1, which is different from Vout j.

[0049] That is to say, after one comparison, the output voltage of the capacitor array circuit will change. In other words, the output voltage of the capacitor array circuit will change with the number of comparisons with the first reference voltage.

[0050] Specifically, the controller first controls the output voltage of the capacitor array circuit to be compared with the first reference voltage for the first time. During the first comparison, the output voltage Vout1 of the capacitor array circuit is compared with the first reference voltage Vref1.

[0051] If Vout1>Vref1, the value of the first bit in the analog-to-digital conversion value is 1; and, in the first-stage capacitor array unit, the active end of the first switch unit is switched to be connected to the ground, and the active end of the second switch unit remains connected to the ground;

[0052] If Vout1>Vref1, the value of the first bit in the analog-to-digital conversion value is 0; and in the first-level capacitor array unit, the active end of the first switch unit remains connected to the power supply voltage, and the active end of the second switch unit is switched to be connected to the power supply voltage.

[0053] The first bit in the above analog-to-digital conversion value is the most significant bit of the analog-to-digital conversion value.

[0054] Since after the first comparison, the active end of the first switch unit in the first-level capacitor array unit changes / the active end of the second switch unit changes, the output voltage of the capacitor array circuit will change accordingly, from Vout1 to Vout2, and Vout2 is the output voltage of the capacitor array circuit during the second comparison.

[0055] After obtaining the value of the first bit in the analog-to-digital conversion value, the controller controls to compare Vout2 with the first reference voltage Vref1. Similarly:

[0056] If Vout2>Vref1, the value of the second bit in the analog-to-digital conversion value is 1; and, in the second-stage capacitor array unit, the moving end of the first switch unit is switched to be connected to the ground, and the moving end of the second switch unit remains connected to the ground;

[0057] If Vout2>Vref1, the value of the second bit in the analog-to-digital conversion value is 0; and in the second-level capacitor array unit, the active end of the first switch unit remains connected to the power supply voltage, and the active end of the second switch unit is switched to be connected to the power supply voltage.

[0058] After the second comparison, the active end of the first switch unit in the second-level capacitor array unit changes / the active end of the second switch unit changes, so the output voltage of the capacitor array circuit changes accordingly, from Vout2 to Vout2, and Vout2 is the output voltage of the capacitor array circuit during the second comparison.

[0059] Similarly, the controller controls the output voltage of the capacitor array circuit to compare with the first reference voltage Vref1 for the Nth time to obtain the value of the Nth bit in the analog-to-digital conversion value. When performing the Nth comparison, the output voltage of the capacitor array circuit is updated to VoutN.

[0060] Step 202 : after comparing the output voltage of the capacitor array circuit with the first reference voltage for the Nth time, updating the output voltage of the capacitor array circuit to the first voltage.

[0061] In an embodiment of the present invention, after obtaining the comparison result of VoutN and Vref1, the controller can determine the connection mode of the active end of the first comparison unit and the connection mode of the active end of the second comparison unit in the Nth level capacitor array unit based on the comparison result of VoutN and Vref1.

[0062] Specifically, if VoutN>Vref1, the active end of the first switch unit in the Nth level capacitor array unit is switched to be connected to the second reference voltage, and the active end of the second switch unit remains connected to the ground;

[0063] If VoutN<Vref1, the active end of the first switch unit in the Nth stage capacitor array unit is kept connected to the power supply voltage, and the active end of the second switch unit is connected to the second reference voltage.

[0064] After the first adjustment is performed on the moving end of the first switch unit / the moving end of the second switch unit in the Nth stage capacitor array unit, the output voltage of the capacitor array circuit changes and is updated from VoutN to the first voltage VoutN+1.

[0065] Step 203: compare the first voltage with the first reference voltage, determine the value of the N+1th bit in the analog-to-digital conversion value based on the comparison result of the first voltage and the first reference voltage, and update the first voltage to the second voltage.

[0066] In a specific implementation, the controller may control the first voltage VoutN+1 to be compared with the first reference voltage Vref1 .

[0067] If VoutN>Vref1, and VoutN+1>Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 1, and the active end of the first switch unit in the Nth level capacitor array unit is switched to be connected to the ground, and the active end of the second switch unit remains connected to the ground;

[0068] If VoutN>Vref1, and VoutN+1<Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 0, and the active end of the first switch unit in the Nth level capacitor array unit is kept connected to the second reference voltage, and the active end of the second switch unit is switched to be connected to the second reference voltage;

[0069] If VoutN<Vref1, and VoutN+1>Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 1, and the active end of the first switch unit in the Nth level capacitor array unit is kept connected to the second reference voltage, and the active end of the second switch unit is switched to be connected to the ground;

[0070] If VoutN<Vref1, and VoutN+1<Vref1, the value of the N+1th bit in the analog-to-digital conversion value is 0, and the active end of the first switch unit in the Nth level capacitor array unit is switched to be connected to the second reference voltage, and the active end of the second switch unit is switched to be connected to the second reference voltage.

[0071] After the controller makes a second adjustment to the active end of the first switch unit / the active end of the second switch unit in the Nth level capacitor array unit, the output voltage of the capacitor array circuit changes, and the output voltage of the capacitor array circuit is updated from the first voltage VoutN+1 to the second voltage VoutN+2.

[0072] Step 204: compare the second voltage with the first reference voltage, and determine the value of the N+2th bit in the analog-to-digital conversion value based on the comparison result of the second voltage with the first reference voltage.

[0073] In a specific implementation, the controller controls the comparison between the second voltage VoutN+2 and the first reference voltage Vref1 to determine the value of the N+2th bit in the analog-to-digital conversion value.

[0074] Specifically, if VoutN+2>Vref1, the value of the N+2th bit in the analog-to-digital conversion value is 1; if VoutN+2<Vref1, the value of the N+2th bit in the analog-to-digital conversion value is 0.

[0075] As can be seen from the above, through steps 201 to 204, an N+2-bit analog-to-digital conversion value can be obtained.

[0076] In some embodiments, the N+2th bit may also be referred to as a redundant bit.

[0077] The analog-to-digital conversion method and the analog-to-digital converter provided in the above embodiments are described below through specific examples.

[0078] Reference Figure 3 , a schematic diagram of the structure of a capacitor array circuit in an embodiment of the present invention is given. Figure 3 In the embodiment, the capacitor array circuit is in the initialization state.

[0079] Figure 3In the embodiment, the capacitor array circuit includes 11 levels of capacitor array units. The analog-to-digital converter can output a 12-bit analog-to-digital conversion value, and add 1 redundant bit on the basis of the 12-bit analog-to-digital conversion value. In other words, the analog-to-digital converter can output a 13-bit analog-to-digital conversion value. Figure 3 In the circuit, the capacitor array circuit is in the initialization state.

[0080] The i-th level capacitor array unit includes a first switch unit Sip and a second switch unit Sin. The first capacitor array and the second capacitor array in the i-th level capacitor array unit both include 2 N-i-1 A unit capacitor.

[0081] Specifically, Figure 3 As shown, the first-level capacitor array unit includes a first switch unit S1p and a second switch unit S1n, and the first capacitor array includes 512 unit capacitors C lsb The second capacitor array also includes 512 unit capacitors C lsb .

[0082] The second-level capacitor array unit includes a first switch unit S2p, a first capacitor array, a second switch unit S2n, and a second capacitor array. The first capacitor array includes 256 unit capacitors C lsb The second capacitor array also includes 256 unit capacitors C lsb .

[0083] Similarly, the 10th level capacitor array unit includes a first switch unit S10p and a second switch unit S10n, and the first capacitor array includes a unit capacitor C lsb The second capacitor array also includes 1 unit capacitor C lsb .

[0084] The 11th capacitor array unit includes a first switch unit S11p, a second switch unit S12p, and capacitors C respectively connected to the second end of the first switch unit S11p. lsb , the capacitor C connected to the second switch unit S12p lsb .

[0085] The moving end of S11p can be selectively connected to the power supply voltage, the second reference voltage and the ground, and the moving end of S11n can be selectively connected to the power supply voltage, the second reference voltage and the ground. The second reference voltage is 1 / 2 times the first reference voltage.

[0086] The controller can compare the output voltage of the capacitor array circuit with the first reference voltage for the first time to obtain the value of the first bit in the analog-to-digital conversion value (i.e., the highest bit in the analog-to-digital conversion value). Similarly, the controller can compare the output voltage of the capacitor array circuit with the first reference voltage for the second time to obtain the value of the second bit in the analog-to-digital conversion value. By analogy, the value of the Nth bit in the analog-to-digital conversion value can be obtained.

[0087] In the sample-and-hold state of the capacitor array circuit, the moving end of the first switch unit of the j-th capacitor array unit is connected to the power supply voltage, and the moving end of the second switch unit is connected to the ground. In this state, the controller compares the output voltage of the capacitor array circuit with the first reference voltage for the first time.

[0088] For the first level capacitor array unit:

[0089] The first capacitor array of the first subunit includes 512 unit capacitors connected in parallel, and the second capacitor array of the second subunit includes 512 unit capacitors connected in parallel.

[0090] The controller controls the output voltage value of the capacitor array circuit to be compared with the first reference voltage Vref1 for the first time. At this time, the output voltage of the capacitor array circuit is Vout1. If Vout1 < Vref1, the active end of the first switch unit of the first-level capacitor array unit remains connected to the power supply voltage, and the active end of the second switch unit is switched from the ground end to the power supply voltage; at this time, the first bit in the analog-to-digital conversion value is 0;

[0091] If Vout1>Vref1, the active end of the first switch unit of the first-level capacitor array unit is switched from the power supply voltage to the ground, and the active end of the second switch unit remains connected to the ground; at this time, the value of the first bit in the analog-to-digital conversion value is 1.

[0092] For the second level capacitor array unit:

[0093] The first capacitor array of the first subunit includes 256 unit capacitors connected in parallel, and the second capacitor array of the second subunit includes 256 unit capacitors connected in parallel.

[0094] The controller controls the output voltage value of the capacitor array circuit to be compared with Vref1 for the second time, and the output voltage value of the capacitor array circuit during the second comparison is Vout2. If Vout2 < Vref1, the active end of the first switch unit of the second-level capacitor array unit remains connected to the power supply voltage, and the active end of the second switch unit is switched from the ground end to the power supply voltage; at this time, the value of the second bit in the analog-to-digital conversion value is 0;

[0095] If Vout2>Vref1, the active end of the first switch unit of the second-level capacitor array unit is switched from the power supply voltage to the ground, and the active end of the second switch unit remains connected to the ground; at this time, the value of the second bit in the analog-to-digital conversion value is 1.

[0096] By analogy, for the 10th level capacitor array unit:

[0097] The first capacitor array of the first sub-unit includes one unit capacitor, and the second capacitor array of the second sub-unit includes one unit capacitor.

[0098] The controller controls the comparison between the output voltage value Vout10 and Vref1 of the capacitor array circuit. If Vout10 < Vref1, the active end of the first switch unit of the 10th level capacitor array remains connected to the power supply voltage, and the active end of the second switch unit is switched from the ground end to the power supply voltage; at this time, the value of the 10th bit in the analog-to-digital conversion value is 0;

[0099] If Vout10>Vref1, the active end of the first switch unit of the 10th level capacitor array is switched from the power supply voltage to the ground, and the active end of the second switch unit remains connected to the ground; at this time, the value of the 10th bit in the analog-to-digital conversion value is 1.

[0100] The structure of the 11th level capacitor array unit is the same as the circuit structure of the 10th level capacitor array unit. The 11th level capacitor array unit includes a first subunit and a second subunit, the first subunit includes a first capacitor and a first switch unit, and the second subunit includes a second capacitor and a second switch unit. The first capacitor and the second capacitor are both unit capacitors.

[0101] The controller controls the output voltage value of the capacitor array circuit to be compared with Vref1 for the 11th time. The output voltage value of the capacitor array circuit during the 11th comparison is Vout11. If Vout11 < Vref1, the active end of the first switch unit in the 11th level capacitor array unit is connected to the power supply voltage, and the active end of the second switch unit is connected to the second reference voltage. The value of the 11th bit in the analog-to-digital conversion value is 0;

[0102] If Vout11>Vref1, the active end of the first switch unit in the 11th level capacitor array unit is connected to the second reference voltage, and the active end of the second switch unit is connected to the second reference voltage; at this time, the value of the 11th bit in the analog-to-digital conversion value is 1.

[0103] After comparing Vout11 and Vref1, the output voltage of the capacitor array circuit changes and is set to Vout12.

[0104] Vout12 is compared with Vref1.

[0105] If Vout11<Vref1 and Vout12<Vref1, the moving end of the first switch unit in the 11th capacitor array unit is connected to the second reference voltage, and the moving end of the second switch unit is connected to the second reference voltage. The value of the 12th bit in the analog-to-digital conversion value is 0.

[0106] If Vout11<Vref1, and Vout12>Vref1, the moving end of the first switch unit in the 11th level capacitor array unit is connected to the power supply voltage, and the moving end of the second switch unit is connected to the ground. The value of the 12th bit in the analog-to-digital conversion value is 1.

[0107] If Vout11>Vref1, and Vout12<Vref1, the moving end of the first switch unit in the 11th level capacitor array unit is connected to the second reference voltage, and the moving end of the second switch unit is connected to the second reference voltage. The value of the 12th bit in the analog-to-digital conversion value is 0.

[0108] If Vout11>Vref1, and Vout12>Vref1, the moving end of the first switch unit in the 11th level capacitor array unit is connected to the ground, and the moving end of the second switch unit is connected to the ground. The value of the 12th bit in the analog-to-digital conversion value is 1.

[0109] After comparing Vout12 with Vref1, the output voltage of the capacitor array circuit is updated to Vout13.

[0110] Vout13 is compared with Vref1.

[0111] If Vout13<Vref1, the value of the 13th bit in the analog-to-digital conversion value is 0; if Vout13>Vref1, the value of the 13th bit in the analog-to-digital conversion value is 1.

[0112] It can be seen from the above content that in the process of obtaining the 13-bit analog-to-digital conversion value, the value of the highest bit (that is, the first bit of the analog-to-digital conversion value) is first obtained, and then the value of the second highest bit (that is, the second bit of the analog-to-digital conversion value) is obtained, and so on, and finally the value of the 13th bit (that is, the lowest bit of the analog-to-digital conversion value) is obtained. In addition, the capacitor array circuit only includes 11 levels of capacitor array units, which can achieve 1 bit of redundancy and 12 bits of analog-to-digital conversion value (essentially a total of 13 bits of analog-to-digital conversion value).

[0113] Reference Figure 4 , a schematic diagram of a P part layout of a capacitor array circuit in an embodiment of the present invention is given. The above P part layout includes the first subunit in the 1st to 11th level capacitor array units, that is, the first subunit of the 11th level capacitor array unit.

[0114] The schematic diagram of the N-part layout of the capacitor array circuit can refer to the schematic diagram of the P-part layout, and the two are mirror images. The above-mentioned N-part layout includes the second subunits in the 1st to 11th level capacitor array units, that is, the second subunits of the 11th level capacitor array units.

[0115] Depend on Figure 4 It can be seen that in the P part of the layout, the capacitors can be completely covered, realizing full utilization of the layout. Correspondingly, in the N part of the layout, the layout can also be fully utilized.

[0116] In summary, by setting the second reference voltage, based on the magnitude relationship between the output voltage of the capacitor array circuit after the Nth comparison and the first reference voltage, it is determined to connect the moving end of the first switch unit / the moving end of the second switch unit of the Nth capacitor array unit to the second reference voltage. Then, the output voltage of the capacitor array circuit is updated to the first voltage. Based on the magnitude relationship between the first voltage and the first reference voltage, the moving end of the first switch unit / the second switch unit connected to the second reference voltage is adjusted, the output voltage of the capacitor array circuit is adjusted from the first voltage to the second voltage, and the value of the N+1th bit in the analog-to-digital conversion value is obtained. Further, the second voltage is compared with the first reference voltage to obtain the N+2th bit in the analog-to-digital conversion value. By using a capacitor array circuit including N-level capacitor array units, the output of the N+2-bit analog-to-digital conversion value is realized, thereby improving the accuracy of the analog-to-digital converter.

[0117] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An analog-to-digital converter, characterized in that: Suitable for converting the input target voltage into an N+2-bit analog-to-digital conversion value and outputting it; the analog-to-digital converter includes: a capacitor array circuit, a comparison circuit and a logic circuit, and the capacitor array circuit includes N levels of capacitor array units; wherein: The i-th level capacitor array unit in the N-level capacitor array unit comprises 2 N-i unit capacitors; the i-th capacitor array unit is coupled to the output end of the capacitor array circuit; i is a positive integer and 1≤i≤N-1; The Nth level capacitor array unit in the N level capacitor array units includes a first subunit and a second subunit, wherein: The first subunit includes a first capacitor and a first switch unit, a moving end of the first switch unit can be selectively connected to a power supply voltage, a second reference voltage and a ground end, a second end of the first switch unit is coupled to a first end of the first capacitor; and a second end of the first capacitor is coupled to an output end of the capacitor array circuit; The second subunit includes a second capacitor and a second switch unit, the active end of the second switch unit is selectively connected to the power supply voltage, the second reference voltage and the ground end, the second end of the second switch unit is coupled to the first end of the second capacitor; the second end of the second capacitor is coupled to the output end of the capacitor array circuit; The comparison circuit has a second input terminal inputting a first reference voltage and an output terminal coupled to the logic circuit; The logic circuit is suitable for converting the output result of the comparison circuit into a corresponding digital signal.

2. The analog-to-digital converter according to claim 1, wherein: The i-th level capacitor array unit comprises a first subunit and a second subunit, the first subunit comprises a first capacitor array and a first switch unit, the second subunit comprises a second capacitor array and a second switch unit, wherein: the first switch unit has a moving end that can be selectively connected to the power supply voltage and the ground end, and a fixed end that is coupled to the first end of the first capacitor array; The first capacitor array, whose second end is coupled to the output end of the capacitor array circuit, comprises 2 N-i-1 Unit capacitance; The second switch unit has a moving end selectively connected to the power supply voltage and the ground, and a fixed end coupled to the first end of the second capacitor array; The second capacitor array, whose second end is coupled to the output end of the capacitor array circuit, comprises 2 N-i-1 A unit capacitor.

3. The analog-to-digital converter according to claim 2, wherein: In the sampling and holding state of the capacitor array circuit, the active end of the first comparison unit of any one of the N-level capacitor array units is connected to the power supply voltage, and the active end of the second comparison unit of any one of the N-level capacitor array units is connected to the ground.

4. The analog-to-digital converter according to claim 1, wherein: The power supply voltage is twice the first reference voltage.

5. The analog-to-digital converter according to claim 1, wherein: The second reference voltage is related to the first reference voltage.

6. An analog-to-digital conversion method, characterized in that: The method is suitable for performing analog-to-digital conversion on an input target voltage based on the analog-to-digital converter provided by any one of claims 1 to 5; the method comprises: Comparing the output voltage of the capacitor array circuit with the first reference voltage for the jth time, and determining the value of the jth bit in the analog-to-digital conversion value based on the jth comparison result; j is a positive integer and 1≤j≤N; after comparing the output voltage of the capacitor array circuit with the first reference voltage for the Nth time, updating the output voltage of the capacitor array circuit to the first voltage; Comparing the first voltage with the first reference voltage, determining a value of the N+1th bit in the analog-to-digital conversion value based on a comparison result of the first voltage with the first reference voltage, and updating the output voltage of the capacitor array circuit to a second voltage; The second voltage is compared with the first reference voltage, and based on the comparison result of the second voltage and the first reference voltage, a value of the N+2th bit in the analog-to-digital conversion value is determined.

7. The analog-to-digital conversion method according to claim 6, wherein: The updating the output voltage of the capacitor array circuit to a first voltage includes: If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, the active end of the first switch unit of the Nth level capacitor array unit is connected to the second reference voltage; if the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, the active end of the second switch unit of the Nth level capacitor array unit is connected to the second reference voltage.

8. The analog-to-digital conversion method according to claim 7, wherein: The step of updating the output voltage of the capacitor array circuit to a second voltage comprises: If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the first switch unit of the Nth stage capacitor array unit to the second reference voltage; If the output voltage of the capacitor array circuit is greater than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, connecting the fixed end of the second switch unit of the Nth level capacitor array unit to the second reference voltage; If the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is greater than the first reference voltage, connecting the fixed end of the second switch unit of the Nth level capacitor array unit to the ground end; If the output voltage of the capacitor array circuit is less than the first reference voltage during the Nth comparison, and the first voltage is less than the first reference voltage, the fixed end of the first switch unit of the Nth stage capacitor array unit is connected to the second reference voltage.

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