FPGA implementation method of DVB high-speed demodulator

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) implementation method of a DVB (Digital Video Broadcasting) high-speed demodulator. A digital signal enters a parallel DDC (Direct Digital Control) module and is re-adapted to multiple symbol rates; the parallel AGC module adjusts the power of the digital signal to a fixed power value; the method comprises the following steps: passing through Oamp; m algorithm: completing symbol synchronization; related peaks are extracted, and frame synchronization is completed; correcting the frequency to enable the frequency to reach participation frequency deviation; performing frequency compensation on the digital signal after loop filtering; after error information is calculated and filtered, the digital signal is compensated; and restoring the original information of the digital signal. According to the invention, by adopting the parallel processing module, the real-time performance and the parallelism degree of digital signal processing can be greatly improved, and the performance of the whole demodulator is enhanced. Each module is designed to be adaptive to the change of a digital signal, for example, the AGC module can dynamically adjust the power of the digital signal to ensure that the output digital signal is always kept at a fixed power level so as to adapt to different receiving conditions.

Description

Technical Field

[0001] The invention belongs to the technical field of digital signal processing, and in particular relates to an FPGA implementation method of a DVB high-speed demodulator. Background Art

[0002] With the continuous development of society, people's demand for satellite digital signal transmission is increasing, especially in the transmission mode and quantity of various information such as files, voice and video. The bandwidth demand of satellite digital signals has also increased accordingly. At present, the symbol rate of most satellite digital signals is generally in the range of tens of megasymbols per second (Msps). However, with the advancement of technology and the expansion of application scenarios, the demand for high-speed digital signal transmission of hundreds of megasymbols per second has become more urgent. Therefore, the present invention aims to design an FPGA implementation scheme that can realize high-speed baseband digital signal processing in the range of 1 megasymbol per second (Msps) to 750 megasymbols per second (Msps). Through this design, the transmission efficiency of satellite digital signals can be effectively improved to meet the challenges of higher bandwidth requirements in the future, and more reliable and efficient technical support can be provided for related application fields.

[0003] In the prior art, the technical solution recorded in the patent with publication number CN114297121A is: a method for implementing bidirectional high-speed data transmission between FPGA chips, which splits the high-speed data processing flow originally located in a single-chip FPGA into 8 paths and distributes them to two or more FPGA chips to achieve collaborative processing of multiple FPGA chips, thereby increasing the capacity limit of data processing.

[0004] In the prior art, as the speed of digital signal processing algorithms becomes faster and faster, the amount of data becomes larger and larger, and the complexity becomes higher and higher, if a large bandwidth and high-resolution spectrum is to be achieved, high-performance chips are required, which increases the price and cost. Summary of the invention

[0005] The object of the present invention is to provide an FPGA implementation method of a DVB high-speed demodulator to solve the problem in the prior art mentioned in the background technology that if a high-performance chip is required to realize a large-bandwidth and high-resolution spectrum, the price and cost increase.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A FPGA implementation method of a DVB high-speed demodulator comprises the following steps:

[0008] Step S1, the digital signal enters the parallel DDC module, and the sampling rate of the digital signal is re-adapted to a multiple symbol rate after passing through the parallel DDC module;

[0009] Step S2, the digital signal passes through a parallel AGC module, and the AGC module adjusts the power of the digital signal to a fixed power value;

[0010] Step S3, parallel symbol synchronization; the clock error is extracted by using the O&M algorithm, the clock error is filtered by the loop filter, and then passed through the NCO control module to adjust the symbol phase, that is, to complete the symbol synchronization;

[0011] Step S4, parallel frame synchronization, extracting correlation peaks according to the digital signal that completes symbol synchronization, thereby completing frame synchronization;

[0012] Step S5, parallel carrier synchronization; extracting the frequency deviation through the L&R algorithm, and correcting the frequency so that the frequency reaches the participating frequency deviation;

[0013] Step S6, parallel phase synchronization; extracting the phase error, sending the error to a loop filter, filtering out the false burr digital signal by the loop filter, and performing frequency compensation on the digital signal after the loop filter, thereby compensating the phase of the digital signal itself;

[0014] Step S7, parallel equalization; for the defect of high bandwidth distortion, the error information is calculated and filtered, and the digital signal is compensated;

[0015] Step S8: After the equalization is completed, the digital signal enters the decoding operation, thereby restoring the original information of the digital signal.

[0016] According to the above technical solution, in step S1, the sampling rate of the digital signal is re-adapted to a multiple of the symbol rate as follows:

[0017] Assume that the digital signal x(m) is T s The analog digital signal x is the sampling rate a (mT s ), pass x(m) through an interpolation filter h(t) to obtain an analog digital signal y(t);

[0018]

[0019] In the formula, y a (t) represents the digital signal after digital interpolation filtering, h(t-mT s ) represents the digital accumulation form of the interpolation filter; m represents the mth sampling; t represents time; mT s represents the mth time period;

[0020] Use the new sampling rate T for y(t) i Sampling is performed to obtain the digital signal of y(t) at the new sampling rate:

[0021]

[0022] Where y(k) represents the digital signal at the new sampling rate; h(kT i -mT s ) represents the cumulative form of the interpolation filter after adjusting the coefficients; kT i Indicates time; mT s represents the mth time period;

[0023] Let kT i =(m k +μ k )T s , define the following variables:

[0024]

[0025] The calculation of the resampling filter is then expressed as follows:

[0026]

[0027] Where, T s Represents the sampling rate, m k is the interpolation base point, which indicates that the interpolator performs interpolation at this moment; μ k Indicates time kT i With m k T s The difference between the optimal interpolation moment and the base point, x(m k -i) represents the sample at the previous moment, h(μ k +i) indicates that the filter is in (μ k +i) corresponding to the phase; N1, N2 represent the sampling samples from N1 to N2; μk represents the fractional delay; i represents the filter index; m k Indicates the base point index.

[0028] According to the above technical solution, in step S2, the AGC module adjusts the power of the digital signal to a fixed power value as follows:

[0029] Assume that the digital signal input to the AGC module is z(k); the AGC module first calculates the instantaneous power value corresponding to the input digital signal, and then subtracts it from the target power p to obtain an error digital signal e; then the error digital signal is sent to a first-order loop filter to complete the loop filtering, and finally the absolute value of the filtered control digital signal is calculated to obtain the digital signal gain G, and finally G is multiplied by the input digital signal to complete the power adjustment, where the corresponding gain expression is:

[0030] G k+1 =G k -γ(|G k Zk | 2 -p)

[0031] In the formula, G k+1 Indicates the current gain value, G k represents the last increment, γ represents the filter coefficient, |G k z k | 2 -p indicates the error between the power value and the target value after the last adjustment; Z k represents the digital sampling signal, and p represents the target power.

[0032] According to the above technical solution, in step S3, the clock error information is extracted, filtered by the loop filter, and sent to the NCO control module, so that the symbol synchronization is completed, which specifically includes the following steps:

[0033] First, the O&M error extraction module extracts the error estimation digital signal from the output sampling point clock of the APRX; then the loop filter filters the error estimation digital signal to obtain a new estimation value; finally, the filtered estimation value is sent to the NCO module, and the NCO accumulates the estimation value to obtain the corresponding clock phase error; then the NCO separates the clock phase error into two control digital signals;

[0034] The extracted clock error is:

[0035]

[0036] Where: x k represents the oversampled data entering the module; N represents the oversampling multiple; L represents the number of symbol samples corresponding to the estimation; m represents the current mth phase error estimation, e -j2πk / N represents the Fourier calculation coefficient; (m+1) represents the (m+1)th phase error estimation, (m+1)LN-1 represents the (m+1)LN-1th symbol, and k represents the kth sample.

[0037] According to the above technical solution, in step S4, parallel frame synchronization is specifically as follows: after symbol synchronization is completed, the best sampling data with 1 times oversampling is obtained, and the data is divided into two paths and sent to different sub-modules after entering the frame synchronization; one path of data is sent to the differential correlation peak detection module; the other path of data is sent to the constellation demapping module and the Reed-Muller decoding module to obtain MODCOD; then the peak value and MODCOD are sent to a state machine module for judgment, and the state machine module is used to verify whether the current symbol is a frame header symbol and make a judgment; if it is judged to be a frame header, the corresponding data frame can be sent to the descrambling module to complete the data descrambling, and if it is not a frame header, the frame header is recaptured.

[0038] According to the above technical solution, in step S5, parallel carrier synchronization is specifically as follows:

[0039] The frequency deviation is estimated through the L&R algorithm, and the loop bandwidth of the loop filter is adjusted to reduce the frequency deviation of the digital signal. Finally, it can be used to correct the frequency deviation through an accumulator and DDS to recover the carrier.

[0040] According to the above technical solution, the L&R algorithm is as follows:

[0041]

[0042] In the formula, represents frequency deviation; r(i) is the received pilot symbol, M is a calculation coefficient, which represents a trade-off factor between algorithm complexity and calculation accuracy, (r(ik)) represents r(i) delayed by k samples, conj() represents conjugate calculation; k represents the kth sample, 1 / (π(M+1)) represents frequency normalization, (M+1) is a trade-off factor; N represents the number of sampling points.

[0043] According to the above technical solution, in step S6, parallel phase synchronization is specifically:

[0044] First, N output sequences are passed through a group of parallel phase detectors, and polarity judgment digital signals are obtained through polarity judgment. The phase error between the output digital signal and the reference digital signal is extracted to obtain a group of N×1 phase error vectors E; then the extracted error vector E is passed through a parallel digital loop filter to suppress input noise and adjust the loop correction speed, and the loop filter generates a corresponding control digital signal W; according to the output of the parallel loop filter, the parallel numerically controlled oscillator NCO obtains different frequency control words to change the carrier compensation frequency Φ output by the NCO.

[0045] According to the above technical solution, in step S7, parallel equalization is implemented by a parallel frequency domain CMA algorithm, which includes a cost function gradient calculation module and a compensation coefficient update module, wherein the cost function gradient calculation module is used to calculate the corresponding gradient drop vector of multiple sampling points. The compensation coefficient update module controls the vector And the appropriate step size μ, the compensation value of each frequency domain can be updated.

[0046] According to the above technical solution, the frequency domain CMA algorithm is specifically shown as follows:

[0047]

[0048] In the formula, represents the corresponding gradient descent vector of the sampling point; N represents the number of sampling points; n represents an integer from 0 to N, and R2 represents the target value, that is, z n+N represents the nth vector currently being calculated; Θ represents the Hadamard product, Y is the output value of the equalizer; F n+N is a 2N×1 Fourier vector.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] In the present invention, by adopting parallel processing modules (such as parallel DDC, AGC, symbol synchronization, frame synchronization, carrier synchronization, phase synchronization and equalization), the real-time and parallelism of digital signal processing can be greatly improved, and the performance of the entire demodulator can be enhanced. Each module is designed to be able to adapt to changes in digital signals. For example, the AGC module can dynamically adjust the power of digital signals to ensure that the output digital signal always remains at a fixed power level, thereby adapting to different receiving conditions. By adopting complex synchronization algorithms (such as O&M algorithms, L&R algorithms) and filters, the method in the present invention can effectively extract and correct clock, frequency and phase errors, reduce the impact of errors on demodulated digital signals, and thus improve the demodulation accuracy of digital signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 The digital signal processing flow chart of the present invention;

[0052] Figure 2 This is a diagram of the parallel DDC implementation architecture of the present invention;

[0053] Figure 3 This is a diagram of the architecture of the parallel decimal interpolation filter of the present invention;

[0054] Figure 4 AGC structure diagram of the present invention;

[0055] Figure 5 This is a structural diagram of symbol synchronization implementation of the present invention;

[0056] Figure 6 It is a flow chart of the O&M error extraction algorithm of the present invention;

[0057] Figure 7 This is a diagram of the frame synchronization implementation architecture of the present invention;

[0058] Figure 8 This is a block diagram of the peak detection implementation of the present invention;

[0059] Fig. 9 This is a block diagram of the baseband processing carrier frequency tracking implementation of the present invention;

[0060] Fig.10This is a block diagram of the APRX parallel carrier phase recovery structure of the present invention;

[0061] Fig.11 This is a block diagram of the channel distortion error compensation algorithm of the present invention;

[0062] Fig.12 This is a block diagram of the parallel frequency domain CMA equalization structure of the present invention;

[0063] Fig.13 It is a structural block diagram of the LDPC decoder of the present invention;

[0064] Fig.14 This is a signal processing waveform diagram of the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Embodiment 1

[0067] like Figure 1 As shown, a FPGA implementation method of a DVB high-speed demodulator includes the following steps:

[0068] Step S1, the digital signal enters the parallel DDC module, and the sampling rate of the digital signal is re-adapted to a multiple symbol rate after passing through the parallel DDC module;

[0069] Step S2, the digital signal passes through a parallel AGC module, and the AGC module adjusts the power of the digital signal to a fixed power value;

[0070] Step S3, parallel symbol synchronization is performed by using the O&M algorithm (the algorithm uses the principle that high-frequency components will appear in the frequency domain adjacent to the symbol corresponding to the square value of the sampling point at the receiving end (shaping matching processing is required), and the clock error is calculated by extracting the position where the high-frequency components appear. The algorithm obtains a clock error value by calculating N sampling points. This method satisfies the condition that the clock error is adjusted once when processing a data frame (N sampling points) in parallel at the same time), extracts the clock error information, and after filtering by the loop filter, sends it to the NCO control module, thereby completing symbol synchronization;

[0071] Step S4, parallel frame synchronization, extracting correlation peaks according to the digital signal that completes symbol synchronization, thereby completing frame synchronization;

[0072] In the present invention, the frame header capture adopts the method of differential autocorrelation peak value, which obtains a correlation peak value after differential operation between symbols and then performs correlation operation with a known symbol sequence, and the correlation peak value is the frame start position. The frame tracking adopts the window tracking strategy, that is, the frame length information obtained after decoding the physical frame header is used to infer the position of the next frame header, and the frame header symbol is extracted at the same time, and it is verified whether these symbols are frame header symbols. If yes, the next frame header is searched and verified; if not, the frame header is captured again, and so on.

[0073] Step S5, parallel carrier synchronization; extracting the frequency deviation through the L&R algorithm, and correcting the frequency so that the frequency reaches a smaller participating frequency deviation;

[0074] Step S6, parallel phase synchronization; extracting the phase error, sending the error to a loop filter, filtering out the false burr digital signal by the loop filter, and performing frequency compensation on the digital signal after the loop filter, thereby compensating the phase of the digital signal itself;

[0075] Step S7, parallel equalization; for the defect of high bandwidth distortion, the error information is calculated and filtered, and the digital signal is compensated;

[0076] Step S8: After the equalization is completed, the digital signal enters the decoding operation, thereby restoring the original information of the digital signal.

[0077] In the present invention, by adopting parallel processing modules (such as parallel DDC, AGC, symbol synchronization, frame synchronization, carrier synchronization, phase synchronization and equalization), the real-time and parallelism of digital signal processing can be greatly improved, and the performance of the entire demodulator can be enhanced. Each module is designed to be able to adapt to changes in digital signals. For example, the AGC module can dynamically adjust the power of digital signals to ensure that the output digital signal always remains at a fixed power level, thereby adapting to different receiving conditions. By adopting complex synchronization algorithms (such as O&M algorithms, L&R algorithms) and filters, the method in the present invention can effectively extract and correct clock, frequency and phase errors, reduce the impact of errors on demodulated digital signals, and thus improve the demodulation accuracy of digital signals.

[0078] Embodiment 2

[0079] This embodiment provides a specific implementation method:

[0080] Step 1: The digital signal first passes through the parallel DDC module to complete the sampling rate adaptation function. The digital signal entering the DDC is a multi-phase parallel input digital signal, that is, N phases (usually N = 16 / 8 / 4). After passing through this module, the sampling rate of the digital signal is re-adapted to 4 times the symbol rate.

[0081] Step 2, the digital signal then passes through the parallel AGC module, which adjusts the power of the digital signal to a fixed power value of -12dB. The module detects the power of the input digital signal and, after passing through a loop filter, feeds the digital signal back to the gain controller to form a closed loop, thereby adjusting the input power and ultimately achieving automatic power adjustment to the target value.

[0082] Step 3: Parallel symbol synchronization uses the O&M algorithm to extract clock error information, and after loop filtering, it is sent to the NCO control module to control the interpolation filter and generate extraction symbol enable, thereby completing symbol synchronization.

[0083] Step 4: Parallel frame synchronization: Based on the characteristics of digital signals, a correlation scheme is used to extract the correlation peak, thereby finding the frame start position, paving the way for further processing of subsequent digital signals.

[0084] Step 5, parallel carrier synchronization, extract the frequency deviation through the L&R algorithm, and correct the frequency so that the frequency reaches a smaller participating frequency deviation, making further preparations for subsequent phase synchronization.

[0085] Step 6, parallel phase synchronization, adopts a parallel closed-loop method, extracts the phase error, and then sends the error to a loop filter. The loop filter further filters out the false burr digital signal, thereby performing frequency compensation on the filtered digital signal, thereby compensating the phase of the digital signal itself and achieving the function of complete phase recovery.

[0086] Step 7: Parallel equalization calculates error information based on the characteristics of the digital signal to address the defect of high-bandwidth distortion, and then compensates the digital signal after filtering to further restore the digital signal.

[0087] Step 8: After completing the equalization, the digital signal enters the decoding operation module, which mainly implements LDPC decoding to restore the original information of the digital signal.

[0088] Functions of each module:

[0089] 1. Parallel DDC

[0090] The parallel DDC circuit block diagram is as follows Figure 2 As shown, the Rx resampling module consists of three cascaded half-band filters, one CIC filter and a fractional interpolation filter.

[0091] Cascaded half-band filters (#1#2#3): Each half-band filter can achieve 2x decimation and can also be bypassed individually, so the entire half-band filter can achieve 4 decimation ratios of 1, 2, 4 and 8 times.

[0092] CIC filter: CIC filter is used to achieve a wide range of decimation multiples, from 1 to 1023 times;

[0093] Decimal interpolation filter: mainly realizes the conversion of fractional rate, and the decimation multiple is between 1.0 and 2.0.

[0094] Bypass control mainly controls the extraction configuration priority and implementation architecture of each functional sub-block. The main strategies are as follows:

[0095] The enabling priority of the half-band filter is: the first stage is enabled first, followed by the second stage, and finally the third stage. Each stage adopts an N-way parallel architecture.

[0096] The CIC decimation filter decimation function is used only when the previous half-band filters are used. Therefore, the CIC filter works at a lower processing rate and a single-channel serial architecture can be used.

[0097] Because the front stage of the fractional interpolation filter may be bypassed, it needs to work under the ADC sampling clock and still adopts an N-way parallel architecture.

[0098] The purpose of the FIR 2x interpolation filter is to make the digital signal bandwidth of the fractional interpolation filter less than 0.4 of the input sampling rate.

[0099] The parameters of each functional sub-block are calculated as follows:

[0100] rx_hb_ par [1:0]

[0101]

[0102] rx_cic_ par [9:0]

[0103]

[0104] in, Indicates rounding down.

[0105] rx_frac_par[23:0]

[0106]

[0107] The resampling filter can realize the conversion of any multiple (especially fractional) rate, that is, the resampling filter can realize the rate conversion of digital signals. Suppose the digital signal x(m) is T s The analog digital signal x is the sampling rate a (mT s). Pass x(m) through an interpolation filter h(t) to obtain an analog digital signal y(t):

[0108]

[0109] In the formula, y a (t) represents the digital signal after digital interpolation filtering, h(t-mT s ) represents the digital accumulation form of the interpolation filter; m represents the mth sampling; t represents time; mT s Represents the mth time period.

[0110] Use the new sampling rate T for y(t) i Sampling is performed to obtain the digital signal of y(t) at the new sampling rate:

[0111]

[0112] Where y(k) represents the digital signal at the new sampling rate; h(kT i -mT s ) represents the cumulative form of the interpolation filter after adjusting the coefficients; kT i Indicates time; mT s represents the mth time period;

[0113] Let kT i =(m k +μ k )T s , define the following variables:

[0114]

[0115] The calculation of the resampling filter is then expressed as follows:

[0116]

[0117] Where, T s Represents the sampling rate, m k is the interpolation base point, which indicates that the interpolator performs interpolation at this moment; μ k Indicates time kT i With m k T s The difference between the optimal interpolation moment and the base point, x(m k -i) represents the sample at the previous moment, h(μ k +i) indicates that the filter is in (μ k +i) corresponding to the phase; N1, N2 represent the sampling samples from N1 to N2; μ k represents fractional delay; i represents filter index; m kRepresents the base point index, the result is as follows Fig.14 shown.

[0118] The relationship between the interpolator output point and the receiver sampling point is as follows: Figure 3 As shown. Among them, m k is the interpolation base point, which indicates that the interpolator performs interpolation at this moment; μ k Indicates time kT i With m k T s The difference between , which represents the fractional interval between the optimal interpolation moment and the base point. k and μ k The value of is controlled by the controller.

[0119] The core interpolation filter implementation architecture is as follows. For simplicity, an example is given below where the N value is 4 and 4-way parallel operation is used. Figure 3 The figure shows a parallel 4-channel digital resampling structure. The 4 groups of FIR filters obtain 4 parallel outputs respectively. The parallel NCO controller outputs 4 decimal intervals and 4 overflow enable digital signals. The outputs of the 4 groups of FIR filters are respectively calculated with the decimal intervals in the corresponding order and sent to the FIFO cache. The overflow enable digital signal is used to select the valid data sequence for parallel output, and the correct output value of the parallel digital resampling can be obtained. Figure 3 Each group of FIR filters can use the register delay addition method to achieve real-time FIR filtering of parallel 4-way input and output.

[0120] 2. Parallel AGC

[0121] Parallel AGC uses multiple parallel non-closed loop modes, and the corresponding structure diagram is as follows Figure 4 As shown: Where z(k) is the input digital signal, which is a multi-item parallel data. The module first calculates the instantaneous power value corresponding to the input digital signal, and then subtracts it from the target power p to obtain an error digital signal e. The error digital signal is then sent to a first-order loop filter to complete the loop filtering. Finally, the absolute value of the filtered control digital signal is calculated to obtain the digital signal gain G. Finally, G is multiplied by the input digital signal to complete the power adjustment. The corresponding gain expression is:

[0122] G k+1 =G k -γ(|G k Z k | 2 -p)

[0123] In the formula, G k+1 Indicates the current gain value, G krepresents the last increment, γ represents the filter coefficient, |G k z k | 2 -p indicates the error between the power value and the target value after the last adjustment; Z k represents the digital sampling signal, and p represents the target power.

[0124] 3. Parallel symbol synchronization

[0125] Parallel symbol synchronization is an algorithm based on a dual feedback structure composed of two control digital signals, namely: the feedback digital signal used to control the deletion or retention of FIFO sampling points, and the feedback digital signal used to adjust the phase angle of each frequency domain component. The corresponding structural block diagram is shown in Figure 5 As shown, first, the O&M error extraction module extracts the error estimation digital signal from the output sampling point clock of APRX; then the loop filter filters the error estimation digital signal to obtain a new estimation value; finally, the filtered estimation value is sent to the NCO module, and the NCO performs accumulation operation on the estimation value to obtain the corresponding clock phase error. Then the NCO separates the clock phase error into two control digital signals, namely: the corresponding sampling point deviation component m with one sampling point and the frequency domain time deviation component δ. The former controls the FIFO to maintain / intercept the sampling point in the FIFO, thereby increasing / decreasing the time of one sampling point; the latter is directly embedded in each frequency domain component, and the clock error is adjusted by adjusting the phase rotation angle of each frequency domain component.

[0126] The O&M algorithm implementation principle diagram is shown in Figure 6: Its input sampling point is the last N points of the APRX output sequence, and the corresponding number of symbols is N / 4, that is, each symbol corresponds to four sampling points. m The real part and imaginary step are respectively composed of the corresponding N / 4 branches added in parallel, where each branch also uses a square unit and an addition unit. m The complex unit consisting of the real and imaginary parts of the phase angle is calculated by Cordic to obtain an unbiased estimate of the phase angle. This structure will simplify the hardware implementation. The resulting structure diagram of the frequency domain parallel error extraction is as follows: Figure 5 shown.

[0127] 4. Parallel frame synchronization

[0128] The frame header capture of the present invention adopts the method of differential autocorrelation peak; and the frame tracking adopts the window tracking strategy, that is, the frame length information obtained after Reed-Muller decoding is used to infer the position of the next frame header, and the frame header symbol is extracted at the same time, and whether these symbols are frame header symbols is verified. If it is, continue to look for the next frame header and continue to verify; if it is not a frame header, recapture the frame header, and so on. Therefore, after the data in the scheme enters the frame synchronization, it is divided into two paths and sent to different sub-modules respectively. One path of data is sent to the differential correlation peak detection module. The other path of data is sent to the constellation demapping module and the Reed-Muller decoding module to obtain MODCOD. The peak and MODCOD are then sent to a state machine module, which can verify whether the current symbol is a frame header symbol and make a judgment. Once the frame header is tracked, the corresponding data frame can be sent to the descrambling module to complete the data descrambling and provide support for subsequent data auxiliary synchronization. The corresponding implementation structure block diagram is shown as follows. Figure 7 shown.

[0129] In order to increase the detection probability of peak detection as much as possible, the symbols involved in the correlation operation need to be as many as possible. At the same time, the correlation operation should be compatible with various frame header types in the ACM mode. Therefore, according to the specific frame structure characteristics of the physical frame structure, 32 symbols in the PLSC in the SOF are selected to participate in the correlation operation together, and the other half of the data in the PLSC is not unique in the ACM mode, so it does not participate in the operation. On the other hand, since the digital signal entering the correlator has a certain frequency deviation, a differentiator needs to be added before the correlator to reduce the impact of the frequency deviation on the correlator. The corresponding structural block diagram is as follows Figure 8 shown.

[0130] The frame synchronization method given by the physical frame structure standard and its solution can be used in CCM mode but not in ACM mode. At the same time, the demodulator needs to decode the RM (Reed-Muller) code of the PLSC segment to obtain 7-bit information to determine the code length, frame length and pilot information. The RM code can only be decoded after the demodulation synchronization is completed. Data-assisted synchronization requires the pilot information and frame length information provided by the RM code, and precise phase recovery requires the modulation mode information contained in the RM code. In this way, RM code decoding and synchronization are mutually required, making demodulation impossible. This solution adopts an RM incoherent demodulation algorithm, which eliminates the interference of frequency deviation on RM decoding through differential operations, and demodulates the soft solution value to support RM decoding, thereby meeting the ACM mode requirements.

[0131] 5. Parallel carrier synchronization

[0132] like Fig. 9 As shown, this scheme uses the L&R scheme to estimate the frequency deviation, and finally reduces the digital signal frequency deviation to a smaller frequency by adjusting the loop bandwidth of the loop filter. After that, it can be used to correct the frequency deviation through an accumulator and DDS to restore the carrier. The estimation formula corresponding to L&R is as follows:

[0133]

[0134] In the formula, represents frequency deviation; r(i) is the received pilot symbol, M is a calculation coefficient, which represents a trade-off factor between algorithm complexity and calculation accuracy, (r(ik)) represents r(i) delayed by k samples, conj() represents conjugate calculation; k represents the kth sample, 1 / (π(M+1)) represents frequency normalization, (M+1) is a trade-off factor; N represents the number of sampling points.

[0135] 6. Parallel phase synchronization

[0136] The anti-aliasing in the parallel receiver is processed in parallel, that is, a set of cosine discrete digital signals whose frequency is the local carrier are multiplied in parallel for N sampling points. Therefore, the carrier compensation frequency can be embedded in the local carrier in parallel to adjust the local carrier frequency, thereby reducing the difference between the carrier frequency at the receiving end and the carrier frequency at the transmitting end. The corresponding parallel carrier recovery block diagram is shown in the figure. Fig.10 As shown. At the receiving end, after being sampled by the high-speed ADC at a rate of 4 sampling points per symbol, the sampling sequence is converted from serial to parallel in a ratio of 1:N, and then the N parallel sampling points are subjected to parallel anti-mixing. The carrier compensation frequency of parallel carrier recovery can be obtained through the N output sequences of APRX. First, the N output sequences are passed through a set of parallel phase detectors, and the polarity judgment digital signal is obtained through polarity judgment. The phase error between the output digital signal and the reference digital signal is effectively extracted, thereby obtaining a set of N×1 phase error vectors E; then the extracted error vector E is passed through a parallel digital loop filter to suppress input noise and adjust the loop correction speed. The loop filter generates a corresponding control digital signal W; according to the output of the parallel loop filter, the parallel digital control oscillator NCO obtains different frequency control words to change the carrier compensation frequency Φ output by the NCO. In this way, the phase error gradually decreases, thereby gradually approaching the carrier frequency deviation value, and finally locking the phase error to achieve parallel carrier recovery. Therefore, the basic structure of the all-digital parallel carrier recovery based on APRX is similar to the traditional carrier recovery module. The parallel carrier recovery module is also mainly composed of three modules:

[0137] 7. Parallel Balancing

[0138] The structure diagram of the parallel frequency domain CMA algorithm is as follows: Fig.11 If you want to effectively suppress the different phase rotations of each frequency component, you can multiply the corresponding coefficients for different frequency components in the frequency domain: This means that in the time domain, different time delay compensations are introduced for different frequency components, thereby suppressing the influence of channel distortion on the digital signal. Fig.11 As can be seen in the figure, the frequency domain error extraction module calculates the phase rotation values ​​of different frequency domain components by processing the N-point output sequence of APRX. Then, the phase compensation value is embedded into each component through the frequency domain characteristics of APRX to suppress the phase rotation caused by channel distortion and finally achieve the purpose of digital signal equalization.

[0139] The implementation structure diagram of the parallel frequency domain CMA algorithm is as follows: Fig.12 As shown. The algorithm consists of two modules, namely the cost function gradient module and the compensation coefficient update module. Based on the knowledge in the previous section, we can know that the cost function gradient module is implemented. This module calculates the corresponding gradient of N sampling points and needs to descend the vector That is, the vector value increment of each frequency domain component of the digital signal at this moment needs to be compensated. The compensation coefficient update module controls the vector and a suitable step size μ, the compensation value of each frequency domain can be updated. The receiver adjusts the frequency domain compensation component once for each frame (N sampling points) of data processed. By continuously adjusting the frequency domain compensation component, the eye diagram of the digital signal will gradually open, so that the constellation points can converge.

[0140] The cost function is:

[0141]

[0142] In the formula, represents the corresponding gradient descent vector of the sampling point; N represents the number of sampling points; n represents an integer from 0 to N, and R2 represents the target value, that is, z n+N Indicates the nth vector currently being calculated; Θ represents the Hadamard product. If it is a vector operation, then the Θ operation refers to the dot product of the vector; Y is the output value of the equalizer; F n+N is a 2N×1 Fourier vector.

[0143] 9. Parallel LDPC decoding

[0144] This design uses the modified minimum sum decoding algorithm to achieve decoding.

[0145] v: variable node, corresponding to the message bit in the LDPC codeword;

[0146] c: check node, corresponding to the check bit in the LDPC codeword;

[0147] λ v: The log-likelihood ratio of the posterior probability of the variable node v. In this algorithm, λ v is defined as follows:

[0148]

[0149] λ v→c : The message from variable node v to check node c;

[0150] Λ c→v : Check the message sent by node c to variable node v;

[0151] S(c): the variable node set consisting of all variable nodes connected to the check node c;

[0152] S(c)\v: the variable node set consisting of all variable nodes connected to the check node c except the variable node v;

[0153] η: Correction coefficient of the minimum sum algorithm (0<η<1);

[0154] l: decoding algorithm iteration counter

[0155] MaxIterNum: the maximum number of iterations of the decoding algorithm;

[0156] sign: sign function, its operation rules are as follows:

[0157]

[0158] There is a certain mapping relationship between the address of the parity node connected to the check node and the address of the check node itself, and there is a certain mapping relationship between the address of the variable node connected to them and the address of the variable node connected to the check node at the beginning of the row. Mapping relationship of parity node addresses: Assuming that the address of the check node itself is addr_cn_j (0≤j≤NK-1), then:

[0159] For the check node cn_0, ​​it is only connected to one parity node, and the address of this parity node is:

[0160] addr_cn_0_pn_1 = K.

[0161] For the check nodes cn_j (1≤j≤NK-1), they are all connected to two parity nodes, whose addresses are:

[0162] addr_cn_j_pn_1=K+addr_cn_j-1

[0163] addr_cn_j_pn_2=K+addr_cn_j.

[0164] In the above description, N is the code length and K is the message frame length.

[0165] Mapping rules for variable node addresses: Assuming that the address of the variable node connected to the check node at the beginning of the row (i.e., column 0) is addr_vn_col_0, then the address of the variable node connected to the check node at column i (0≤i≤359) in the same row is

[0166]

[0167] According to the above address mapping rules, we can calculate Fig.13 The addresses of all variable nodes and parity nodes connected to a row of 360 check nodes are obtained. Then the modified minimum sum algorithm is executed simultaneously for these 360 ​​check nodes to achieve 360-degree parallel decoding.

[0168] If low parallel decoding is required to save logic resources, the parallel architecture needs to be reconstructed. The reconstruction method is described below: First, determine the value of parallelism M, which must be a factor of 360. Then, calculate the sampling factor L based on the selected parallelism:

[0169]

[0170] Finally, according to the sampling factor L Fig.13 Each row in the 360-degree parallel architecture is sampled and reconstructed. The sampling and reconstruction method is as follows: starting from the kth (0≤k≤L-1)th column of each row, with the sampling factor L as the interval, M check nodes are sampled to reconstruct the processing object group of a decoding operation of a parallel decoder with a parallel degree of M. Therefore, the corresponding structural block diagram is as follows Fig.13 shown.

[0171] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0172] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for implementing a DVB high-speed demodulator using FPGA, characterized in that: The following steps are involved: Step S1, the digital signal enters the parallel DDC module, and the sampling rate of the digital signal is re-adapted to a multiple symbol rate after passing through the parallel DDC module; Step S2, the digital signal passes through a parallel AGC module, and the AGC module adjusts the power of the digital signal to a fixed power value; Step S3, parallel symbol synchronization; the clock error is extracted by using the O&M algorithm, the clock error is filtered by the loop filter, and then passed through the NCO control module to adjust the symbol phase, that is, to complete the symbol synchronization; Step S4, parallel frame synchronization, extracting correlation peaks according to the digital signal that completes symbol synchronization, thereby completing frame synchronization; Step S5, parallel carrier synchronization; extracting frequency deviation through L&R algorithm and correcting the frequency; Step S6, parallel phase synchronization; extracting the phase error, sending the error to a loop filter, filtering out the false burr digital signal by the loop filter, and performing frequency compensation on the digital signal after the loop filter, thereby compensating the phase of the digital signal itself; Step S7, parallel equalization; for the defect of high bandwidth distortion, the error information is calculated and filtered, and the digital signal is compensated; Step S8: After the equalization is completed, the digital signal enters the decoding operation, thereby restoring the original information of the digital signal.

2. The FPGA implementation method of a DVB high-speed demodulator according to claim 1, characterized in that: In step S1, the sampling rate of the digital signal is re-adapted to a multiple of the symbol rate as follows: Assume that the digital signal x(m) is T s The analog digital signal x is the sampling rate a (mT s ), pass x(m) through an interpolation filter h(t) to obtain an analog digital signal y(t); In the formula, y a (t) represents the digital signal after digital interpolation filtering, h(t-mT s ) represents the digital accumulation form of the interpolation filter; m represents the mth sampling; t represents time; mT s represents the mth time period; Use the new sampling rate T for y(t) i Sampling is performed to obtain the digital signal of y(t) at the new sampling rate: Where y(k) represents the digital signal at the new sampling rate; h(kT i -mT s ) represents the cumulative form of the interpolation filter after adjusting the coefficients; kT i Indicates time; mT s represents the mth time period; Let kT i =(m k +μ k )T s , define the following variables: The calculation of the resampling filter is then expressed as follows: Where, T s Represents the sampling rate, m k is the interpolation base point, which indicates that the interpolator performs interpolation at this moment; μ k Indicates time kT i With m k T s The difference between the optimal interpolation moment and the base point, x(m k -i) represents the sample at the previous moment, h(μ k +i) indicates that the filter is in (μ k +i) corresponding to the phase; N1, N2 represent the sampling samples from N1 to N2; μ k represents fractional delay; i represents filter index; m k Indicates the base point index.

3. The FPGA implementation method of a DVB high-speed demodulator according to claim 2, characterized in that: In step S2, the AGC module adjusts the power of the digital signal to a fixed power value as follows: Assume that the digital signal input to the AGC module is z(k); the AGC module first calculates the instantaneous power value corresponding to the input digital signal, and then subtracts it from the target power p to obtain an error digital signal e; then the error digital signal is sent to a first-order loop filter to complete the loop filtering, and finally the absolute value of the filtered control digital signal is calculated to obtain the digital signal gain G, and finally G is multiplied by the input digital signal to complete the power adjustment, where the corresponding gain expression is: G k+1 =G k -γ(|G k Z k | 2 -p) In the formula, G k+1 Indicates the current gain value, G k represents the last increment, γ represents the filter coefficient, |G k z k | 2 -p indicates the error between the power value and the target value after the last adjustment; Z k represents the digital sampling signal, and p represents the target power.

4. The FPGA implementation method of a DVB high-speed demodulator according to claim 3, characterized in that: In step S3, the clock error information is extracted, filtered by a loop filter, and then sent to the NCO control module, thereby completing symbol synchronization. Specifically, the following steps are included: First, the O&M error extraction module extracts the error estimation digital signal from the output sampling point clock of the APRX; then the loop filter filters the error estimation digital signal to obtain a new estimation value; finally, the filtered estimation value is sent to the NCO module, and the NCO accumulates the estimation value to obtain the corresponding clock phase error; then the NCO separates the clock phase error into two control digital signals; The extracted clock error is: Where: x k represents the oversampled data entering the module; N represents the oversampling multiple; L represents the number of symbol samples corresponding to the estimation; m represents the current mth phase error estimation, e -j2πk / N represents the Fourier calculation coefficient; (m+1) represents the (m+1)th phase error estimation, (m+1)LN-1 represents the (m+1)LN-1th symbol, and k represents the kth sample.

5. The FPGA implementation method of a DVB high-speed demodulator according to claim 4, characterized in that: In step S4, parallel frame synchronization is specifically as follows: after symbol synchronization is completed, the best sampling data with 1 times oversampling is obtained, and the data is divided into two paths and sent to different sub-modules after entering the frame synchronization; one path of data is sent to the differential correlation peak detection module; the other path of data is sent to the constellation demapping module and the Reed-Muller decoding module to obtain MODCOD; then the peak value and MODCOD are sent to a state machine module for judgment, and the state machine module is used to verify whether the current symbol is a frame header symbol and make a judgment; if it is judged to be a frame header, the corresponding data frame can be sent to the descrambling module to complete the data descrambling, and if it is not a frame header, the frame header is recaptured.

6. The FPGA implementation method of a DVB high-speed demodulator according to claim 5, characterized in that: In step S5, the parallel carrier synchronization is specifically as follows: The frequency deviation is estimated through the L&R algorithm, and the loop bandwidth of the loop filter is adjusted to reduce the frequency deviation of the digital signal. Finally, it can be used to correct the frequency deviation through an accumulator and DDS to recover the carrier.

7. The FPGA implementation method of a DVB high-speed demodulator according to claim 6, characterized in that: The L&R algorithm is shown below: In the formula, represents frequency deviation; r(i) is the received pilot symbol, M is a calculation coefficient, which represents a trade-off factor between algorithm complexity and calculation accuracy, (r(ik)) represents r(i) delayed by k samples, conj() represents conjugate calculation; k represents the kth sample, 1 / (π(M+1)) represents frequency normalization, (M+1) is a trade-off factor; N represents the number of sampling points.

8. The FPGA implementation method of a DVB high-speed demodulator according to claim 1, characterized in that: In step S6, the parallel phase synchronization is specifically as follows: First, N output sequences are passed through a group of parallel phase detectors, and polarity judgment digital signals are obtained through polarity judgment. The phase error between the output digital signal and the reference digital signal is extracted to obtain a group of N×1 phase error vectors E; then the extracted error vector E is passed through a parallel digital loop filter to suppress input noise and adjust the loop correction speed, and the loop filter generates a corresponding control digital signal W; according to the output of the parallel loop filter, the parallel numerically controlled oscillator NCO obtains different frequency control words to change the carrier compensation frequency Φ output by the NCO.

9. The FPGA implementation method of a DVB high-speed demodulator according to claim 1, characterized in that: In step S7, parallel equalization is implemented by a parallel frequency domain CMA algorithm, which includes a cost function gradient calculation module and a compensation coefficient update module, wherein the cost function gradient calculation module is used to calculate the corresponding gradient drop vector ▽ of multiple sampling points; and the compensation coefficient update module controls the vector And the appropriate step size μ, the compensation value of each frequency domain can be updated.

10. The FPGA implementation method of a DVB high-speed demodulator according to claim 9, characterized in that: The frequency domain CMA algorithm is specifically shown in the following formula: In the formula, represents the corresponding gradient descent vector of the sampling point; N represents the number of sampling points; n represents an integer from 0 to N, and R2 represents the target value, that is, z n+N represents the nth vector currently being calculated; Θ represents the Hadamard product, Y is the output value of the equalizer; F n+N is a 2N×1 Fourier vector.

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