Method for reducing SiC-MOS device interface state density and MOS capacitor

Abstract

The invention provides a method for reducing the interface state density of a SiC-MOS device and an MOS capacitor. The method comprises the following steps: providing a silicon carbide substrate; forming a silicon dioxide oxide layer on the silicon carbide substrate; pure oxygen annealing is carried out by adopting a rapid annealing process; pure nitrogen annealing is carried out by adopting a rapid annealing process; forming a gate electrode on the silicon dioxide oxide layer; and forming a substrate electrode at the bottom of the silicon carbide substrate to obtain the SiC-MOS capacitor. According to the invention, the two-step annealing process of low-pressure pure oxygen annealing and pure nitrogen annealing is carried out on the silicon dioxide (SiO2) / silicon carbide (SiC) interface, so that the device has relatively low interface state density and relatively high flat-band voltage stability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit devices, and in particular to a method for reducing interface state density of a SiC-MOS device and a MOS capacitor. Background Art

[0002] With the booming development of industries such as computers, power regulation / transmission / distribution, industrial motor control, automotive electronics, aircraft and ships, these fields have an increasing demand for electronic devices that can serve under harsh working conditions such as high power, high voltage and high temperature.

[0003] In the semiconductor industry, silicon carbide (SiC) has excellent properties such as large bandgap, high critical breakdown field strength, high thermal conductivity, and high saturated carrier drift rate. These properties make it show great application potential in the field of high-temperature, high-frequency, and high-power devices. However, in practical applications, there are high-density interface states at the silicon dioxide (SiO2) / silicon carbide (SiC) interface. These interface states seriously restrict the electrical performance of silicon carbide-based devices, making the actual channel carrier mobility far lower than the theoretical value. At the same time, it also leads to problems such as increased device leakage current, reduced switching speed, increased on-resistance, and reduced device threshold voltage stability.

[0004] At present, the methods for reducing the interface state density of silicon dioxide (SiO2) / silicon carbide (SiC) are mainly focused on the annealing process after the interface is formed. Although the traditional annealing in NO or N2O atmosphere can effectively reduce the interface state density, the toxicity of NO gas limits its application in actual production. In addition, due to the presence of O, there is inevitably a competitive reaction between O and N during the annealing process, which limits the passivation efficiency. Other studies have shown that when the nitridation annealing time is too long, the annealing reduces the original interface state of silicon dioxide (SiO2) / silicon carbide (SiC) and also produces additional interface ultrafast states, forming carrier scattering centers. Therefore, N atoms are introduced to the interface at a suitable concentration. In recent years, some studies have also replaced the annealing gas with nitrogen (N2), which has also achieved a certain effect of reducing the interface state. In addition, N2 is safer than toxic NO, and it also limits the additional oxidation of the substrate during the annealing process. However, due to the excessive stability of the chemical properties of N2, annealing usually needs to be carried out under harsh conditions of ultra-high temperature (over 1350°C).

[0005] The search found:

[0006] The Chinese invention patent with application publication number CN114843185A discloses a method for preparing a silicon carbide device, which comprises preparing an oxide layer on a silicon carbide substrate; performing a thermal annealing treatment in an oxygen atmosphere at a temperature of 900°C to 1100°C; and performing subsequent processes to form the silicon carbide device. The patent has limited effect in reducing the interface state density of silicon dioxide (SiO2) / silicon carbide (SiC), and its best result E C The interface state density at -0.2 eV is about 1.25×10 12 cm -2 eV -1 .

[0007] The Chinese invention patent with application publication number CN111048413A discloses a method for manufacturing a gate oxide layer on a silicon carbide material. In a low-pressure environment, silicon dioxide with a thickness of 50-70nm is deposited on the surface of silicon carbide by thermal decomposition of tetraethyl orthosilicate; then the silicon carbide substrate forming the main oxide layer is subjected to a first high-temperature annealing in an oxygen environment; then the oxide layer is subjected to a second high-temperature annealing in a nitrogen atmosphere; and finally, the silicon carbide substrate forming the oxide layer is subjected to a third high-temperature treatment in argon. This patent requires the deposition of 50-70nm thick silicon dioxide on the surface of silicon carbide by thermal decomposition of tetraethyl orthosilicate. The three-step annealing process is cumbersome and costly. Summary of the invention

[0008] In view of the defects in the prior art, an object of the present invention is to provide a method for reducing the interface state density of a SiC-MOS device and a MOS capacitor.

[0009] The objective of the present invention is achieved through the following technical solutions:

[0010] According to one aspect of the present invention, there is provided a method for reducing the interface state density of a SiC-MOS device, comprising:

[0011] Providing a silicon carbide substrate;

[0012] forming a silicon dioxide oxide layer on the silicon carbide substrate;

[0013] Pure oxygen annealing is performed using a rapid annealing process;

[0014] The rapid annealing process is used for pure nitrogen annealing;

[0015] forming a gate electrode on the silicon dioxide oxide layer;

[0016] A substrate electrode is formed at the bottom of the silicon carbide substrate to obtain a SiC-MOS capacitor.

[0017] Optionally, a silicon dioxide oxide layer is formed on the silicon carbide substrate, wherein the silicon dioxide oxide layer is prepared by any one of thermal oxidation, sputtering, CVD and ALD.

[0018] Optionally, a silicon dioxide oxide layer is formed on the silicon carbide substrate, wherein: the thickness of the silicon dioxide oxide layer is 5-100 nm.

[0019] Optionally, the pure oxygen annealing is performed using a rapid annealing process, wherein: the annealing temperature is 700-900° C., the annealing time is 1-30 min, and the O2 pressure is 0.001-0.01 atm.

[0020] Optionally, the pure oxygen annealing is performed using a rapid annealing process, wherein: O2 is introduced when the annealing furnace reaches a preset temperature, and O2 is turned off and the O2 in the cavity is purged before the temperature drops.

[0021] Optionally, the rapid annealing process is used for pure nitrogen annealing, wherein: the annealing temperature is 700-1600° C., the annealing time is 1-120 min, and N2 is passed throughout the annealing process.

[0022] Optionally, forming a gate electrode on the silicon dioxide oxide layer comprises: preparing the gate electrode on the silicon dioxide oxide layer by sputtering or thermal evaporation, and patterning the gate electrode by photolithography or hard mask method.

[0023] Optionally, forming a substrate electrode at the bottom of the silicon carbide substrate includes: after removing an oxide layer at the bottom of the silicon carbide substrate, preparing a substrate electrode at the bottom of the silicon carbide substrate by sputtering or thermal evaporation.

[0024] Optionally, the method has at least one of the following features:

[0025] -The material of the silicon carbide substrate is 4H-silicon carbide or 6H-silicon carbide;

[0026] -The material of the gate electrode is Au or Al;

[0027] -The material of the substrate electrode is Al or Ni.

[0028] According to another aspect of the present invention, a SiC-MOS capacitor is provided. The SiC-MOS capacitor is prepared by using the above-mentioned method for reducing the interface state density of a SiC-MOS device.

[0029] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0030] The present invention reduces the additional oxidation of the silicon carbide substrate by performing a two-step annealing process of low-pressure pure oxygen annealing and pure nitrogen annealing on the silicon dioxide (SiO2) / silicon carbide (SiC) interface, and uses non-toxic nitrogen for nitridation, which significantly reduces the silicon dioxide (SiO2) / silicon carbide (SiC) interface state density. C -0.2eV interface state is as low as 1.63×10 11 cm -2 eV -1 (High and low frequency method). In addition, this method also improves the flat band voltage stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0032] Figure 1 A schematic diagram of the structure of a SiC-MOS capacitor according to an embodiment of the present invention;

[0033] Figure 1 Middle: 1 is the substrate electrode, 2 is the silicon carbide substrate layer, 3 is the silicon dioxide oxide layer, and 4 is the gate electrode;

[0034] Figure 2 A schematic diagram of a method of performing pure oxygen annealing using a rapid annealing process in one embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a method of performing pure nitrogen annealing using a rapid annealing process in one embodiment of the present invention;

[0036] Figure 4 The test results of the silicon dioxide (SiO2) / silicon carbide (SiC) interface state density of the device in one embodiment of the present invention;

[0037] Figure 5 The figure is a test result of the flat-band voltage stability of the device in one embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in the present application, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] In addition, in the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs, all of which belong to the scope of protection of the present application.

[0041] A method for reducing the interface state density of a SiC-MOS device provided by an embodiment of the present invention comprises the following steps:

[0042] Step S1, providing a silicon carbide substrate;

[0043] Step S2, forming a silicon dioxide oxide layer on the silicon carbide substrate;

[0044] Step S3, using a rapid annealing process to perform pure oxygen annealing;

[0045] Step S4, using a rapid annealing process to perform pure nitrogen annealing;

[0046] Step S5, forming a gate electrode on the silicon dioxide oxide layer;

[0047] Step S6: forming a substrate electrode at the bottom of the silicon carbide substrate to obtain a SiC-MOS capacitor.

[0048] In some embodiments, in step S1, the material of the silicon carbide substrate is different silicon carbide crystal forms such as 4H-silicon carbide (4H-SiC) or 6H-silicon carbide (6H-SiC), which is specifically determined according to the working conditions and performance requirements of the device.

[0049] In some embodiments, in step S2, before forming the oxide layer, the silicon carbide substrate is cleaned and pretreated to remove surface impurities and contaminants. The silicon dioxide oxide layer is prepared by any one of thermal oxidation, sputtering, CVD and ALD to obtain an oxide layer with a dense structure, uniform thickness and good quality.

[0050] The thickness of the silicon dioxide oxide layer mainly considers factors such as the oxide layer capacitance per unit area, leakage current, and reliability. When the thickness of the silicon dioxide oxide layer is small, the oxide layer capacitance per unit area can be increased, thereby improving the transconductance, cutoff frequency and other performance of the device; but when the thickness of the silicon dioxide oxide layer is too small, it is easy to cause an increase in the leakage current of the device, and excessive leakage current will affect the power consumption and reliability of the device. In addition, the thickness of the silicon dioxide oxide layer is also related to the preparation process. For example, ALD can control the oxide layer thickness more accurately. Preferably, the thickness of the silicon dioxide oxide layer is 5-100nm.

[0051] In some embodiments, in step S3, the annealing temperature is 700-900°C, the annealing time is 1-30 min, and the O2 pressure is 0.001-0.01 atm. The first step of pure oxygen annealing is performed at a relatively low temperature and low pressure, which can avoid direct oxidation of the silicon carbide substrate and avoid the introduction of new defects due to direct oxidation of the substrate. Under the premise of avoiding direct oxidation of the substrate as much as possible, oxygen is used to passivate defects such as oxygen vacancies near the silicon dioxide (SiO2) / silicon carbide (SiC) interface, thereby improving the interface quality. The annealing time is determined according to the thickness of the silicon dioxide oxide layer. The greater the thickness, the longer the annealing time.

[0052] During the pure oxygen annealing process, in order to avoid additional oxidation of the substrate, O2 is introduced when the annealing furnace reaches the preset temperature, namely the annealing temperature. O2 is turned off and the O2 in the cavity is cleared before the cooling process begins. The cooling process is a part of the annealing process. After the annealing time is kept at the annealing temperature, the heating is stopped and the process of cooling to room temperature is called the cooling process.

[0053] In some embodiments, in step S4, the annealing temperature is 700-1600°C, the annealing time is 1-120 minutes, and N2 is passed throughout the annealing process. Pure nitrogen annealing is performed at a relatively high annealing temperature, which can achieve interface nitridation, further passivate silicon dioxide (SiO2) / silicon carbide (SiC) interface defects, improve the quality of the interface, and thus enhance the performance of the device. The higher the nitrogen annealing temperature, the better the nitridation effect, but the corresponding difficulty and cost will increase. Preferably, the pure nitrogen annealing temperature is 700-1000°C. The annealing time is determined according to the thickness of the silicon dioxide oxide layer. The thicker the silicon dioxide oxide layer, the longer the annealing time.

[0054] In some embodiments, in step S5, a gate electrode is prepared on the silicon dioxide oxide layer by sputtering or thermal evaporation, and the gate electrode is patterned by photolithography or a hard mask method.

[0055] The material of the gate electrode is determined by comprehensive factors such as device performance requirements, process compatibility, reliability, and cost. Exemplarily, the material of the gate electrode is a metal material such as Au or Al.

[0056] In some embodiments, in step S6, after removing the oxide layer at the bottom of the silicon carbide substrate, a substrate electrode is prepared at the bottom of the silicon carbide substrate by sputtering or thermal evaporation.

[0057] The material of the substrate electrode is determined by comprehensive factors such as device performance requirements, process compatibility, reliability, and cost. Exemplarily, the material of the substrate electrode is a metal material such as Al or Ni.

[0058] Another embodiment of the present invention provides a SiC-MOS capacitor, which is prepared using the above-mentioned method for reducing the interface state density of SiC-MOS devices. The SiC-MOS capacitor has a lower silicon dioxide (SiO2) / silicon carbide (SiC) interface state density and good flat-band voltage stability.

[0059] like Figure 1 As shown, in a specific embodiment, a silicon carbide MOS capacitor is provided, which includes, from bottom to top, a substrate electrode 1, a silicon carbide substrate layer 2, a silicon dioxide oxide layer 3 and a gate electrode 4; the substrate electrode 1 is an Al film with a thickness of 100 nm; the silicon carbide substrate 2 is a 4H-silicon carbide (4H-SiC) having an n-type nitrogen-doped epitaxial layer, the thickness of the epitaxial layer is 7.28 μm, and the doping concentration of the epitaxial layer is 2.26×10 16 cm -3 The silicon dioxide oxide layer 3 is a silicon dioxide film deposited by the PEALD method, and has a thickness of 10 nm; the gate electrode 4 is an Au film, and has a thickness of 50 nm.

[0060] The method for preparing the silicon carbide MOS capacitor comprises the following steps:

[0061] S1, cleaning the silicon carbide substrate layer 2, using an organic ultrasonic cleaning plus a standard RCA cleaning method to fully clean the silicon carbide substrate;

[0062] S2, a silicon dioxide oxide layer 3 is prepared on the silicon carbide substrate layer 2 by using a PEALD method, wherein the precursors are BTBAS (C8H 22 N2Si) and oxygen plasma, the operating temperature is 200-300℃;

[0063] S3. A rapid annealing process is used for annealing, wherein the annealing temperature is 700-900° C., the annealing time is 1-30 min, the process gas is O2, and the pressure is 0.001-0.01 atm.

[0064] Preferably, in order to avoid additional oxidation of the substrate, O2 is introduced into the annealing furnace only when the temperature reaches a preset value, and O2 is turned off and the O2 in the chamber is purged before the temperature drops. Figure 2 As shown;

[0065] S4, adopt rapid annealing process for annealing, wherein the annealing temperature is 700~1600℃, the annealing time is 1~120min, the process gas is N2, and N2 is passed throughout the annealing process. Figure 3 As shown;

[0066] S5, preparing a gate electrode 4 on the silicon dioxide oxide layer 3 by using a vacuum resistance thermal evaporation method, the electrode material is Au, the electrode thickness is 50nm, and the patterning of the gate electrode 4 is achieved by using a hard mask;

[0067] S6, removing the oxide layer at the bottom of the silicon carbide substrate layer 2, and preparing a substrate electrode 1 at the bottom of the silicon carbide substrate layer 2 by vacuum resistance thermal evaporation, wherein the electrode material is Al and the electrode thickness is 100 nm;

[0068] The above-mentioned embodiment of the present invention implements a two-step annealing process of low-pressure pure oxygen annealing and pure nitrogen annealing on the silicon dioxide (SiO2) / silicon carbide (SiC) interface to reduce additional oxidation of the substrate and use non-toxic nitrogen for nitridation, thereby significantly reducing the silicon dioxide (SiO2) / silicon carbide (SiC) interface state density. Compared with the prior art with application publication number CN111048413A, the number of steps is reduced and the cost is reduced.

[0069] The interface state density of the above embodiment was measured using the high and low frequency method, and the results are as follows: Figure 4 As shown, the interface state at EC-0.2eV is as low as 1.63×1011cm -2 eV -1 , which is about one order of magnitude lower than the EC-0.2eV of the device in the prior art with application publication number CN114843185A. The above embodiment of the present invention has a more significant effect in reducing the interface state density of silicon dioxide (SiO2) / silicon carbide (SiC). In addition, the device in the above embodiment is subjected to stress testing, and a constant voltage stress is applied to the gate to make the electric field of the oxide layer 5MV / cm. The flat band voltage is extracted at intervals, such as Figure 5 As shown, after 1000s of stress, the flat-band voltage offset of the device in the embodiment is less than 0.05V. This result shows that the above embodiment of the present invention can effectively improve the flat-band voltage stability of the device.

[0070] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various modifications or variations within the scope of the claims, which does not affect the essence of the present invention. The above preferred features can be used in any combination without conflicting with each other.

Claims

1. A method for reducing the interface state density of a SiC-MOS device, characterized in that: include: Providing a silicon carbide substrate; forming a silicon dioxide oxide layer on the silicon carbide substrate; Pure oxygen annealing is performed using a rapid annealing process; The rapid annealing process is used for pure nitrogen annealing; forming a gate electrode on the silicon dioxide oxide layer; A substrate electrode is formed at the bottom of the silicon carbide substrate to obtain a SiC-MOS capacitor.

2. The method for reducing the interface state density of SiC-MOS device according to claim 1, characterized in that: A silicon dioxide oxide layer is formed on the silicon carbide substrate, wherein the silicon dioxide oxide layer is prepared by any one of thermal oxidation, sputtering, CVD and ALD.

3. The method for reducing the interface state density of SiC-MOS device according to claim 1, characterized in that: A silicon dioxide oxide layer is formed on the silicon carbide substrate, wherein the thickness of the silicon dioxide oxide layer is 5-100 nm.

4. The method for reducing the interface state density of SiC-MOS device according to claim 1, characterized in that: The pure oxygen annealing is performed by adopting a rapid annealing process, wherein: the annealing temperature is 700-900° C., the annealing time is 1-30 minutes, and the O2 pressure is 0.001-0.01 atm.

5. The method for reducing interface state density of SiC-MOS device according to claim 1, characterized in that: The pure oxygen annealing is performed by adopting a rapid annealing process, wherein: O2 is introduced when the annealing furnace reaches a preset temperature, and O2 is turned off and the O2 in the cavity is cleared before the temperature drops.

6. The method for reducing interface state density of SiC-MOS device according to claim 1, characterized in that: The rapid annealing process is used for pure nitrogen annealing, wherein: the annealing temperature is 700-1600° C., the annealing time is 1-120 min, and N2 is passed throughout the annealing process.

7. The method for reducing the interface state density of SiC-MOS device according to claim 1, characterized in that: The gate electrode is formed on the silicon dioxide oxide layer, comprising: preparing the gate electrode on the silicon dioxide oxide layer by sputtering or thermal evaporation, and patterning the gate electrode by photolithography or hard mask method.

8. The method for reducing interface state density of SiC-MOS device according to claim 1, characterized in that: Forming a substrate electrode at the bottom of the silicon carbide substrate comprises: after removing the oxide layer at the bottom of the silicon carbide substrate, preparing the substrate electrode at the bottom of the silicon carbide substrate by sputtering or thermal evaporation.

9. The method for reducing interface state density of SiC-MOS device according to claim 1, characterized in that: Have at least one of the following characteristics: -The material of the silicon carbide substrate is 4H-silicon carbide or 6H-silicon carbide; -The material of the gate electrode is Au or Al; -The material of the substrate electrode is Al or Ni.

10. A SiC-MOS capacitor, characterized in that: The method for reducing the interface state density of a SiC-MOS device according to any one of claims 1 to 9 is used to prepare the device.

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