High-voltage NLDMOS structure and manufacturing method thereof

Abstract

The invention provides a high-voltage NLDMOS (N-type laterally diffused metal oxide semiconductor) structure which comprises a P-type substrate, and an N-type injection region is formed in a region, close to a drain end, of the substrate; an N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on a field oxide region of the epitaxial layer; a P well is formed on the epitaxial layer, and a P-type doped layer close to the upper surface of the epitaxial layer is formed on the epitaxial layer below the source end and the field oxide layer; the gate structure comprises a gate dielectric layer and a gate polycrystalline silicon layer, one end of the gate polycrystalline silicon layer extends to the P well, the other end of the gate polycrystalline silicon layer extends to the adjacent field oxide layer, and the drain polycrystalline silicon field plate is located on the field oxide layer close to the drain end; an N-type source end heavily doped region, an N-type drain end heavily doped region and a P-type heavily doped P well lead-out region; the interlayer dielectric layer is located between the source end and the drain end, and a contact piece used for leading out the drain end polycrystalline silicon field plate is formed on the interlayer dielectric layer. The breakdown voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-voltage NLDMOS structure and a manufacturing method thereof. Background Art

[0002] High voltage (such as 1100V) LDMOS has the characteristics of high voltage and large current of discrete devices, and also absorbs the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can realize the functions that originally required multiple chips, greatly reducing the area, reducing costs, and improving energy efficiency. It is in line with the development direction of miniaturization, intelligence, and low energy consumption of modern power electronic devices.

[0003] The breakdown voltage is a key parameter for measuring high-voltage devices. The existing technology can increase the depletion of the drift region (such as Figure 1 As shown), the surface electric field reduction (Resurf) effect is achieved, but the breakdown voltage of this structure still does not meet actual needs.

[0004] In order to solve the above problems, it is necessary to propose a novel high-voltage NLDMOS structure and a manufacturing method thereof. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a high-voltage NLDMOS structure and a manufacturing method thereof, so as to solve the problem that the breakdown voltage of the high-voltage LDMOS in the prior art needs to be improved.

[0006] To achieve the above objectives and other related objectives, the present invention provides a high voltage NLDMOS structure, including:

[0007] A P-type substrate, wherein an N-type implantation region is formed in a region of the substrate close to a drain terminal;

[0008] An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxygen region of the epitaxial layer;

[0009] A P well is formed on the epitaxial layer, and a P-type doping layer is formed on the epitaxial layer at the source end and below the field oxide layer and close to the upper surface of the epitaxial layer;

[0010] A gate structure and a drain polysilicon field plate, wherein the gate structure comprises a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P well, and the other end thereof extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer near the drain end;

[0011] N-type heavily doped source end region and drain end region and P-type heavily doped P-well lead-out region;

[0012] An interlayer dielectric layer located between the source and drain terminals, with a contact element for leading out the polysilicon field plate of the drain terminal formed on the interlayer dielectric layer;

[0013] The first and second metal layers are located at the source and drain ends, the first metal layer serves as the source end heavily doped region, the lead end of the P-well lead-out region and the source end metal field plate, and the second metal layer serves as the contact and the drain end heavily doped region lead-out end and the drain end metal field plate.

[0014] Preferably, the gate dielectric layer is a thermal oxide layer.

[0015] Preferably, the material of the interlayer dielectric layer is silicon dioxide.

[0016] Preferably, the first and second metal layers are made of aluminum.

[0017] Preferably, the N-type implantation region consists of a plurality of spaced implantation regions.

[0018] The present invention also provides a method for manufacturing the above-mentioned high-voltage NLDMOS structure, comprising:

[0019] Step 1: providing a P-type substrate, and forming an N-type implantation region in a region of the substrate near the drain end by ion implantation;

[0020] Step 2: forming an N-type epitaxial layer on the substrate, and forming a field oxide layer on the field oxide region of the epitaxial layer;

[0021] Step 3: forming a P well on the epitaxial layer by ion implantation, and forming a P-type doped layer close to the upper surface of the epitaxial layer on the epitaxial layer at the source end and below the field oxide layer by ion implantation;

[0022] Step 4: forming a gate structure and a drain polysilicon field plate, wherein the gate structure includes a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P well, and the other end thereof extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer close to the drain end;

[0023] Step 5: using ion implantation to form an N-type heavily doped source end region and a heavily doped drain end region and a P-type heavily doped P-well lead-out region;

[0024] Step six, forming an interlayer dielectric layer between the source and drain terminals, and forming a contact for leading out the polysilicon field plate of the drain terminal on the interlayer dielectric layer; forming a first and a second metal layer at the source and drain terminals, wherein the first metal layer serves as the lead-out terminal of the source terminal heavily doped region, the lead-out terminal of the P-well lead-out region, and the source terminal metal field plate, and the second metal layer serves as the contact and the lead-out terminal of the drain terminal heavily doped region and the drain terminal metal field plate.

[0025] Preferably, the N-type implantation region in step 1 is composed of a plurality of spaced implantation regions.

[0026] Preferably, the method of forming the field oxide layer in step 2 comprises: forming a groove on the epitaxial layer by photolithography and etching; and forming the field oxide layer filling the groove.

[0027] Preferably, the method for forming the gate structure and the drain polysilicon field plate in step four includes: forming the gate dielectric layer; depositing a polysilicon layer; and patterning the gate dielectric layer and the polysilicon layer by photolithography and etching to form the gate polysilicon layer and the drain polysilicon field plate.

[0028] Preferably, in step four, the gate dielectric layer is formed by thermal oxidation.

[0029] Preferably, the material of the interlayer dielectric layer in step six is ​​silicon dioxide.

[0030] Preferably, the material of the first and second metal layers in step six is ​​aluminum.

[0031] As described above, the high voltage NLDMOS structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0032] The N-type implantation region of the present invention increases the drain end depletion region area and can introduce a new electric field peak between the surface U-type electric field peaks, thereby reducing the electric field peak of the surface U-type electric field and improving the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a schematic diagram of a high voltage NLDMOS structure of the prior art;

[0034] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0035] Figure 3 Shown is a schematic diagram of the N-type implantation region layout of the present invention;

[0036] Figure 4 It is a schematic diagram showing the formation of an N-type implantation region and an epitaxial layer on a substrate according to the present invention;

[0037] Figure 5 Shown is a schematic diagram of forming a field oxide layer according to the present invention;

[0038] Figure 6 It is a schematic diagram of forming a P well according to the present invention;

[0039] Figure 7 It is a schematic diagram of forming a P-type doping layer according to the present invention;

[0040] Figure 8 It is a schematic diagram showing the formation of a gate structure and a drain-end polysilicon field plate according to the present invention;

[0041] Fig. 9 It is a schematic diagram showing the formation of a source end heavily doped region, a drain end heavily doped region and a P-well lead-out region according to the present invention;

[0042] Fig.10 It is a schematic diagram showing the formation of the first and second metal layers of the present invention;

[0043] Fig.11 It is a schematic diagram comparing the surface electric field of a device having a prior art structure of the present invention and a structure of an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Fig.10 The present invention provides a high voltage NLDMOS structure, comprising:

[0046] A P-type substrate 101, with an N-type implantation region 102 formed in a region of the substrate 101 close to a drain terminal;

[0047] In some embodiments, the N-type implant region 102 is composed of a plurality of spaced implant regions.

[0048] See also Figure 3 By adjusting the layout, the N-type implant is implanted at intervals in the W (width) direction and the L (length) direction. Through diffusion, the doping concentration of the N-type implant in the L direction and the W direction can be self-regulated with only one step of implantation. The electric field can be further reduced at places where the surface electric field strength is high, and the electric field can be raised at places where the surface electric field strength is low, so as to realize self-regulation of the surface electric field and increase the breakdown voltage by about 130V. At the same time, the interval implantation can prevent excessive longitudinal diffusion and affect the doping concentration on the device surface.

[0049] An N-type epitaxial layer 103 is formed on the substrate 101, and a field oxide layer 104 is formed on the field oxide region of the epitaxial layer 103;

[0050] A P well 105 is formed on the epitaxial layer 103 , and a P type doping layer 106 is formed on the epitaxial layer 103 near the upper surface of the epitaxial layer 103 at the source end and below the field oxide layer 104 ;

[0051] The gate structure and the drain polysilicon field plate 108b, the gate structure includes a gate dielectric layer 107 and a gate polysilicon layer 108a, one end of the gate polysilicon layer 108a extends to the P well 105, and the other end thereof extends to the adjacent field oxide layer 104, and the drain polysilicon field plate 108b is located on the field oxide layer 104 close to the drain end;

[0052] In some embodiments, the gate dielectric layer 107 is a thermal oxide layer.

[0053] N-type heavily doped source region 109b and drain region 109a and P-type heavily doped P-well lead-out region 110;

[0054] An interlayer dielectric layer 111 located between the source and drain terminals, on which a contact for leading out the polysilicon field plate 108b of the drain terminal is formed;

[0055] In some embodiments, the material of the interlayer dielectric layer 111 is silicon dioxide.

[0056] The first and second metal layers are located at the source and drain ends. The first metal layer 112a serves as the lead-out end of the source end heavily doped region 109b, the P-well lead-out region 110 and the source end metal field plate. The second metal layer 112b serves as the contact and the lead-out end of the drain end heavily doped region 109a and the drain end metal field plate. The source end metal field plate and the drain end metal field plate play a role in increasing the peak electric field on the surface of the drift region, thereby increasing the breakdown voltage.

[0057] In some embodiments, the material of the first and second metal layers is aluminum.

[0058] See also Fig.11 , which shows a schematic diagram comparing the surface electric field of the device of the prior art structure and the structure of an embodiment of the present invention. An N-type injection region 102 is injected into the drift region near the bottom of the drain terminal before the N-type epitaxial layer 103 is formed, so its depth is deeper than the injection depth of the P-type doped layer 106. The N-type injection region 102 increases the area of ​​the drain depletion region and can introduce a new electric field peak between the surface U-type electric field peaks, thereby reducing the electric field peak of the surface U-type electric field and improving the breakdown voltage.

[0059] See also Figure 2 The present invention also provides a method for manufacturing the above-mentioned high-voltage NLDMOS structure, comprising:

[0060] Step 1: Provide a P-type substrate 101, and use ion implantation to form an N-type implantation region 102 in the region near the drain end of the substrate 101, forming a Figure 4 The structure shown;

[0061] See also Figure 3By adjusting the layout, the N-type implant is implanted at intervals in the W direction and the L direction. Through diffusion, the doping concentration of the N-type implant in the L direction and the W direction can be self-regulated with only one step of implantation. The electric field can be further reduced at places where the surface electric field strength is high, and the electric field can be raised at places where the surface electric field strength is low, so as to realize self-regulation of the surface electric field and increase the breakdown voltage by about 130V. At the same time, the interval implantation can prevent excessive longitudinal diffusion and affect the doping concentration on the device surface.

[0062] Step 2: Form an N-type epitaxial layer 103 on the substrate 101. The N-type epitaxial layer 103 serves as a drift region. Form a field oxide layer 104 on the field oxide region of the epitaxial layer 103. Figure 5 The structure shown;

[0063] In some embodiments, the method of forming the field oxide layer 104 in step 2 includes: forming a trench on the epitaxial layer 103 by photolithography and etching; and forming the field oxide layer 104 filling the trench.

[0064] Step 3: Form a P well 105 on the epitaxial layer 103 by ion implantation. The P well 105 serves as a body region. Figure 6 The structure shown in FIG. 1 is formed by ion implantation on the epitaxial layer 103 below the source end and the field oxide layer 104 to form a P-type doped layer 106 near the upper surface of the epitaxial layer 103, as shown in FIG. Figure 7 The structure shown;

[0065] Step 4: Form a gate structure and a drain polysilicon field plate 108b. The gate structure includes a gate dielectric layer 107 and a gate polysilicon layer 108a. One end of the gate polysilicon layer 108a extends to the P well 105, and the other end extends to the adjacent field oxide layer 104. The drain polysilicon field plate 108b is located on the field oxide layer 104 near the drain end, forming a gate structure as shown in FIG. Figure 8 The structure shown;

[0066] In some embodiments, the method of forming a gate structure and a drain polysilicon field plate 108b in step four includes: forming a gate dielectric layer 107; depositing a polysilicon layer; and patterning the gate dielectric layer 107 and the polysilicon layer by photolithography and etching to form a gate polysilicon layer 108a and a drain polysilicon field plate 108b.

[0067] In some embodiments, in step 4, the gate dielectric layer 107 is formed by thermal oxidation.

[0068] Step 5: Use ion implantation to form an N-type source heavily doped region 109b, a drain heavily doped region 109a, and a P-type heavily doped P-well lead-out region 110, forming Fig. 9 The structure shown;

[0069] Step 6: Form an interlayer dielectric layer 111 between the source and drain terminals, and form a contact for leading out the polysilicon field plate 108b of the drain terminal on the interlayer dielectric layer 111; form the first and second metal layers at the source and drain terminals, the first metal layer 112a is used as the lead-out terminal of the source terminal heavily doped region 109b, the P-well lead-out region 110 and the source terminal metal field plate, and the second metal layer 112b is used as the contact and the lead-out terminal of the drain terminal heavily doped region 109a and the drain terminal metal field plate, so as to form a Fig.10 In the structure shown, the source metal field plate and the drain metal field plate play a role in increasing the peak electric field on the surface of the drift region, thereby increasing the breakdown voltage.

[0070] In some embodiments, the material of the interlayer dielectric layer 111 in step six is ​​silicon dioxide.

[0071] In some embodiments, the material of the first and second metal layers in step six is ​​aluminum.

[0072] See also Fig.11 , which shows a schematic diagram comparing the surface electric field of the device of the prior art structure and the structure of an embodiment of the present invention. An N-type injection region 102 is injected into the drift region near the bottom of the drain terminal before the N-type epitaxial layer 103 is formed, so its depth is deeper than the injection depth of the P-type doped layer 106. The N-type injection region 102 increases the area of ​​the drain depletion region and can introduce a new electric field peak between the surface U-type electric field peaks, thereby reducing the electric field peak of the surface U-type electric field and improving the breakdown voltage.

[0073] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0074] In summary, the N-type implantation region of the present invention increases the area of ​​the drain end depletion region, and can introduce a new electric field peak between the surface U-type electric field peaks, thereby reducing the electric field peak of the surface U-type electric field and improving the breakdown voltage. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high voltage NLDMOS structure, characterized in that: At least: A P-type substrate, wherein an N-type implantation region is formed in a region of the substrate close to a drain terminal; An N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on the field oxygen region of the epitaxial layer; A P well is formed on the epitaxial layer, and a P-type doping layer is formed on the epitaxial layer at the source end and below the field oxide layer and close to the upper surface of the epitaxial layer; A gate structure and a drain polysilicon field plate, wherein the gate structure comprises a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P well, and the other end thereof extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer near the drain end; N-type heavily doped source end region and drain end region and P-type heavily doped P-well lead-out region; An interlayer dielectric layer located between the source and drain terminals, with a contact element for leading out the polysilicon field plate of the drain terminal formed on the interlayer dielectric layer; The first and second metal layers are located at the source and drain ends, the first metal layer serves as the source end heavily doped region, the lead end of the P-well lead-out region and the source end metal field plate, and the second metal layer serves as the contact and the drain end heavily doped region lead-out end and the drain end metal field plate.

2. The high voltage NLDMOS structure according to claim 1, characterized in that: The gate dielectric layer is a thermal oxide layer.

3. The high voltage NLDMOS structure according to claim 1, characterized in that: The materials of the first and second metal layers are aluminum.

4. The high voltage NLDMOS structure according to claim 1, characterized in that: The N-type implantation region is composed of a plurality of spaced implantation regions.

5. The method for manufacturing a high voltage NLDMOS structure according to any one of claims 1 to 4, characterized in that: At least: Step 1: providing a P-type substrate, and forming an N-type implantation region in a region of the substrate near the drain end by ion implantation; Step 2: forming an N-type epitaxial layer on the substrate, and forming a field oxide layer on the field oxide region of the epitaxial layer; Step 3: forming a P well on the epitaxial layer by ion implantation, and forming a P-type doped layer close to the upper surface of the epitaxial layer on the epitaxial layer at the source end and below the field oxide layer by ion implantation; Step 4: forming a gate structure and a drain polysilicon field plate, wherein the gate structure includes a gate dielectric layer and a gate polysilicon layer, one end of the gate polysilicon layer extends to the P well, and the other end thereof extends to the adjacent field oxide layer, and the drain polysilicon field plate is located on the field oxide layer close to the drain end; Step 5: using ion implantation to form an N-type heavily doped source end region and a heavily doped drain end region and a P-type heavily doped P-well lead-out region; Step six, forming an interlayer dielectric layer between the source and drain terminals, and forming a contact for leading out the polysilicon field plate of the drain terminal on the interlayer dielectric layer; forming a first and a second metal layer at the source and drain terminals, wherein the first metal layer serves as the lead-out terminal of the source terminal heavily doped region, the lead-out terminal of the P-well lead-out region, and the source terminal metal field plate, and the second metal layer serves as the contact and the lead-out terminal of the drain terminal heavily doped region and the drain terminal metal field plate.

6. The method for manufacturing a high voltage NLDMOS structure according to claim 5, characterized in that: The N-type implantation region in step 1 is composed of a plurality of spaced implantation regions.

7. The method for manufacturing a high voltage NLDMOS structure according to claim 5, characterized in that: The method for forming the field oxide layer in step 2 includes: forming a groove on the epitaxial layer by photolithography and etching; and forming the field oxide layer filling the groove.

8. The method for manufacturing a high voltage NLDMOS structure according to claim 5, characterized in that: The method for forming the gate structure and the drain polysilicon field plate in step 4 includes: forming the gate dielectric layer; depositing a polysilicon layer; and patterning the gate dielectric layer and the polysilicon layer by photolithography and etching to form the gate polysilicon layer and the drain polysilicon field plate.

9. The method for manufacturing a high voltage NLDMOS structure according to claim 5, characterized in that: In step 4, the gate dielectric layer is formed by thermal oxidation.

10. The method for manufacturing a high voltage NLDMOS structure according to claim 5, characterized in that: The material of the first and second metal layers in step six is ​​aluminum.

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