Semiconductor structure and preparation method thereof, and control circuit of radio frequency switch

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and a control circuit of a radio frequency switch. The semiconductor structure comprises a substrate; the active regions and the non-active regions are located on the substrate and arranged in the first direction, and the active regions are located between the adjacent non-active regions; the first P-type region, the first insulating region and the first N-type region are located in the active region and are continuously arranged in the first direction; the first polycrystalline layer is positioned above the first insulating region; and a second P-type region and a second N-type region are arranged in the first polycrystalline layer. According to the semiconductor structure, the first insulation region is formed between the first P-type region and the first N-type region, and the first insulation region can limit mutual diffusion between a plurality of sub-regions in the first P-type region and a plurality of sub-regions in the first N-type region, so that charge accumulation on a junction of a diode caused by high-frequency rapid switching of a radio frequency switch is reduced; according to the invention, the diode is not easy to generate unexpected conduction, that is, the performance of the diode is not easy to degrade, so that the reliability is better, and the protection of the transistor is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, and a control circuit of a radio frequency switch. Background Art

[0002] Radio frequency (RF) switches play a key role in wireless communication systems. They are used to switch signals between different circuit paths, such as switching between receive and transmit modes, or distributing signals between different antenna and receiver circuits. The switching of switches is generally controlled by transistors, and in order to make the transistors work as well as possible, diodes are generally connected to the transistors to protect them. With the development of wireless communication technology, the performance requirements for RF switches are getting higher and higher, especially in terms of switching speed. Fast switching capabilities are crucial to improving communication efficiency, reducing power consumption and improving user experience. Researchers have found that in high-frequency fast switching applications, charge will accumulate, causing diode performance degradation, which in turn leads to poor reliability and affects the performance of the entire switch. Summary of the invention

[0003] The purpose of the present application is to provide a semiconductor structure and a preparation method thereof, and a control circuit of a radio frequency switch. The diode performance formed by the semiconductor structure is not easy to degrade, and the protection of the transistor in the control circuit of the radio frequency switch can be ensured.

[0004] To achieve the above objectives, this application provides the following technical solutions:

[0005] The present application provides a semiconductor structure, comprising:

[0006] substrate;

[0007] Active regions and inactive regions located on the substrate and arranged along a first direction, wherein the active regions are located between adjacent inactive regions;

[0008] A first P-type region, a first insulating region, and a first N-type region located in the active region and arranged continuously along the first direction;

[0009] A first polycrystalline layer is located above the first insulating region, wherein the first polycrystalline layer has a second P-type region and a second N-type region.

[0010] In one embodiment, the first P-type region and the second P-type region are located on the same side, and the first N-type region and the second N-type region are located on the same side.

[0011] In one embodiment, a distance between the second P-type region and the second N-type region is greater than or equal to zero.

[0012] In one embodiment, the semiconductor structure further includes:

[0013] a metal layer located above the first polycrystalline layer;

[0014] A first contact hole is provided between the first P-type region and the metal layer, a second contact hole is provided between the first polycrystalline layer and the metal layer, and a third contact hole is provided between the first N-type region and the metal layer. The first N-type region is electrically connected to the first polycrystalline layer via the third contact hole, the metal layer, and the second contact hole, and the first P-type region is electrically connected to the substrate via the first contact hole and the metal layer.

[0015] In one embodiment, a first oxide layer is further provided between the first polycrystalline layer and the first insulating region.

[0016] In one embodiment, the semiconductor structure further includes:

[0017] a third N-type region located in the active region and a second insulating region located between the first P-type region and the third N-type region;

[0018] A second polycrystalline layer is located above the second insulating region, wherein the second polycrystalline layer has a third P-type region and a fourth N-type region.

[0019] The present application also provides a control circuit of a radio frequency switch, comprising:

[0020] A transistor circuit for controlling the switching of the radio frequency switch;

[0021] A protection circuit is coupled to the transistor circuit and is used to protect the transistor circuit. The protection circuit includes a semiconductor device determined by the semiconductor structure as described above.

[0022] In one embodiment, the transistor circuit includes a transistor, the first N-type region is electrically connected to a gate terminal of the transistor, and the first P-type region is electrically connected to a body region of the transistor.

[0023] The present application further provides a method for preparing a semiconductor structure, the method comprising:

[0024] forming active regions and inactive regions arranged along a first direction on a substrate, wherein the active regions are located between adjacent inactive regions;

[0025] forming a first polycrystalline layer on the active area;

[0026] P-type ion implantation and N-type ion implantation are performed on the first polycrystalline layer and the active area to form a first P-type area, a first insulating area, and a first N-type area continuously arranged along the first direction in the active area, and a second P-type area and a second N-type area are formed in the first polycrystalline layer, and the first insulating area is located below the first polycrystalline layer.

[0027] In one embodiment, the preparation method further comprises:

[0028] Before forming the active area and the inactive area, a buried oxide layer is formed on the substrate, and the active area and the inactive area are located on the buried oxide layer;

[0029] Before forming the first polycrystalline layer on the active region, forming a first oxide layer on the active region, the first polycrystalline layer being located on the first oxide layer;

[0030] After completing the ion implantation, a first contact hole, a second contact hole, and a third contact hole are formed on the first P-type region, the first polycrystalline layer, and the first N-type region, respectively, and a metal layer is formed on the first polycrystalline layer, the first N-type region is electrically connected to the first polycrystalline layer via the third contact hole, the metal layer, and the second contact hole, and the first P-type region is electrically connected to the substrate via the first contact hole and the metal layer.

[0031] Compared with the prior art, the technical solution of the present application has the following beneficial effects:

[0032] The semiconductor structure of the present application forms a first insulating region between the first P-type region and the first N-type region. In the diode determined by the semiconductor structure, the junction of the diode actually includes the first insulating region, the junction of the first insulating region and the first P-type region, and the junction of the first insulating region and the first N-type region. The first insulating region can limit the mutual diffusion between the majority carriers in the first P-type region and the majority carriers in the first N-type region, thereby reducing the charge accumulation on the junction of the diode due to the high-frequency rapid switching of the radio frequency switch, making it difficult for the diode to be unexpectedly turned on, that is, the performance of the diode is not easy to degrade, so the reliability is better, ensuring the protection of the transistor.

[0033] The semiconductor structure of the present application is provided with a first polycrystalline layer above the first insulating region. By forming a device structure having a first P-type region, a first insulating region, a first N-type region, and a first polycrystalline layer, the reverse breakdown voltage of the diode can be located between the conduction voltage and the breakdown voltage of the transistor. The second P-type region and the second N-type region are provided on the first polycrystalline layer at the same time, so that the reverse breakdown voltage of the diode can be flexibly adjusted. By providing the second N-type region on the first polycrystalline layer, a strong inversion layer can be formed in the first insulating region below the second N-type region when the transistor is working normally, so as to form a current channel, thereby reducing resistance, reducing heat generation, and reducing the risk of thermal breakdown of the junction of the diode. By providing the second N-type region on the first polycrystalline layer, the second N-type region and the first insulating region are matched, the forward conduction voltage of the diode can be increased, and the voltage from the substrate (also the body region of the transistor) can be isolated to reduce the influence of the substrate voltage on the transistor through the diode, thereby improving the overall linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of a semiconductor structure provided for the first embodiment of the present application;

[0036] Figure 2 A schematic diagram of another semiconductor structure provided for the first embodiment of the present application;

[0037] Figure 3 A schematic diagram of a control circuit of a radio frequency switch provided in the second embodiment of the present application;

[0038] Figure 4-Figure 6 A schematic diagram of a semiconductor structure formed during the preparation process of a semiconductor structure preparation method provided in the present application, Figure 4 Schematic diagram of forming the active region and the first polycrystalline layer (before ion implantation). Figure 5 Schematic diagram of P-type ion implantation and N-type ion implantation (during ion implantation). Figure 6 Schematic diagram of forming contact holes and metal layers (after ion implantation). DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present application. In the following embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0040] See also Figure 1 As shown, the first embodiment of the present application provides a semiconductor structure, the semiconductor structure comprising:

[0041] Substrate 101;

[0042] An active region 102 and an inactive region 103 located on the substrate 101 and arranged along a first direction (Y direction), wherein the active region 102 is located between adjacent inactive regions 103;

[0043] A first P-type region 104, a first insulating region 105, and a first N-type region 106 located in the active region 102 and arranged continuously along a first direction (Y direction);

[0044] The first polycrystalline layer 107 is located above the first insulating region 105 , and the first polycrystalline layer 107 has a second P-type region 108 and a second N-type region 109 .

[0045] The material of the substrate 101 may be silicon, or other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The inactive region 103 may include a shallow trench isolation (STI) structure.

[0046] In this embodiment, the first P-type region 104, the first insulating region 105, and the first N-type region 106 define a PIN diode (semiconductor device), the first P-type region 104 is the anode of the diode, and the first N-type region 106 is the cathode of the diode.

[0047] In this embodiment, the diode of the present invention can be used as a protection circuit to protect the control circuit of the radio frequency switch. The control circuit of the radio frequency switch may include a transistor circuit, which is used to control the switching of the radio frequency switch, and the diode is coupled to the transistor circuit to protect the transistor circuit.

[0048] Specifically, the transistor circuit may include a transistor, the first N-type region 106 is electrically connected to the gate terminal of the transistor, the first P-type region 104 is electrically connected to the body region of the transistor, that is, the cathode of the diode is connected to the gate terminal of the transistor, and the anode of the diode is connected to the body region of the transistor; and the first polycrystalline layer 107 is also electrically connected to the gate terminal of the transistor.

[0049] In this embodiment, a first insulating region 105 is formed between the first P-type region 104 and the first N-type region 106 of the semiconductor structure. In the diode determined by the semiconductor structure, the junction of the diode actually includes the first insulating region 105, the junction of the first insulating region 105 and the first P-type region 104, and the junction of the first insulating region 105 and the first N-type region 106. The first insulating region 105 can limit the mutual diffusion between the majority carriers in the first P-type region 104 and the majority carriers in the first N-type region 106, thereby reducing the charge accumulation on the junction of the diode due to the high-frequency rapid switching of the radio frequency switch, so that the diode is not prone to unexpected conduction, that is, the performance of the diode is not easy to degrade, thereby improving the reliability of the diode and ensuring the protection of the transistor. In the existing scheme, at the junction of the P-type region and the N-type region of the diode, during the high-frequency rapid switching of the radio frequency switch, because the electrons move back and forth in the forward and reverse directions, and the appearance of some high-energy particles, it is easy to generate charge accumulation, thereby making the diode prone to unexpected conduction.

[0050] In this embodiment, the semiconductor structure is provided with a first polycrystalline layer 107 above the first insulating region 105. The voltage applied to the first polycrystalline layer 107 is the same as the voltage applied to the gate terminal (also a polycrystalline layer) of the transistor, so that when the transistor is working normally, when a positive voltage is applied to the gate terminal of the transistor, a positive voltage is also applied to the first polycrystalline layer 107, and the first insulating region 105 below the first polycrystalline layer 107 generates an inversion layer, so that the first P-type region 104 and the first N-type region 106 are easily reversely conductive, that is, the reverse breakdown voltage of the diode can be reduced, so that the reverse breakdown voltage of the diode is not too large. In this way, the present application scheme forms a device structure having a first P-type region 104, a first insulating region 105, a first N-type region 106, and a first polycrystalline layer 107, so that the reverse breakdown voltage of the diode is between the on-voltage and the breakdown voltage of the transistor. Therefore, when the voltage applied to the gate terminal of the transistor is too large (commonly known as overload), the current can be discharged through the diode of the present application scheme (diode reverse breakdown) to protect the transistor.

[0051] Furthermore, by simultaneously providing the second P-type region 108 and the second N-type region 109 on the first polycrystalline layer 107 , the reverse breakdown voltage of the diode can be flexibly adjusted.

[0052] Furthermore, by setting a second N-type region 109 in the first polycrystalline layer 107, when the transistor is working normally, a strong inversion layer can be formed in the first insulating region 105 below the second N-type region 109 to form a current channel, thereby reducing resistance, reducing heat generation, and reducing the risk of thermal breakdown of the diode junction.

[0053] Further, when the transistor is turned off, the voltage applied to the first polycrystalline layer 107 and the voltage applied to the gate terminal of the transistor are both zero voltage or negative voltage. If the forward conduction voltage of the diode is low, when the unnecessary disturbance voltage (ripple voltage) received on the substrate 101 is greater than the forward conduction voltage of the diode, the disturbance voltage will be applied to the gate terminal of the transistor through the conduction of the diode, thereby affecting the current and linearity of the transistor (RF switch). The present application scheme can increase the forward conduction voltage of the diode by setting a second N-type region 109 on the first polycrystalline layer 107 so that the second N-type region 109 and the first insulating region 105 cooperate, and can isolate the voltage from the substrate 101 (also the body region of the transistor) to reduce the influence of the substrate 101 voltage on the transistor through the diode, thereby improving the overall linearity.

[0054] In a specific embodiment, the semiconductor structure may further include: a metal layer 115 located above the first polycrystalline layer 107 .

[0055] In this embodiment, a first contact hole 112 is defined between the first P-type region 104 and the metal layer 115 , a second contact hole 113 is defined between the first polycrystalline layer 107 and the metal layer 115 , and a third contact hole 114 is defined between the first N-type region 106 and the metal layer 115 .

[0056] Specifically, the first N-type region 106 is electrically connected to the first polycrystalline layer 107 via the third contact hole 114 , the metal layer 115 , and the second contact hole 113 , and the first P-type region 104 is electrically connected to the substrate 101 via the first contact hole 112 and the metal layer 115 .

[0057] In this embodiment, each contact hole is not just a hollow "hole", but the "hole" is filled with a conductive material (such as tungsten) to achieve electrical connection, and there is a dielectric layer between the metal layer 115 and the first polycrystalline layer 107 (and the active area 102), and the "hole" is located in the dielectric layer. This application only simplifies the description, which is easy to understand for those skilled in the art.

[0058] In a specific embodiment, the metal layer 115 may include multiple components, that is, the first P-type region 104 and the first N-type region 106 are actually connected to other structures via different parts of the metal layer 115 .

[0059] As mentioned above, the semiconductor structure includes a substrate 101. In the semiconductor manufacturing process, diodes, transistors, etc. are all prepared on the substrate 101, and the first P-type region 104 is electrically connected to the substrate 101. The first P-type region 104 is electrically connected to the substrate 101 via the first contact hole 112 and the metal layer 115. In this embodiment, the semiconductor structure and the transistor in the control circuit of the radio frequency switch are prepared simultaneously on the same substrate 101 to directly realize the electrical connection between the first P-type region 104 and the body region of the transistor.

[0060] In one embodiment, the substrate 101 further has a buried oxide layer 111 , and the active area 102 and the inactive area 103 are both located on the buried oxide layer 111 , so that the semiconductor structure can be better isolated (the inactive area 103 also isolates the active area 102 ).

[0061] In one embodiment, a first oxide layer 110 is further provided between the first polycrystalline layer 107 and the first insulating region 105. The material of the first oxide layer 110 may be silicon oxide.

[0062] In one embodiment, the first P-type region 104 and the second P-type region 108 are located on the same side, and the first N-type region 106 and the second N-type region 109 are located on the same side. That is, in the same plane view, if the first P-type region 104 is located on the left and the first N-type region 106 is located on the right, the second P-type region 108 is also located on the left and the second N-type region 109 is located on the right; or if the first P-type region 104 is located on the right and the first N-type region 106 is located on the left, the second P-type region 108 is also located on the right and the second N-type region 109 is located on the left. Thus, the preparation can be convenient and the process complexity can be reduced.

[0063] In other embodiments, the first P-type region 104 and the second P-type region 108, the first N-type region 106 and the second N-type region 109 may not be located on the same side. Alternatively, the first P-type region 104, the second P-type region 108, the first N-type region 106, and the second N-type region 109 may be located in the same orientation in the same plane view.

[0064] In this embodiment, the distance between the second P-type region 108 and the second N-type region 109 is greater than or equal to 0. That is, according to the different requirements of different actual products, the second P-type region 108 and the second N-type region 109 can be adjacent to each other or at a certain distance in the first polycrystalline layer 107, as long as they do not overlap. Therefore, by adjusting the distribution of the second P-type region 108 and the second N-type region 109 on the first polycrystalline layer 107 to form work functions of different regions, different work function differences can be obtained, and then the threshold voltage of the diode can be adjusted to achieve flexible adjustment of the threshold voltage of the semiconductor device.

[0065] In one embodiment, the semiconductor structure may further include a spacer 116 , and the material of the spacer 116 may include one or more of SiON, SiBCN, SiCN, and SiN doped with C or O.

[0066] See also Figure 2 As shown, in one embodiment, the semiconductor structure further includes:

[0067] A third N-type region 120 located in the active region 102 and a second insulating region (blocked by the second polycrystalline layer 117 described below, not numbered) located between the first P-type region 104 and the third N-type region 120 ;

[0068] The second polycrystalline layer 117 is located above the second insulating region, and has a third P-type region 118 and a fourth N-type region 119 therein.

[0069] Those skilled in the art can understand that two diodes connected in parallel are formed in this way, wherein the first P-type region 104, the first insulating region 105, and the first N-type region 106 together form a first diode in the form of a PIN, and the first polycrystalline layer 107 having the second P-type region 108 and the second N-type region 109 is a part of the first diode; the first P-type region 104, the second insulating region, and the third N-type region 120 together form a second diode in the form of a PIN, and the second polycrystalline layer 117 having the third P-type region 118 and the fourth N-type region 119 is a part of the second diode. In this way, more different usage requirements can be met.

[0070] See also Figure 3 As shown, the second embodiment of the present application provides a control circuit of a radio frequency switch, including:

[0071] A transistor circuit for controlling the switching of the radio frequency switch;

[0072] A protection circuit is coupled to the transistor circuit and is used to protect the transistor circuit. The protection circuit includes a semiconductor device determined by the semiconductor structure as described above.

[0073] In a specific embodiment, the transistor circuit includes a transmitting branch and a receiving branch, and both the transmitting branch and the receiving branch are connected to the antenna A so that the antenna A transmits a transmitting signal TX or receives a receiving signal RX.

[0074] In this embodiment, the transmitting branch and the receiving branch both include a plurality of transistor units connected to each other (the number may be the same or different), and each transistor unit may include a transistor, a gate terminal resistor, a drain-source resistor and a drain-source capacitor.

[0075] Among them, the drain end of the transistor T1 in the first transistor unit in the transmitting branch is connected to the antenna A, the source end of the transistor Tn in the last transistor unit is used to receive the transmitting signal TX, and the transistors T1, T2, ..., Tn in adjacent transistor units are connected in sequence through the source end of the transistor in the previous transistor unit and the drain end of the transistor in the next transistor unit, and the transistors in each transistor unit receive the transmitting control signal VT through their own gate terminal resistors.

[0076] In this embodiment, the source end of the transistor t1 in the first transistor unit of the receiving branch is connected to the antenna A, the drain end of the transistor tn in the last transistor unit is used to send the receiving signal RX to other internal processing circuits, and the transistors t1, t2, ..., tn in adjacent transistor units are connected in sequence to the source end of the transistor in the next transistor unit through the drain end of the transistor in the previous transistor unit, and the transistors in each transistor unit receive the control signal VR through their own gate terminal resistors.

[0077] In this embodiment, each transistor unit may include a diode (i.e., a protection circuit, and the figure only schematically shows the diode in the first transistor unit of the transmitting branch and the first transistor unit of the receiving branch), the cathode of the diode is electrically connected to the gate terminal of the transistor, and the anode of the diode is electrically connected to the body region of the transistor (the symbol B in the figure represents the body region of the transistor). That is, in the semiconductor structure of the present application, the first N-type region 106 is electrically connected to the gate terminal of the transistor, and the first P-type region 104 is electrically connected to the body region of the transistor.

[0078] The control circuit of the radio frequency switch of the present application adopts the diode formed by the aforementioned semiconductor structure as a protection circuit to protect the transistor in the control circuit, so that when the voltage applied to the gate terminal of the transistor is overloaded, the current can be discharged through the diode in the protection circuit to protect the transistor.

[0079] See also Figure 4-Figure 6 As shown, a schematic diagram of a semiconductor structure formed during the preparation process of a semiconductor structure preparation method is provided, wherein Figure 4 Schematic diagram of forming the active region and the first polycrystalline layer (before ion implantation). Figure 5 Schematic diagram of P-type ion implantation and N-type ion implantation (during ion implantation). Figure 6 The schematic diagram of forming each contact hole and metal layer (after ion implantation) is shown below. Figure 1 , Figures 4 to 6 The preparation method is described in detail.

[0080] In this embodiment, the method for preparing the semiconductor structure may include:

[0081] An active region 102 and an inactive region 103 arranged along a first direction (Y direction) are formed on a substrate 101, and the active region 102 is located between adjacent inactive regions 103;

[0082] forming a first polycrystalline layer 107 on the active region 102;

[0083] P-type ion implantation and N-type ion implantation are performed on the first polycrystalline layer 107 and the active area 102 to form a first P-type region 104, a first insulating region 105, and a first N-type region 106 which are continuously arranged along a first direction (Y direction) in the active area 102, and a second P-type region 108 and a second N-type region 109 are formed in the first polycrystalline layer 107. The first insulating region 105 is located below the first polycrystalline layer 107.

[0084] In this embodiment, the P-type ion implantation and the N-type ion implantation into the first polycrystalline layer 107 and the active region 102 may be performed in sequence.

[0085] Specifically, after the active region 102 and the first polycrystalline layer 107 are formed, P-type ion implantation may be performed once into the active region 102 and the first polycrystalline layer 107 , thereby forming a first P-type region 104 in the active region 102 and a second P-type region 108 in the first polycrystalline layer 107 .

[0086] In this embodiment, the semiconductor structure after P-type ion implantation may be implanted with N-type ions once, so as to simultaneously form the first N-type region 106 in the active region 102 and the second N-type region 109 in the first polycrystalline layer 107 .

[0087] In this embodiment, the first polycrystalline layer 107 is located on the active region 102 . When ion implantation is performed, the first insulating region 105 is naturally formed below the first polycrystalline layer 107 due to the blocking of the first polycrystalline layer 107 .

[0088] Those skilled in the art will appreciate that the present application does not have a strict limitation on the order of P-type ion implantation and N-type ion implantation. P-type ion implantation may be performed first and then N-type ion implantation, or N-type ion implantation may be performed first and then P-type ion implantation.

[0089] In one embodiment, when performing P-type ion implantation on the first polycrystalline layer 107 and the active region 102, multiple ion implantations may be performed. For example, a first P-type region 104 may be formed in the active region 102 through a single ion implantation, and then a second P-type region 108 may be formed on the first polycrystalline layer 107 through a second ion implantation.

[0090] In one embodiment, when performing N-type ion implantation on the first polycrystalline layer 107 and the active region 102, multiple ion implantations may be performed. For example, a first N-type region 106 may be formed in the active region 102 by a single ion implantation, and then a second N-type region 109 may be formed on the first polycrystalline layer 107 by a second ion implantation.

[0091] In a specific embodiment, the material of the active region 102 is intrinsic silicon, and the material of the inactive region 103 is silicon oxide. P-type ions may include boron (B) or boron difluoride (BF2), and N-type ions may include phosphorus (P) or arsenic (As). The ion implantation depth and concentration are determined according to the effective active region depth of the wafer, and are consistent with the parameters of the drain and source implantation of the transistor.

[0092] In one embodiment, the distance between the region where the P-type ions are implanted and the region where the N-type ions are implanted is greater than or equal to 0. In this way, the distance between the second P-type region 108 and the second N-type region 109 as described above is greater than or equal to 0. As for the distance between the first P-type region 104 and the first N-type region 106, because the first polycrystalline layer 107 blocks the ion implantation, no matter what the distance between the region where the P-type ions are implanted and the region where the N-type ions are implanted is, the distance between the first P-type region 104 and the first N-type region 106 will not change, that is, the first P-type region 104, the first insulating region 105, and the first N-type region 106 will be stably formed in the active region 102, and a PIN diode will be stably formed.

[0093] In one embodiment, the method for preparing a semiconductor structure may further include: before forming the active area 102 and the inactive area 103 on the substrate 101 , forming a buried oxide layer 111 on the substrate 101 , and the active area 102 and the inactive area 103 are located on the buried oxide layer 111 .

[0094] Furthermore, before forming the first polycrystalline layer 107 on the active region 102 , a first oxide layer 110 is formed on the active region 102 , and the first polycrystalline layer 107 is located on the first oxide layer 110 .

[0095] In this embodiment, after ion implantation is completed, a first contact hole 112, a second contact hole 113, and a third contact hole 114 are formed on the first P-type region 104, the first polycrystalline layer 107, and the first N-type region 106, respectively, and a metal layer 115 is formed on the first polycrystalline layer 107. The first N-type region 106 is electrically connected to the first polycrystalline layer 107 via the third contact hole 114, the metal layer 115, and the second contact hole 113, and the first P-type region 104 is electrically connected to the substrate 101 via the first contact hole 112 and the metal layer 115.

[0096] Among them, the preparation process of the semiconductor structure is compatible with the preparation process of the transistor, and the semiconductor structure and the transistor can be prepared at the same time, that is, the connection relationship between the semiconductor structure and the transistor can be realized at the same time, that is, the first N-type region 106 (the cathode of the diode) is electrically connected to the gate terminal of the transistor, and the first P-type region 104 (the anode of the diode) is electrically connected to the body region of the transistor.

[0097] In this embodiment, Figure 2 The semiconductor structure shown can also be prepared using the above-mentioned preparation method, which will not be described in detail here.

[0098] Compared with the prior art, the technical solution of the present application has the following beneficial effects:

[0099] The semiconductor structure of the present application forms a first insulating region 105 between the first P-type region 104 and the first N-type region 106. In the diode determined by the semiconductor structure, the junction of the diode actually includes the first insulating region 105, the junction of the first insulating region 105 and the first P-type region 104, and the junction of the first insulating region 105 and the first N-type region 106. The first insulating region 105 can limit the mutual diffusion between the majority carriers in the first P-type region 104 and the majority carriers in the first N-type region 106, thereby reducing the charge accumulation on the junction of the diode due to the high-frequency rapid switching of the radio frequency switch, making it difficult for the diode to be unexpectedly turned on, that is, the performance of the diode is not easy to degrade, so the reliability is better, ensuring the protection of the transistor.

[0100] The semiconductor structure of the present application is provided with a first polycrystalline layer 107 above the first insulating region 105. By forming a device structure having a first P-type region 104, a first insulating region 105, a first N-type region 106, and a first polycrystalline layer 107, the reverse breakdown voltage of the diode can be located between the conduction voltage and the breakdown voltage of the transistor. The second P-type region 108 and the second N-type region 109 are provided on the first polycrystalline layer 107 at the same time, so that the reverse breakdown voltage of the diode can be flexibly adjusted. By providing the second N-type region 109 on the first polycrystalline layer 107, a strong inversion layer can be formed in the first insulating region 105 below the second N-type region 109 when the transistor is working normally, so as to form a current channel, thereby reducing resistance, reducing heat generation, and reducing the risk of thermal breakdown of the junction of the diode. By setting a second N-type region 109 on the first polycrystalline layer 107, the second N-type region 109 cooperates with the first insulating region 105, so as to increase the forward conduction voltage of the diode, isolate the voltage from the substrate 101 (which is also the body region of the transistor), and reduce the influence of the substrate 101 voltage on the transistor through the diode, thereby improving the overall linearity.

[0101] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. The content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; Active regions and inactive regions located on the substrate and arranged along a first direction, wherein the active regions are located between adjacent inactive regions; A first P-type region, a first insulating region, and a first N-type region located in the active region and arranged continuously along the first direction; A first polycrystalline layer is located above the first insulating region, wherein the first polycrystalline layer has a second P-type region and a second N-type region.

2. The semiconductor structure according to claim 1, characterized in that: The first P-type region and the second P-type region are located on the same side, and the first N-type region and the second N-type region are located on the same side.

3. The semiconductor structure according to claim 1, characterized in that: A distance between the second P-type region and the second N-type region is greater than or equal to 0.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: a metal layer located above the first polycrystalline layer; A first contact hole is provided between the first P-type region and the metal layer, a second contact hole is provided between the first polycrystalline layer and the metal layer, and a third contact hole is provided between the first N-type region and the metal layer. The first N-type region is electrically connected to the first polycrystalline layer via the third contact hole, the metal layer, and the second contact hole, and the first P-type region is electrically connected to the substrate via the first contact hole and the metal layer.

5. The semiconductor structure according to claim 1, characterized in that: A first oxide layer is further provided between the first polycrystalline layer and the first insulating region.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: a third N-type region located in the active region and a second insulating region located between the first P-type region and the third N-type region; A second polycrystalline layer is located above the second insulating region, wherein the second polycrystalline layer has a third P-type region and a fourth N-type region.

7. A control circuit of a radio frequency switch, characterized in that: include: A transistor circuit for controlling the switching of the radio frequency switch; A protection circuit is coupled to the transistor circuit and is used to protect the transistor circuit. The protection circuit includes a semiconductor device determined by the semiconductor structure according to any one of claims 1 to 6.

8. The control circuit of the radio frequency switch according to claim 7, characterized in that: The transistor circuit includes a transistor, the first N-type region is electrically connected to a gate terminal of the transistor, and the first P-type region is electrically connected to a body region of the transistor.

9. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: forming active regions and inactive regions arranged along a first direction on a substrate, wherein the active regions are located between adjacent inactive regions; forming a first polycrystalline layer on the active area; P-type ion implantation and N-type ion implantation are performed on the first polycrystalline layer and the active area to form a first P-type area, a first insulating area, and a first N-type area continuously arranged along a first direction in the active area, and a second P-type area and a second N-type area are formed in the first polycrystalline layer, and the first insulating area is located below the first polycrystalline layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The preparation method further comprises: Before forming the active area and the inactive area, a buried oxide layer is formed on the substrate, and the active area and the inactive area are located on the buried oxide layer; Before forming the first polycrystalline layer on the active region, forming a first oxide layer on the active region, the first polycrystalline layer being located on the first oxide layer; After completing the ion implantation, a first contact hole, a second contact hole, and a third contact hole are formed on the first P-type region, the first polycrystalline layer, and the first N-type region, respectively, and a metal layer is formed on the first polycrystalline layer, the first N-type region is electrically connected to the first polycrystalline layer via the third contact hole, the metal layer, and the second contact hole, and the first P-type region is electrically connected to the substrate via the first contact hole and the metal layer.

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