High-performance on-chip cross network structure

Abstract

The invention relates to the technical field of high-performance computer networks, and discloses a high-performance on-chip cross network structure, which comprises a router group and a small cross line group, the router group comprises an input-stage router, an output-stage router and an intermediate-stage router; the small cross line group comprises cross lines between at least two stages of routers and is used for connecting the routers at all stages; the middle-level router comprises input ports and output ports, the number of the input ports and the number of the output ports are both smaller than or equal to a first threshold value, and the input ports of the middle-level router are connected with the routers of the corresponding number in the upper-level router; each output port of the middle-level router is respectively connected with a corresponding number of routers in the next-level router; the high-performance on-chip cross network structure has at least one connecting line for any pair of input-stage routers and output-stage routers. According to the invention, the problems of overlarge chip area occupation and performance reduction of a cross network structure can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance computer networks, and in particular to a high-performance on-chip cross network structure. Background Art

[0002] On-chip crossbar network is a technology that realizes communication inside integrated circuit chips. It transmits data packets through a group of network routers, which can meet the needs of multiple processors to access different storage resources at the same time, while improving system bandwidth. On-chip crossbar network eliminates the shortcomings of the bus method and realizes multi-channel communication at the same time, thereby greatly reducing latency. And because of its good scalability, it is used to connect many processor cores and storage resources.

[0003] However, as high-performance system-on-chip (SoC) gradually develops from single-core system to multi-core system (MPSoC) and as on-chip storage resources increase, the scale of the cross-network grows exponentially, which puts higher requirements on the structural planning, performance, area and wiring difficulty of the on-chip cross-network.

[0004] Currently, the basic structure of the on-chip crossbar network is a crossbar switch, which adopts a non-direct connection topology, that is, all terminal nodes are connected through one or more intermediate switching nodes. In the related technology, there are mainly two implementation methods:

[0005] (1) Single router method: All input terminal nodes and output terminal nodes are connected through an n×m router. However, as the scale of multi-core systems increases, the number of processors and storage resources increase, this method is prone to network congestion, resulting in performance degradation.

[0006] (2) Multiple routers sharing: Multiple routers and connecting lines form a large on-chip cross-connect network to improve performance. Although this method can improve network performance, it adds a large number of routers and connecting line resources, resulting in excessive chip area occupation, and faces difficulties such as layout, routing and timing in actual physical implementation. Summary of the invention

[0007] In view of this, the present invention provides a high-performance on-chip cross network structure to solve the problem of excessive chip area occupation and reduced performance of the cross network structure chip.

[0008] In a first aspect, the present invention provides a high-performance on-chip cross network structure, the structure comprising: the network structure comprises a router group and a small cross line group; the router group comprises an input-level router, an output-level router and an intermediate-level router; the small cross line group comprises a cross line between at least two levels of routers, which is used to connect routers at each level; the intermediate-level router comprises an input port and an output port, the number of input ports and the number of output ports are both less than or equal to a first threshold, each input port of the intermediate-level router is respectively connected to a corresponding number of routers in an upper-level router; each output port of the intermediate-level router is respectively connected to a corresponding number of routers in a lower-level router; the high-performance on-chip cross network structure has at least one connection line for any pair of input-level routers and output-level routers.

[0009] Furthermore, the number of levels of routers is related to the number of input ports and the number of output ports of the intermediate level routers.

[0010] Furthermore, the first threshold is 4.

[0011] Furthermore, the first threshold is determined according to the traffic of the cross network structure.

[0012] Furthermore, each small cross-line group corresponds to a small cross-network; in the small cross-network, each lower-level router is connected to each upper-level router in the small cross-network.

[0013] Furthermore, the formula for the number of small cross-line groups i between the x-th level router and the x+1-th level router of the structure is:

[0014] i=n / a_in

[0015] Where n is the number of output ports of the x-th level router, a_in is the number of input ports of the x+1-th level router; x≥0, and x is an integer.

[0016] Furthermore, in each group of small cross networks, the formula for the number of intermediate routers j is:

[0017] j=m / a_out

[0018] Where m is the number of routers that need to be connected to the next level router, and a_out is the number of output ports of the intermediate level router.

[0019] Furthermore, the number of input ports of each output-level router is equal to the number of routers in each group of small cross-networks of the intermediate-level routers in the previous layer.

[0020] Furthermore, the number of output ports of each input-level router is equal to the number of routers in each group of small crossbar networks of the intermediate-level routers in the next layer.

[0021] Furthermore, the level of the router is greater than a second threshold; the second threshold is 3.

[0022] The technical solution provided by this application may have the following beneficial effects:

[0023] The high-performance on-chip cross network structure provided by the present invention includes a router group and a small cross line group; wherein the router group includes an input-level router, an output-level router and an intermediate-level router; the small cross line group includes a cross line between at least two levels of routers, which is used to connect routers at all levels. The input-level router and the output-level router serve as the starting point and the end point of the network, and they are responsible for receiving and sending data packets, respectively. By setting the intermediate-level router, the network is divided into a plurality of smaller cross networks, reducing the load of a single router. The number of input ports and output ports of the intermediate-level router is limited to below the first threshold, further optimizing network performance and reducing resource occupation. The small cross line group forms a multi-level cross network structure by connecting routers at all levels, so that data packets can be transmitted more efficiently in the network. For any pair of input-level routers and output-level routers, there is at least one connection line to ensure that data packets can be transmitted from any input port to any output port. The above scheme can reduce chip area occupation and improve network performance through a reasonable grading strategy and parameter selection method. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a schematic diagram of a multi-stage router network structure according to an embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a high-performance on-chip crossbar network structure according to an embodiment of the present invention;

[0027] Figure 3 is another schematic diagram of an on-chip crossover network structure according to an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the hardware structure of a router device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0030] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0031] The present invention provides a high-performance on-chip cross-network structure, the structure comprising:

[0032] The network structure includes a router group and a small cross-line group.

[0033] On-chip crossbar network is a technology that realizes communication inside an integrated circuit chip, and transmits data packets through a group of network routers. Routers are devices responsible for receiving, forwarding and sending data packets in the network. The network structure of the present invention consists of two core parts, namely the router group and the small crossbar group.

[0034] The router group includes an input-level router, an output-level router, and an intermediate-level router.

[0035] The input-level router, output-level router, and intermediate-level router included in the router group are responsible for receiving, forwarding, and sending data, and are key components for achieving network communication. The input-level router is located at the entry end of the network structure and is responsible for receiving data packets from the outside or other modules inside the chip. It is the starting point of the data and ensures that the data can enter the network smoothly. The output-level router is located at the exit end of the network structure and is responsible for sending data packets to the target module or external device. It is the end point of the data and ensures that the data can reach the destination accurately. The intermediate-level router is located between the input and output levels and plays the role of data forwarding and routing.

[0036] The small cross-line group includes cross-lines between at least two levels of routers, and is used to connect the routers at each level.

[0037] The small crossbar group consists of a series of crossbars that connect routers at different levels. A crossbar is a connection line used to connect different routers. In the on-chip crossbar network, the crossbar is a key component for implementing data routing and transmission.

[0038] The intermediate-level router includes an input port and an output port, the number of the input ports and the number of the output ports are both less than or equal to a first threshold, each input port of the intermediate-level router is respectively connected to a corresponding number of routers in an upper-level router; each output port of the intermediate-level router is respectively connected to a corresponding number of routers in a lower-level router; and the high-performance on-chip cross-network structure has at least one connection line for any pair of input-level routers and output-level routers.

[0039] Each intermediate router has multiple input ports and output ports for receiving and sending data. Among them, the input port is the interface on the router for receiving data, and the output port is the interface on the router for sending data. The first threshold is a settable parameter used to limit the number of ports of the intermediate router. By setting this threshold, the scale of the intermediate router can be controlled. The input port of each intermediate router is connected to the corresponding number of routers in the upper-level router to ensure that the data transmitted from the upper-level router can smoothly enter the intermediate router for processing. Similarly, the output port of each intermediate router is connected to the corresponding number of routers in the lower-level router to ensure that the processed data can be smoothly transmitted to the lower-level router. In the network structure of the present invention, no matter which pair of input-level routers and output-level routers, there is at least one connection line to ensure that data can be freely transmitted between them.

[0040] In summary, the high-performance on-chip cross-network structure of the present invention realizes efficient data transmission and flexible network configuration by designing router groups and small cross-line groups, as well as port connection methods and threshold limits, which can reduce chip area occupancy and improve network performance.

[0041] Furthermore, the number of levels of routers is related to the number of input ports and the number of output ports of the intermediate level routers.

[0042] In the on-chip crossbar network structure, the router is divided into multiple levels, including the input level, the output level, and multiple intermediate levels. The number of levels of the router refers to the number of these levels. When designing the network structure, it is necessary to comprehensively consider the number of input ports and output ports of the intermediate routers, as well as the number of router levels determined by this. Specifically, the selection of the number of input ports and the number of output ports will directly affect the processing capacity of the router, thereby affecting the performance of the entire network structure.

[0043] The high-performance on-chip cross network structure of the present invention can reduce the chip area occupied by the entire network structure by controlling the number of levels of routers and the number of ports of intermediate-level routers while ensuring performance.

[0044] Furthermore, the first threshold is 4.

[0045] In the high-performance on-chip cross-network structure of the present invention, the number of input ports and the number of output ports of the intermediate router are limited to 4 or less. By limiting the number of ports of the intermediate router, the network performance can be improved.

[0046] Furthermore, the first threshold is determined according to the traffic of the cross network structure.

[0047] In network communication, traffic refers to the measure of data passing through the network per unit time. For the on-chip cross-network structure in the present invention, traffic refers to the amount of data transmitted between processors or between processors and storage resources. The size of the traffic directly affects the load and performance requirements of the network. The setting of the first threshold is determined based on the actual traffic situation of the cross-network structure. Based on the traffic characteristics of the network, including the size, distribution, peak value, etc. of the traffic, the appropriate number of intermediate router ports (i.e., the first threshold) is determined. Through the setting based on traffic, it is ensured that the network can maintain efficient and stable operation when facing different traffic loads.

[0048] Furthermore, each small cross-line group corresponds to a small cross-network; in the small cross-network, each lower-level router is connected to each upper-level router in the small cross-network.

[0049] In the on-chip crossbar network, each small crossbar group constitutes a small crossbar network. A small crossbar network refers to a network substructure composed of a group of small crossbars. Each small crossbar network is a relatively independent communication unit that can handle a part of the network traffic and realize data transmission of the entire network through interconnection with other small crossbar networks. Inside the small crossbar network, each level of router is connected to the routers of the previous and next levels, forming a multi-level router network. This connection method ensures that each router in the network can receive data from its previous level router and forward it to the next level router, thereby realizing the level-by-level transmission of data.

[0050] Among them, a multi-level router network such as Figure 1 As shown in FIG. 1 , by adding connection lines between n input-level routers and m output-level routers, a large on-chip crossover network is formed. Each input-level router has 1 input port and m output ports, and each output-level router has n input ports and 1 output port. The multi-level router network can improve the performance of the on-chip crossover network.

[0051] Furthermore, the formula for the number of small cross-line groups i between the x-th level router and the x+1-th level router of the structure is:

[0052] i=n / a_in

[0053] Where n is the number of output ports of the x-th level router, a_in is the number of input ports of the x+1-th level router; x≥0, and x is an integer.

[0054] This formula is used to calculate the number of small cross-line groups. Through this formula, the number of small cross-line groups required can be determined based on the number of ports on the router. Where x ≥ 0, and x is an integer. The value range of the variable x is restricted. x represents the level of the router in the network structure. Since the network structure is usually numbered from level 0, the value range of x starts from 0 and must be an integer.

[0055] Furthermore, in each group of small cross networks, the formula for the number of intermediate routers j is:

[0056] j=m / a_out

[0057] Where m is the number of routers that need to be connected to the next level router, and a_out is the number of output ports of the intermediate level router.

[0058] This formula is used to calculate the number of intermediate routers in each group of small cross networks. Through this formula, the number of intermediate routers required can be determined based on the number of routers that actually need to be connected and the number of ports of the intermediate routers.

[0059] Furthermore, the number of input ports of each output-level router is equal to the number of routers in each group of small cross-networks of the intermediate-level routers in the previous layer.

[0060] The number of input ports of an output-level router determines how many data it can simultaneously receive from the intermediate routers in the previous layer. The number of input ports of an output-level router is equal to the number of routers contained in each group of small cross-networks in the intermediate router in the previous layer, ensuring that the number of input ports of each output-level router matches the number of routers in the intermediate router in the previous layer, so that the data flowing out of the intermediate router can seamlessly enter the output-level router, thereby achieving efficient data flow in the entire network.

[0061] Furthermore, the number of output ports of each input-level router is equal to the number of routers in each group of small crossbar networks of the intermediate-level routers in the next layer.

[0062] The number of output ports of an input-level router determines how many intermediate routers in the next layer it can send data to at the same time. The number of output ports of an input-level router is equal to the number of routers contained in each group of small cross-networks in the intermediate routers in the next layer, ensuring that the number of output ports of each input-level router matches the number of routers in the intermediate routers in the next layer, so that the data flowing out of the input-level router can seamlessly enter the intermediate router, thereby achieving efficient data flow in the entire network.

[0063] Furthermore, the level of the router is greater than a second threshold; the second threshold is 3.

[0064] In the present invention, the number of levels of routers in the on-chip crossbar network structure needs to be greater than a specific value, which is defined as the second threshold, and the second threshold is explicitly specified as 3. That is, in order to ensure the performance and efficiency of the network, the number of levels of routers in the on-chip crossbar network cannot be less than three.

[0065] Specifically, in an embodiment of the present invention, the on-chip crossbar network structure is as follows: Figure 2 The present invention is a multi-level cross network structure, and the network level k is defined as the level of routers that need to be connected through intermediate cross lines.

[0066] The number of input-level routers is n, and the number of output-level routers is m. The selection of the number of input / output ports a_in / a_out of the intermediate-level router is related to the size of the network traffic. Under full network load, the smaller a_in / a_out is, the better the network performance is, but the number of network levels will become larger. Therefore, it is necessary to determine the value of a based on the performance and area requirements of the actual network. a_in and a_out can be different. Under full network load, according to experimental results, it is recommended that a≤4 will have better performance.

[0067] After the a_in of the intermediate router is determined, the number of groups i of small cross lines between the 0th and 1st levels of the network is also determined, i=n / a_in (i is rounded up). As shown in the figure, each group of small cross lines is numbered b0, b1, ..., bi-1.

[0068] In each group of small cross networks, the number of intermediate routers j=m / a_out, numbered c0, c1, ..., cj-1.

[0069] The network level is k, and the initial network level is 2. If each level of small cross-network is still large after adding one intermediate router, then the iteration can be continued, and another intermediate router can be added between the small cross-networks until the area of ​​the small cross-network meets the layout and routing requirements. Each level is numbered L0, L1, ..., Lk-1.

[0070] After the above parameters are determined, the number of ports of the 0th and kth level routers is also determined. The 0th level is the input level, and the number of output ports of each input level router is equal to the number of routers in each small cross network of the intermediate level routers in the next layer. The kth level is the output level, and the number of input ports of each output level router is equal to the number of routers in each small cross network of the intermediate level routers in the previous layer.

[0071] like Figure 3, taking the on-chip crossbar network required for 8 input terminal nodes and 8 output terminal nodes as an example:

[0072] First, select a_in and a_out. In order to minimize the network area occupied and ensure network performance, a_in and a_out are selected as 4.

[0073] The number of groups of small cross lines between level 0 and level 1 in the network is b=8 / 4=2, which are b0 and b1 respectively.

[0074] In each group of small cross-networks, the number of intermediate switching nodes is c=8 / 4=2.

[0075] According to the above parameter selection, after adding an intermediate router, the size of the small cross network is 4×2 cross lines. The network scale is not large and does not need to be further graded. Therefore, the level of this network is 3 levels L0~L2.

[0076] An embodiment of the present invention further provides a routing device for use in the above-mentioned high-performance on-chip cross-network structure.

[0077] See also Figure 4 , Figure 4 is a schematic diagram of the structure of a routing device provided by an optional embodiment of the present invention, such as Figure 4 As shown, the routing device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed in the routing device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple routing devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 4 A processor 10 is taken as an example.

[0078] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0079] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0080] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data created according to the use of the routing device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the routing device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0081] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0082] The routing device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.

[0083] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the routing device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0084] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be downloaded through a network and originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a router, a processor or hardware, the method shown in the above embodiment is implemented.

[0085] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a router, can call or provide the method and / or technical solution according to the present invention through the operation of the router. Those skilled in the art should understand that the existence of the computer program instruction in the computer-readable medium includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes but is not limited to: the router directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0086] The above is only a preferred specific embodiment of the present invention, which is an implementation method based on the overall concept of the present invention, and the protection scope of the present invention is not limited to this. Those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations all fall within the scope defined by the attached claims.

Claims

1. A high-performance on-chip crossbar network structure, characterized in that: The structure comprises: The network structure includes a router group and a small cross-line group; The router group includes an input-level router, an output-level router, and an intermediate-level router; The small cross-line group includes cross-lines between at least two levels of routers, and is used to connect the routers at each level; The intermediate-level router includes an input port and an output port, the number of the input ports and the number of the output ports are both less than or equal to a first threshold, each input port of the intermediate-level router is respectively connected to a corresponding number of routers in an upper-level router; each output port of the intermediate-level router is respectively connected to a corresponding number of routers in a lower-level router; the high-performance on-chip cross-network structure has at least one connection line for any pair of input-level routers and output-level routers.

2. The structure according to claim 1, characterized in that: The structure comprises: The number of levels of the router is related to the number of input ports and the number of output ports of the intermediate level router.

3. The structure according to claim 1, characterized in that: The first threshold is 4.

4. The structure according to claim 1, characterized in that The first threshold is determined according to the traffic of the cross network structure.

5. The structure according to any one of claims 1 to 4, characterized in that: Each small cross line group corresponds to a small cross network; in the small cross network, each lower-level router is connected to each upper-level router in the small cross network.

6. The structure according to claim 5, characterized in that The formula for the number i of small cross-line groups between the x-th level router and the x+1-th level router of the structure is: i=n / a_in Wherein, n is the number of output ports of the x-th level router, a_in is the number of input ports of the x+1-th level router; x≥0, and x is an integer.

7. The structure according to claim 6, characterized in that In each group of small cross networks, the formula for the number j of the intermediate routers is: j=m / a_out Wherein, m is the number of routers that need to be connected to the next-level router, and a_out is the number of output ports of the intermediate-level router.

8. The structure according to claim 7, characterized in that The number of input ports of each of the output-level routers is equal to the number of routers in each group of small cross-networks of the intermediate-level routers in the previous layer.

9. The structure according to claim 7, characterized in that The number of output ports of each of the input-level routers is equal to the number of routers in each group of small cross-networks of the intermediate-level routers in the next layer.

10. The structure according to claim 2, characterized in that The level of the router is greater than a second threshold; the second threshold is 3.

Images