Semiconductor test management system

Abstract

The invention discloses a semiconductor test management system, relates to the technical field of semiconductor test, and solves the technical problems that performance detection and evaluation in different stages of wafer production are lacked, and it is difficult to detect whether a wafer has performance abnormity in the production stage in time. According to the stage performance evaluation coefficient of the semiconductor wafer of each node, a node early warning module performs stage early warning on the semiconductor wafer with stage performance abnormity, analyzes the comprehensive performance coefficient of the semiconductor wafer, and performs early warning on the semiconductor wafer which does not meet the standard; by monitoring and analyzing stage performance coefficients in real time, semiconductor wafers which do not meet the standard can be quickly identified, measures are taken in advance, and greater loss generated in the subsequent process is avoided. By detecting whether the performance of the wafer is abnormal or not in the production stage, resources can be reasonably allocated, and defective wafers can be centrally processed or re-evaluated instead of wasting time and materials on possibly failed products.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor testing, in particular to a semiconductor testing management system. Background Art

[0002] Semiconductor Test Management System (STMS) is an integrated software platform designed to support testing, data collection, analysis and quality control in the semiconductor manufacturing process. The system can effectively manage various test processes from wafer level to package level, including but not limited to electrical testing, optical inspection, defect analysis, etc. STMS is usually combined with production equipment, automation systems and data analysis tools to achieve real-time monitoring, fault warning and performance optimization. With the development of big data and artificial intelligence, the semiconductor industry is gradually transforming to data-driven decision-making. Companies need to effectively collect, store and analyze large amounts of data to optimize production processes and improve yields.

[0003] Most existing semiconductor test management systems usually perform various tests on completed semiconductor wafers, but lack performance testing and evaluation at different stages of wafer production, making it difficult to detect whether there are performance anomalies in the wafers in a timely manner during the production stage. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a semiconductor test management system for solving the technical problem of lack of performance detection and evaluation at different stages of wafer production, and difficulty in timely detecting whether there are performance abnormalities in the wafer during the production stage.

[0005] To solve the above problems, a first aspect of the present invention provides a semiconductor test management system, comprising:

[0006] Information management module: used to obtain and store the basic information of the generated semiconductor wafers, including: material type, size, doping type, doping concentration, crystal structure and performance standards, and set detection nodes for the production process of semiconductor wafers, including: lithography nodes, etching nodes, ion implantation nodes and thin film deposition nodes;

[0007] Test data acquisition module: for photolithography nodes and etching nodes, the three-dimensional point cloud data after photolithography and etching are detected respectively; for ion implantation nodes, the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are collected; for thin film deposition nodes, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected through the test machine, and basic information labels are set for the data collected at each node;

[0008] Intelligent scheduling module: used to detect the use status of the test machine at the current node, and according to the current test machine status and basic information of the semiconductor wafer, to match the semiconductor wafer of the thin film deposition node with the test machine to test the semiconductor wafer after thin film deposition;

[0009] Data analysis module: analyzing the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data collection module;

[0010] Node warning module: It is used to issue a stage warning for semiconductor wafers with abnormal stage performance according to the stage performance evaluation coefficient of the semiconductor wafers at each node, and to analyze the comprehensive performance coefficient of the semiconductor wafers to issue a warning for semiconductor wafers that do not meet the standards.

[0011] As a further solution of the present invention: the test data acquisition module collects electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after film deposition through the test machine for the thin film deposition node, including the following steps:

[0012] For the thin film deposition node, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-set detection temperature type semiconductor wafer according to the material type data of the semiconductor wafer in the basic information tag of the semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes: single crystal silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer;

[0013] For semiconductor wafers with fixed detection temperature, a high detection temperature, a medium detection temperature and a low detection temperature are set for the semiconductor wafers with fixed detection temperature;

[0014] For semiconductor wafers with self-set detection temperature, manually input the test temperature of the semiconductor wafers with self-set detection temperature;

[0015] Under different detection temperatures, the test machine collects electrical test data, surface high-definition images and infrared detection images of the packaged semiconductor wafers. The electrical test data includes threshold voltage, leakage current, saturation current and conductivity.

[0016] As a further solution of the present invention: the test data collection module sets basic information labels for the data collected by each node, including the following steps:

[0017] Obtain basic information data of semiconductor wafers, and extract data on material type, size, doping type, doping concentration and performance standards from the basic information data;

[0018] Generate a unique code for the semiconductor wafer, and use the key fields of the semiconductor wafer's code, material type and size as basic information tags based on the extracted material type, size and coding information of the semiconductor wafer;

[0019] According to the extracted data of doping type, doping concentration and performance standard of the semiconductor wafer, a parameter list of the semiconductor wafer is constructed, and the parameter list of the semiconductor wafer is stored in each node;

[0020] A corresponding key-value pair is set for each type of data in the parameter list of the semiconductor wafer, and key-value pairs corresponding to the doping type, doping concentration, crystal structure, and performance standard data types are added to the basic information tag.

[0021] As a further solution of the present invention: the intelligent scheduling module detects the use status of the test machine at the current node, and according to the current test machine status and the basic information of the semiconductor wafer, performs a test on the semiconductor wafer after thin film deposition by matching the semiconductor wafer at the thin film deposition node, including the following steps:

[0022] Count the test machines of thin film deposition nodes, including: sorting machine, probe station and scanning test station, and number the test machines of thin film deposition nodes, among which the scanning test station includes: SEM scanning electron microscope and optical interferometer;

[0023] Detect the usage status of the current node test machine. For the probe station, collect the usage status of the probe station including: the number of wafers to be tested by the probe station and the size of the last wafer to be tested by the probe station. For the scanning test station, collect the number of wafers to be tested by the scanning test station;

[0024] According to the current test machine status and the size information in the basic information of the semiconductor wafer, select 2 to 3 probe stations with the least number of wafers to be tested in the probe station;

[0025] Detect the size of the last wafer to be tested of the selected probe station, select the probe station whose area of ​​the last wafer to be tested is closest to the area of ​​the semiconductor wafer after thin film deposition, if there are multiple probe stations that meet the requirements, randomly select a probe station that meets the requirements as the detection machine for electrical testing, and send the number of the detection machine to the sorting machine, which transfers the semiconductor wafer after thin film deposition to the corresponding probe station;

[0026] After the electrical test on the probe station, the scanning test station with the least number of wafers to be tested is selected as the detection machine for three-dimensional point cloud data detection and deposited film thickness data detection, and the number of the detection machine is sent to the sorting machine, which transfers the semiconductor wafers after the electrical test to the corresponding scanning test station.

[0027] As a further solution of the present invention: the data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer of each node according to the detection data of each node collected by the test data collection module, including the following steps:

[0028] For the lithography node and the etching node, obtain the 3D point cloud data after lithography and etching;

[0029] Through the three-dimensional point cloud data after the wafer lithography process is completed, it is detected whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern. If they are consistent, the lithography node detection is qualified. If not, the lithography node detection is unqualified, and the corresponding coded wafer generates a quality warning signal;

[0030] Through the three-dimensional point cloud data after the wafer etching process is completed, detect whether the depth and shape of the etching position of the wafer at the etching node meet the preset etching depth and shape. If they are consistent, the etching node detection is qualified; if they are inconsistent, the etching node detection is unqualified, and a quality warning signal is generated for the corresponding coded wafer;

[0031] For the ion implantation node, the ion implantation performance evaluation coefficient of the semiconductor wafer is analyzed based on the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation;

[0032] For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected by the test machine to detect whether the corresponding semiconductor wafer has passed the inspection at the node. At the node where the inspection fails, the corresponding coded wafer generates a quality warning signal; if the corresponding semiconductor wafer has passed the inspection at the node, the performance evaluation coefficient of the semiconductor wafer in the thin film deposition stage is analyzed.

[0033] As a further solution of the present invention: analyzing the ion implantation stage performance evaluation coefficient of the semiconductor wafer according to the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, including the following steps:

[0034] Obtaining an X-ray fluorescence spectrum and a Fourier transform infrared spectrum of the semiconductor wafer after ion implantation;

[0035] Extract the doping type and doping concentration data of the wafer through the basic information label of the wafer;

[0036] Obtaining Fourier transform infrared spectra of n-type doped wafers and p-type doped wafers in historical data, and marking the positions, widths, and frequency ranges of the absorption peaks of the Fourier transform infrared spectra of the n-type doped wafers and the p-type doped wafers;

[0037] The deep learning model is trained through the annotated Fourier transform infrared spectra to identify the doping type of the wafer;

[0038] By inputting the Fourier transform infrared spectrum image collected in real time at the ion implantation node into the trained deep learning model, the wafer is identified as an n-type doped wafer or a p-type doped wafer;

[0039] According to the X-ray fluorescence spectrum of the semiconductor wafer, characteristic peaks in the X-ray fluorescence spectrum are extracted, and the area sum of the characteristic peaks in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity;

[0040] Selecting several groups of semiconductor wafers of the same doping type to be tested, obtaining actual doping concentration data of the several groups of wafers, and detecting characteristic peak intensities of the several groups of wafers;

[0041] The performance evaluation coefficient of the ion implantation stage of the semiconductor wafer is calculated by the following formula:

[0042]

[0043] Where: α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, C std To extract the standard doping concentration data of the wafer, C sample is the doping concentration of the semiconductor wafer during the ion implantation stage, C i is the average value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the average value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of crystal elements;

[0044] As a further solution of the present invention: for a thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition collected by the test machine are obtained, and the corresponding semiconductor wafer is detected to be qualified at the node. At the node where the detection is unqualified, a quality warning signal is generated for the corresponding coded wafer, including the following steps:

[0045] For the thin film deposition node, the electrical test data of the semiconductor wafer after thin film deposition collected by the test machine is obtained to detect whether the electrical test data exceeds the preset threshold range. If so, the thin film deposition node detection fails, and a quality warning signal is generated for the corresponding coded wafer. Otherwise, the three-dimensional point cloud data and the deposited film thickness data are detected;

[0046] Detect whether the difference between the highest position and the lowest thickness of the deposited film position of the three-dimensional point cloud data is greater than the preset maximum threshold. If so, the film deposition node detection is unqualified, and the corresponding coded wafer generates a quality warning signal. Otherwise, the deposited film thickness data is detected;

[0047] Detect whether the deposited film thickness data belongs to the preset threshold range. If not, the film deposition node detection fails, and the corresponding coded wafer generates a quality warning signal. Otherwise, analyze the performance evaluation coefficient of the semiconductor wafer at the film deposition stage.

[0048] As a further solution of the present invention: analyzing the performance evaluation coefficient of the thin film deposition stage of the semiconductor wafer includes the following steps:

[0049] Through the three-dimensional point cloud data of the wafer, the distance from each point on the non-etching position surface to the preset detection surface is detected;

[0050] Extract the standard values ​​of threshold voltage, leakage current, saturation current and conductivity from the performance standard data of the basic information of the semiconductor wafer;

[0051] Obtain electrical test data of semiconductor wafers, and calculate the average values ​​of threshold voltage, leakage current, saturation current and conductivity at different test temperatures;

[0052] According to the electrical test data of the semiconductor wafer and the distance from each point on the non-etched surface to the preset detection surface, the performance evaluation coefficient of the thin film deposition stage is calculated by the following formula:

[0053]

[0054] Among them, β is the performance evaluation coefficient of the thin film deposition stage, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, and σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, and σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the non-etching position surface to the preset detection surface, and σ0 is the mean value of the distance from each point on the non-etching position surface to the preset detection surface.

[0055] As a further solution of the present invention: the node early warning module performs a phased early warning on semiconductor wafers with abnormal phase performance according to the phase performance evaluation coefficient of the semiconductor wafers of each node, including the following steps:

[0056] According to the quality warning signal of the wafer with corresponding code generated by the data analysis module, a phased warning is issued for semiconductor wafers with abnormal performance at the corresponding node stage;

[0057] According to the stage performance evaluation results of the semiconductor wafers at each node, if the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds a preset threshold, a stage warning will be issued for the semiconductor wafer with abnormal stage performance at the corresponding node.

[0058] As a further solution of the present invention: the node early warning module analyzes the comprehensive performance coefficient of the semiconductor wafer and issues an early warning for semiconductor wafers that do not meet the standards, including the following steps:

[0059] According to the stage performance evaluation coefficient of the semiconductor wafer at each node, for the wafers that have not shown a stage warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed by the following formula:

[0060] K=e - (α+β)

[0061] Wherein, K is the comprehensive performance coefficient of the semiconductor wafer, α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, and β is the performance evaluation coefficient of the thin film deposition stage;

[0062] If the comprehensive performance coefficient of the semiconductor wafer is less than a preset threshold, the corresponding semiconductor wafer has quality risks, and an early warning is issued for the semiconductor wafer with quality risks.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] The present invention collects electrical test data, three-dimensional point cloud data and deposited film thickness data of semiconductor wafers after film deposition through a test machine, and sets basic information labels for the data collected at each node; by monitoring the data of each node, it is convenient to timely understand whether the process parameters in the wafer production process are within the set range, so as to adjust the process conditions in time to ensure product quality. The data of each node is marked and archived, which is convenient for providing complete production inspection records, tracing the source of problems, and facilitating quality management and improvement.

[0065] The present invention uses a node early warning module to conduct a phased early warning on semiconductor wafers with abnormal stage performance according to the stage performance evaluation coefficient of the semiconductor wafer of each node, and analyzes the comprehensive performance coefficient of the semiconductor wafer to warn semiconductor wafers that do not meet the standards; through real-time monitoring and analysis of the stage performance coefficient, it is easy to quickly identify semiconductor wafers that do not meet the standards, take measures in advance, and avoid greater losses in subsequent processes. It is convenient to identify potential defects at an early stage, reduce the outflow of unqualified products, improve the overall yield, and reduce production costs. By detecting whether the wafer has performance abnormalities during the production stage, resources can be reasonably allocated, and problematic wafers can be centrally processed or re-evaluated, rather than wasting time and materials on products that may fail. The quality control of the production process is enhanced through a phased early warning mechanism, so that each link can maintain a high standard, which is conducive to the consistency and reliability of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0067] Figure 1 It is a schematic diagram of the system framework of the present invention;

[0068] Figure 2 The present invention is a flow chart of a method for analyzing the stage performance evaluation coefficients of semiconductor wafers at various nodes. DETAILED DESCRIPTION

[0069] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] See also Figure 1-Figure 2 According to a first aspect of the present invention, a semiconductor test management system is provided, comprising:

[0071] Information management module: used to obtain and store the basic information of the generated semiconductor wafers, including: material type, size, doping type, doping concentration, crystal structure and performance standards, and set detection nodes for the production process of semiconductor wafers, including: lithography nodes, etching nodes, ion implantation nodes and thin film deposition nodes;

[0072] Test data acquisition module: for photolithography nodes and etching nodes, the three-dimensional point cloud data after photolithography and etching are detected respectively; for ion implantation nodes, the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are collected; for thin film deposition nodes, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected through the test machine, and basic information labels are set for the data collected at each node;

[0073] Intelligent scheduling module: used to detect the use status of the test machine at the current node, and according to the current test machine status and basic information of the semiconductor wafer, to match the semiconductor wafer of the thin film deposition node with the test machine to test the semiconductor wafer after thin film deposition;

[0074] Data analysis module: analyzing the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data collection module;

[0075] Node warning module: It is used to issue a stage warning for semiconductor wafers with abnormal stage performance according to the stage performance evaluation coefficient of the semiconductor wafers at each node, and to analyze the comprehensive performance coefficient of the semiconductor wafers to issue a warning for semiconductor wafers that do not meet the standards.

[0076] Specifically, in this embodiment, the test data acquisition module detects the three-dimensional point cloud data after lithography and etching for the lithography node and the etching node, respectively. For the ion implantation node, the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are collected. For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected through the test machine, and basic information labels are set for the data collected at each node; by monitoring the data of each node, it is convenient to timely understand whether the process parameters in the wafer production process are within the set range, so as to adjust the process conditions in time to ensure product quality. The data of each node is marked and archived, which is convenient for providing complete production inspection records, tracing the source of problems, and facilitating quality management and improvement.

[0077] 3D point cloud data can help identify surface defects or unevenness, and by discovering problems early, it can reduce scrap rates and production costs. At the same time, collecting different types of data, such as spectrograms, 3D point clouds, electrical tests, etc., provides a basis for multi-dimensional analysis and helps to comprehensively evaluate process effects and material properties.

[0078] The intelligent scheduling module detects the usage status of the test machine at the current node, and according to the current test machine status and basic information of the semiconductor wafer, a test machine matching the semiconductor wafer at the thin film deposition node is used to test the semiconductor wafer after thin film deposition;

[0079] By real-time monitoring of the use status of the test machine, it is convenient to effectively allocate and utilize the equipment, avoid equipment idleness or overload, and improve overall production efficiency; through intelligent scheduling, waiting time is reduced, thereby speeding up the overall process of semiconductor wafers from deposition to testing and shortening the production cycle. The intelligent scheduling system can automatically adjust the plan based on real-time data, making the production process more flexible to respond to emergencies or order changes. Automated scheduling reduces the need for manual intervention, thereby reducing labor costs and alleviating the workload of operators.

[0080] The node warning module can provide a stage warning for semiconductor wafers with abnormal stage performance according to the stage performance evaluation coefficient of the semiconductor wafers at each node, and analyze the comprehensive performance coefficient of the semiconductor wafer to warn semiconductor wafers that do not meet the standards; through real-time monitoring and analysis of the stage performance coefficient, it is easy to quickly identify semiconductor wafers that do not meet the standards, take measures in advance, and avoid greater losses in subsequent processes. Early warning facilitates the identification of potential defects at an early stage, reduces the outflow of unqualified products, improves the overall yield, and reduces production costs. By detecting whether there are performance anomalies in the wafers during the production stage, resources can be reasonably allocated, and problematic wafers can be centrally processed or re-evaluated, rather than wasting time and materials on products that may fail. The staged warning mechanism enhances quality control in the production process, allowing each link to maintain high standards, which helps the consistency and reliability of the final product.

[0081] In one embodiment of the present invention, the test data acquisition module collects electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after film deposition through a test machine for a thin film deposition node, including the following steps:

[0082] For the thin film deposition node, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-set detection temperature type semiconductor wafer according to the material type data of the semiconductor wafer in the basic information tag of the semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes: single crystal silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer;

[0083] For semiconductor wafers with fixed detection temperature, a high detection temperature, a medium detection temperature and a low detection temperature are set for the semiconductor wafers with fixed detection temperature;

[0084] For semiconductor wafers with self-set detection temperature, manually input the test temperature of the semiconductor wafers with self-set detection temperature;

[0085] Under different detection temperatures, the test machine collects electrical test data, surface high-definition images and infrared detection images of the packaged semiconductor wafers. The electrical test data includes threshold voltage, leakage current, saturation current and conductivity.

[0086] Specifically, in this implementation, for common single crystal silicon semiconductor wafers, gallium arsenide semiconductor wafers, gallium nitride semiconductor wafers, and silicon carbide semiconductor wafers, a fixed detection temperature is set as shown below;

[0087] For single crystal silicon semiconductor wafers, the high temperature detection temperature is set to 80°C, the medium temperature detection temperature is set to 20°C, and the low temperature detection temperature is set to -10°C;

[0088] For gallium arsenide semiconductor wafers, the high temperature detection temperature is set to 40°C, the medium temperature detection temperature is set to 20°C, and the low temperature detection temperature is set to 0°C;

[0089] For gallium nitride semiconductor wafers, the high temperature detection temperature is set to 100°C, the medium temperature detection temperature is set to 20°C, and the low temperature detection temperature is set to 0°C;

[0090] For silicon carbide semiconductor wafers, the high temperature detection temperature is set to 150°C, the medium temperature detection temperature is set to 40°C, and the low temperature detection temperature is set to -20°C.

[0091] Wafers that need to set the detection temperature themselves are classified as self-setting detection temperature type semiconductor wafers. For the self-setting detection temperature type semiconductor wafers, the test temperature of the self-setting detection temperature type semiconductor wafers is manually input.

[0092] In one embodiment of the present invention, the test data collection module sets basic information tags for the data collected by each node, including the following steps:

[0093] Obtain basic information data of semiconductor wafers, and extract data on material type, size, doping type, doping concentration and performance standards from the basic information data;

[0094] Generate a unique code for the semiconductor wafer, and use the key fields of the semiconductor wafer's code, material type and size as basic information tags based on the extracted material type, size and coding information of the semiconductor wafer;

[0095] According to the extracted data of doping type, doping concentration and performance standard of the semiconductor wafer, a parameter list of the semiconductor wafer is constructed, and the parameter list of the semiconductor wafer is stored in each node;

[0096] A corresponding key-value pair is set for each type of data in the parameter list of the semiconductor wafer, and key-value pairs corresponding to the doping type, doping concentration, crystal structure, and performance standard data types are added to the basic information tag.

[0097] In one embodiment of the present invention, the intelligent scheduling module detects the use status of the test machine at the current node, and according to the current test machine status and the basic information of the semiconductor wafer, performs a test on the semiconductor wafer after thin film deposition by matching the semiconductor wafer at the thin film deposition node with the test machine, including the following steps:

[0098] Count the test machines of thin film deposition nodes, including: sorting machine, probe station and scanning test station, and number the test machines of thin film deposition nodes, among which the scanning test station includes: SEM scanning electron microscope and optical interferometer;

[0099] Detect the usage status of the current node test machine. For the probe station, collect the usage status of the probe station including: the number of wafers to be tested by the probe station and the size of the last wafer to be tested by the probe station. For the scanning test station, collect the number of wafers to be tested by the scanning test station;

[0100] According to the current test machine status and the size information in the basic information of the semiconductor wafer, select 2 to 3 probe stations with the least number of wafers to be tested in the probe station;

[0101] Detect the size of the last wafer to be tested of the selected probe station, select the probe station whose area of ​​the last wafer to be tested is closest to the area of ​​the semiconductor wafer after thin film deposition, if there are multiple probe stations that meet the requirements, randomly select a probe station that meets the requirements as the detection machine for electrical testing, and send the number of the detection machine to the sorting machine, which transfers the semiconductor wafer after thin film deposition to the corresponding probe station;

[0102] After the electrical test on the probe station, the scanning test station with the least number of wafers to be tested is selected as the detection machine for three-dimensional point cloud data detection and deposited film thickness data detection, and the number of the detection machine is sent to the sorting machine, which transfers the semiconductor wafers after the electrical test to the corresponding scanning test station.

[0103] In one embodiment of the present invention, the data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer of each node according to the detection data of each node collected by the test data collection module, including the following steps:

[0104] For the lithography node and the etching node, obtain the 3D point cloud data after lithography and etching;

[0105] Through the three-dimensional point cloud data after the wafer lithography process is completed, it is detected whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern. If they are consistent, the lithography node detection is qualified. If not, the lithography node detection is unqualified, and the corresponding coded wafer generates a quality warning signal;

[0106] Through the three-dimensional point cloud data after the wafer etching process is completed, detect whether the depth and shape of the etching position of the wafer at the etching node meet the preset etching depth and shape. If they are consistent, the etching node detection is qualified; if they are inconsistent, the etching node detection is unqualified, and a quality warning signal is generated for the corresponding coded wafer;

[0107] For the ion implantation node, the ion implantation performance evaluation coefficient of the semiconductor wafer is analyzed based on the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation;

[0108] For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected by the test machine to detect whether the corresponding semiconductor wafer has passed the inspection at the node. At the node where the inspection fails, the corresponding coded wafer generates a quality warning signal; if the corresponding semiconductor wafer has passed the inspection at the node, the performance evaluation coefficient of the semiconductor wafer in the thin film deposition stage is analyzed.

[0109] In one embodiment of the present invention, analyzing the ion implantation performance evaluation coefficient of the semiconductor wafer according to the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation includes the following steps:

[0110] Obtaining an X-ray fluorescence spectrum and a Fourier transform infrared spectrum of the semiconductor wafer after ion implantation;

[0111] Extract the doping type and doping concentration data of the wafer through the basic information label of the wafer;

[0112] Obtaining Fourier transform infrared spectra of n-type doped wafers and p-type doped wafers in historical data, and marking the positions, widths, and frequency ranges of the absorption peaks of the Fourier transform infrared spectra of the n-type doped wafers and the p-type doped wafers;

[0113] The deep learning model is trained through the annotated Fourier transform infrared spectra to identify the doping type of the wafer;

[0114] By inputting the Fourier transform infrared spectrum image collected in real time at the ion implantation node into the trained deep learning model, the wafer is identified as an n-type doped wafer or a p-type doped wafer;

[0115] According to the X-ray fluorescence spectrum of the semiconductor wafer, characteristic peaks in the X-ray fluorescence spectrum are extracted, and the area sum of the characteristic peaks in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity;

[0116] Selecting several groups of semiconductor wafers of the same doping type to be tested, obtaining actual doping concentration data of the several groups of wafers, and detecting characteristic peak intensities of the several groups of wafers;

[0117] The performance evaluation coefficient of the ion implantation stage of the semiconductor wafer is calculated by the following formula:

[0118]

[0119] Where: α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, C std To extract the standard doping concentration data of the wafer, C sample is the doping concentration of the semiconductor wafer during the ion implantation stage, C i is the average value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the average value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of crystal elements;

[0120] In one embodiment of the present invention, for a thin film deposition node, electrical test data, three-dimensional point cloud data and deposited film thickness data of a semiconductor wafer after thin film deposition collected by a test machine are obtained, and the corresponding semiconductor wafer is detected to be qualified at the node. If the node is detected to be unqualified, a quality warning signal is generated for the corresponding coded wafer, including the following steps:

[0121] For the thin film deposition node, the electrical test data of the semiconductor wafer after thin film deposition collected by the test machine is obtained to detect whether the electrical test data exceeds the preset threshold range. If so, the thin film deposition node detection fails, and a quality warning signal is generated for the corresponding coded wafer. Otherwise, the three-dimensional point cloud data and the deposited film thickness data are detected;

[0122] Detect whether the difference between the highest position and the lowest thickness of the deposited film position of the three-dimensional point cloud data is greater than the preset maximum threshold. If so, the film deposition node detection is unqualified, and the corresponding coded wafer generates a quality warning signal. Otherwise, the deposited film thickness data is detected;

[0123] Detect whether the deposited film thickness data belongs to the preset threshold range. If not, the film deposition node detection fails, and the corresponding coded wafer generates a quality warning signal. Otherwise, analyze the performance evaluation coefficient of the semiconductor wafer at the film deposition stage.

[0124] In one embodiment of the present invention, analyzing the performance evaluation coefficient of the thin film deposition stage of a semiconductor wafer includes the following steps:

[0125] Through the three-dimensional point cloud data of the wafer, the distance from each point on the non-etching position surface to the preset detection surface is detected;

[0126] Extract the standard values ​​of threshold voltage, leakage current, saturation current and conductivity from the performance standard data of the basic information of the semiconductor wafer;

[0127] Obtain electrical test data of semiconductor wafers, and calculate the average values ​​of threshold voltage, leakage current, saturation current and conductivity at different test temperatures;

[0128] According to the electrical test data of the semiconductor wafer and the distance from each point on the non-etched surface to the preset detection surface, the performance evaluation coefficient of the thin film deposition stage is calculated by the following formula:

[0129]

[0130] Among them, β is the performance evaluation coefficient of the thin film deposition stage, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, and σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, and σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the non-etching position surface to the preset detection surface, and σ0 is the mean value of the distance from each point on the non-etching position surface to the preset detection surface.

[0131] In one embodiment of the present invention, the node early warning module performs a phased early warning on semiconductor wafers with abnormal phase performance according to the phase performance evaluation coefficient of the semiconductor wafers of each node, including the following steps:

[0132] According to the quality warning signal of the wafer with corresponding code generated by the data analysis module, a phased warning is issued for semiconductor wafers with abnormal performance at the corresponding node stage;

[0133] According to the stage performance evaluation results of the semiconductor wafers at each node, if the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds a preset threshold, a stage warning will be issued for the semiconductor wafer with abnormal stage performance at the corresponding node.

[0134] Specifically, in the present embodiment, statistics are collected on the ion implantation stage performance evaluation coefficients or the thin film deposition stage performance evaluation coefficients of semiconductor wafers at corresponding stage nodes for a large number of qualified wafers. If the ion implantation stage performance evaluation coefficient of the semiconductor wafer exceeds 0.8%, or the thin film deposition stage performance evaluation coefficient exceeds 0.6%, a stage-by-stage warning is issued for semiconductor wafers with abnormal performance at the corresponding node stage.

[0135] In one embodiment of the present invention, the node early warning module analyzes the comprehensive performance coefficient of the semiconductor wafer and issues an early warning for the semiconductor wafer that does not meet the standards, including the following steps:

[0136] According to the stage performance evaluation coefficient of the semiconductor wafer at each node, for the wafers that have not shown a stage warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed by the following formula:

[0137] K=e -(α+β)

[0138] Wherein, K is the comprehensive performance coefficient of the semiconductor wafer, α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, and β is the performance evaluation coefficient of the thin film deposition stage;

[0139] If the comprehensive performance coefficient of the semiconductor wafer is less than a preset threshold, the corresponding semiconductor wafer has quality risks, and an early warning is issued for the semiconductor wafer with quality risks.

[0140] Specifically, in this embodiment, after statistics of comprehensive performance coefficients of a large number of qualified semiconductor wafers, it is set that if the comprehensive performance coefficient of a semiconductor wafer is less than 1, the corresponding semiconductor wafer has quality risk, and an early warning is issued for the semiconductor wafer with quality risk.

[0141] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A semiconductor test management system, characterized in that: include: Information management module: used to obtain and store the basic information of the generated semiconductor wafers, including: material type, size, doping type, doping concentration, crystal structure and performance standards, and set detection nodes for the production process of semiconductor wafers, including: lithography nodes, etching nodes, ion implantation nodes and thin film deposition nodes; Test data acquisition module: for photolithography nodes and etching nodes, the three-dimensional point cloud data after photolithography and etching are detected respectively; for ion implantation nodes, the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are collected; for thin film deposition nodes, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected through the test machine, and basic information labels are set for the data collected at each node; Intelligent scheduling module: used to detect the use status of the test machine at the current node, and according to the current test machine status and basic information of the semiconductor wafer, to match the semiconductor wafer of the thin film deposition node with the test machine to test the semiconductor wafer after thin film deposition; Data analysis module: analyzing the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data collection module; Node warning module: It is used to issue a stage warning for semiconductor wafers with abnormal stage performance according to the stage performance evaluation coefficient of the semiconductor wafers at each node, and to analyze the comprehensive performance coefficient of the semiconductor wafers to issue a warning for semiconductor wafers that do not meet the standards.

2. A semiconductor test management system according to claim 1, characterized in that: The test data acquisition module collects electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after film deposition through the test machine for the film deposition node, including the following steps: For the thin film deposition node, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-set detection temperature type semiconductor wafer according to the material type data of the semiconductor wafer in the basic information tag of the semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes: single crystal silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer; For semiconductor wafers with fixed detection temperature, a high detection temperature, a medium detection temperature and a low detection temperature are set for the semiconductor wafers with fixed detection temperature; For semiconductor wafers with self-set detection temperature, manually input the test temperature of the semiconductor wafers with self-set detection temperature; Under different detection temperatures, the test machine collects electrical test data, surface high-definition images and infrared detection images of the packaged semiconductor wafers. The electrical test data includes threshold voltage, leakage current, saturation current and conductivity.

3. A semiconductor test management system according to claim 1, characterized in that: The test data collection module sets basic information labels for the data collected by each node, including the following steps: Obtain basic information data of semiconductor wafers, and extract data on material type, size, doping type, doping concentration and performance standards from the basic information data; Generate a unique code for the semiconductor wafer, and use the key fields of the semiconductor wafer's code, material type and size as basic information tags based on the extracted material type, size and coding information of the semiconductor wafer; According to the extracted data of doping type, doping concentration and performance standard of the semiconductor wafer, a parameter list of the semiconductor wafer is constructed, and the parameter list of the semiconductor wafer is stored in each node; A corresponding key-value pair is set for each type of data in the parameter list of the semiconductor wafer, and key-value pairs corresponding to the doping type, doping concentration, crystal structure, and performance standard data types are added to the basic information tag.

4. A semiconductor test management system according to claim 1, characterized in that: The intelligent scheduling module detects the use status of the test machine at the current node, and according to the current test machine status and the basic information of the semiconductor wafer, performs a test on the semiconductor wafer after thin film deposition by matching the semiconductor wafer at the thin film deposition node, including the following steps: Count the test machines of thin film deposition nodes, including: sorting machine, probe station and scanning test station, and number the test machines of thin film deposition nodes, among which the scanning test station includes: SEM scanning electron microscope and optical interferometer; Detect the usage status of the current node test machine. For the probe station, collect the usage status of the probe station including: the number of wafers to be tested by the probe station and the size of the last wafer to be tested by the probe station. For the scanning test station, collect the number of wafers to be tested by the scanning test station; According to the current test machine status and the size information in the basic information of the semiconductor wafer, select 2 to 3 probe stations with the least number of wafers to be tested in the probe station; Detect the size of the last wafer to be tested of the selected probe station, select the probe station whose area of ​​the last wafer to be tested is closest to the area of ​​the semiconductor wafer after thin film deposition, if there are multiple probe stations that meet the requirements, randomly select a probe station that meets the requirements as the detection machine for electrical testing, and send the number of the detection machine to the sorting machine, which transfers the semiconductor wafer after thin film deposition to the corresponding probe station; After the electrical test on the probe station, the scanning test station with the least number of wafers to be tested is selected as the detection machine for three-dimensional point cloud data detection and deposited film thickness data detection, and the number of the detection machine is sent to the sorting machine, which transfers the semiconductor wafers after the electrical test to the corresponding scanning test station.

5. A semiconductor test management system according to claim 2, characterized in that: The data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data collection module, including the following steps: For the lithography node and the etching node, obtain the 3D point cloud data after lithography and etching; Through the three-dimensional point cloud data after the wafer lithography process is completed, it is detected whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern. If they are consistent, the lithography node detection is qualified. If not, the lithography node detection is unqualified, and the corresponding coded wafer generates a quality warning signal; Through the three-dimensional point cloud data after the wafer etching process is completed, detect whether the depth and shape of the etching position of the wafer at the etching node meet the preset etching depth and shape. If they are consistent, the etching node detection is qualified; if they are inconsistent, the etching node detection is unqualified, and a quality warning signal is generated for the corresponding coded wafer; For the ion implantation node, the ion implantation performance evaluation coefficient of the semiconductor wafer is analyzed based on the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation; For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected by the test machine to detect whether the corresponding semiconductor wafer has passed the inspection at the node. At the node where the inspection fails, the corresponding coded wafer generates a quality warning signal; if the corresponding semiconductor wafer has passed the inspection at the node, the performance evaluation coefficient of the semiconductor wafer in the thin film deposition stage is analyzed.

6. A semiconductor test management system according to claim 5, characterized in that: According to the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, the ion implantation stage performance evaluation coefficient of the semiconductor wafer is analyzed, including the following steps: Obtaining an X-ray fluorescence spectrum and a Fourier transform infrared spectrum of the semiconductor wafer after ion implantation; Extract the doping type and doping concentration data of the wafer through the basic information label of the wafer; Obtaining Fourier transform infrared spectra of n-type doped wafers and p-type doped wafers in historical data, and marking the positions, widths, and frequency ranges of the absorption peaks of the Fourier transform infrared spectra of the n-type doped wafers and the p-type doped wafers; The deep learning model is trained through the annotated Fourier transform infrared spectra to identify the doping type of the wafer; By inputting the Fourier transform infrared spectrum image collected in real time at the ion implantation node into the trained deep learning model, the wafer is identified as an n-type doped wafer or a p-type doped wafer; According to the X-ray fluorescence spectrum of the semiconductor wafer, characteristic peaks in the X-ray fluorescence spectrum are extracted, and the area sum of the characteristic peaks in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity; Selecting several groups of semiconductor wafers of the same doping type to be tested, obtaining actual doping concentration data of the several groups of wafers, and detecting characteristic peak intensities of the several groups of wafers; The performance evaluation coefficient of the ion implantation stage of the semiconductor wafer is calculated by the following formula: Where: α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, C std To extract the standard doping concentration data of the wafer, C sample is the doping concentration of the semiconductor wafer during the ion implantation stage, C i is the average value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the average value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of crystal elements.

7. A semiconductor test management system according to claim 5, characterized in that: For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition collected by the test machine are obtained, and the corresponding semiconductor wafer is detected to be qualified at the node. If the node is detected to be unqualified, the corresponding coded wafer generates a quality warning signal, including the following steps: For the thin film deposition node, the electrical test data of the semiconductor wafer after thin film deposition collected by the test machine is obtained to detect whether the electrical test data exceeds the preset threshold range. If so, the thin film deposition node detection fails, and a quality warning signal is generated for the corresponding coded wafer. Otherwise, the three-dimensional point cloud data and the deposited film thickness data are detected; Detect whether the difference between the highest position and the lowest thickness of the deposited film position of the three-dimensional point cloud data is greater than the preset maximum threshold. If so, the film deposition node detection is unqualified, and the corresponding coded wafer generates a quality warning signal. Otherwise, the deposited film thickness data is detected; Check whether the deposited film thickness data falls within the preset threshold range. If not, the film deposition node detection fails and the corresponding coded wafer generates a quality warning signal. Otherwise, analyze the performance evaluation coefficient of the semiconductor wafer in the film deposition stage.

8. A semiconductor test management system according to claim 7, characterized in that: Analyzing the performance evaluation coefficient of the thin film deposition stage of a semiconductor wafer includes the following steps: Through the three-dimensional point cloud data of the wafer, the distance from each point on the non-etching position surface to the preset detection surface is detected; Extract the standard values ​​of threshold voltage, leakage current, saturation current and conductivity from the performance standard data of the basic information of the semiconductor wafer; Obtain electrical test data of semiconductor wafers, and calculate the average values ​​of threshold voltage, leakage current, saturation current and conductivity at different test temperatures; According to the electrical test data of the semiconductor wafer and the distance from each point on the non-etched surface to the preset detection surface, the performance evaluation coefficient of the thin film deposition stage is calculated by the following formula: Among them, β is the performance evaluation coefficient of the thin film deposition stage, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, and σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, and σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the non-etching position surface to the preset detection surface, and σ0 is the mean value of the distance from each point on the non-etching position surface to the preset detection surface.

9. A semiconductor test management system according to claim 5, characterized in that: The node early warning module performs a phased early warning on semiconductor wafers with abnormal phase performance according to the phase performance evaluation coefficients of semiconductor wafers at each node, including the following steps: According to the corresponding coded wafer generation quality warning signal generated by the data analysis module, a phased warning is carried out for semiconductor wafers with abnormal performance at the corresponding node stage; According to the stage performance evaluation results of the semiconductor wafers at each node, if the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds a preset threshold, a stage warning will be issued for the semiconductor wafer with abnormal stage performance at the corresponding node.

10. A semiconductor test management system according to claim 9, characterized in that: The node early warning module analyzes the comprehensive performance coefficient of the semiconductor wafer and issues an early warning for semiconductor wafers that do not meet the standards, including the following steps: According to the stage performance evaluation coefficient of the semiconductor wafer at each node, for the wafers that have not shown a stage warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed by the following formula: K=e - (a+b) Wherein, K is the comprehensive performance coefficient of the semiconductor wafer, α is the performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, and β is the performance evaluation coefficient of the thin film deposition stage; If the comprehensive performance coefficient of the semiconductor wafer is less than a preset threshold, the corresponding semiconductor wafer has quality risks, and an early warning is issued for the semiconductor wafer with quality risks.

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