Automatic correction circuit and method for offset voltage of operational amplifier

Abstract

The invention relates to an operational amplifier offset voltage automatic correction circuit and method, and the circuit comprises an operational amplifier main body circuit which comprises an operational amplifier basic circuit and an input offset correction transistor array which are connected in sequence. The operational amplifier main body circuit at least comprises an in-phase input end Vi +, a reverse input end Vi-and an output end Vout; the automatic correction circuit comprises a correction control circuit and a correction mark generation circuit which are connected in sequence, the correction control circuit is electrically connected with the operational amplifier main body circuit, and the correction mark generation circuit is electrically connected with the output end Vout of the operational amplifier main body circuit. The offset voltage automatic correction circuit can adapt to a wide power supply voltage range and has high offset correction precision, the provided offset voltage automatic correction circuit does not need additional analog circuits such as a comparator and a filter, automatic correction control is completed only through digital logic, and the circuit complexity and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an automatic correction circuit and method for offset voltage of an operational amplifier. Background Art

[0002] The operational amplifier is one of the most commonly used analog circuits and is widely used in electronic fields such as signal processing, instrumentation, and automatic control. Input offset voltage is a key technical indicator of the operational amplifier, which characterizes the voltage value that needs to be compensated at the input end in order to make the output 0 when the differential input of the operational amplifier is 0. The existence of offset voltage will seriously deteriorate the gain error and linearity performance of the operational amplifier, thereby reducing the sensitivity of the circuit system and increasing the error. Therefore, in actual circuit design, we must find ways to reduce the offset voltage of the operational amplifier. The offset of the operational amplifier is mainly caused by the asymmetry of the internal components of the operational amplifier. The deviation of the integrated circuit manufacturing process, the temperature and humidity gradient, and the stress gradient of the working environment will cause the electrical characteristics of the semiconductor device to mismatch, thereby causing the operational amplifier to be offset.

[0003] At present, the main methods for reducing operational amplifier offset are: 1) improving semiconductor manufacturing processes, improving processing accuracy, and reducing device mismatch. This is the most essential solution, but the process iteration cycle is long and the cost is high; 2) correcting and compensating for offset from the perspective of circuit design. This method is highly flexible and low-cost, so it is widely used in the circuit field. For example: CN106656081A proposes a method of introducing a trimming current I_trim to compensate for operational amplifier offset, but the current mirror matching accuracy and leakage will restrict the accuracy of offset compensation; CN107370463A proposes a method of compensating for operational amplifier offset by adjusting the load tube substrate voltage and the output stage common mode level, but when the power supply voltage is reduced, the adjustable voltage range is very narrow and is not suitable for low power supply voltage application scenarios; CN107769737A proposes a method of using a comparator to form a feedback loop to adjust the operational amplifier input differential pair transistor substrate voltage to reduce the operational amplifier offset voltage, but additional comparators and filter circuits are required for auxiliary correction, resulting in increased circuit complexity and cost. Summary of the invention

[0004] The present invention provides an automatic correction circuit and method for offset voltage of an operational amplifier, aiming to solve at least one of the technical problems existing in the prior art.

[0005] The technical solution of the present invention is an operational amplifier offset voltage automatic correction circuit, comprising:

[0006] An operational amplifier main circuit, the operational amplifier main circuit comprising an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, the operational amplifier main circuit comprising at least a non-inverting input terminal Vi+, a reverse input terminal Vi- and an output terminal Vout;

[0007] An automatic correction circuit, the automatic correction circuit includes a correction control circuit and a correction mark generating circuit connected in sequence, the correction control circuit is electrically connected to the operational amplifier main circuit, and the correction mark generating circuit is electrically connected to the output terminal Vout of the operational amplifier main circuit.

[0008] Furthermore, the operational amplifier basic circuit includes an input differential pair of transistors and an output array, and the input differential pair of transistors includes a PMOS differential pair of transistors and an NMOS differential pair of transistors; wherein,

[0009] The PMOS differential pair includes an operational amplifier PMOS transistor pm0 at the same-direction input end and an operational amplifier PMOS transistor pm0' at the reverse input end. The source of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the first transistor array of the output array; the source of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the second transistor array of the output array;

[0010] The NMOS differential pair includes an NMOS transistor nm0 at the same-direction input end of the op amp and an NMOS transistor nm0' at the reverse input end of the op amp. The source of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the third transistor array of the output array; the source of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the fourth transistor array of the output array.

[0011] Further, the output array includes a first transistor array, a second transistor array, a third transistor array and a fourth transistor array,

[0012] The first transistor array is a PMOS offset correction tube array at the same direction input end, and the first transistor array includes k PMOS offset correction tubes pm1-pmk, the gate of each PMOS offset correction tube pm1-pmk is respectively connected to the gate of the PMOS transistor pm0 at the same direction input end of the operational amplifier, the source of each PMOS offset correction tube pm1-pmk is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1-pmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect the PMOS transistor pm0 at the same direction input end of the operational amplifier in parallel is controlled by the switch control signal cal_p+[k:1] of the corresponding control end;

[0013] The second transistor array is a reverse input end PMOS offset correction tube array, the second transistor array includes k PMOS offset correction tubes pm1'-pmk', the gate of each PMOS offset correction tube pm1'-pmk' is respectively connected to the gate of the reverse input end PMOS transistor pm0' of the operational amplifier, the source of each PMOS offset correction tube pm1'-pmk' is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1'-pmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the reverse input end PMOS transistor pm0' of the operational amplifier is controlled by the switch control signal cal_p-[k:1] of the corresponding control end;

[0014] The third transistor array is a non-inverting input end NMOS offset correction tube array, and the third transistor array includes k NMOS offset correction tubes nm1-nmk, the gate of each NMOS offset correction tube nm1-nmk is respectively connected to the gate of the non-inverting input end NMOS transistor nm0 of the operational amplifier, the source of each NMOS offset correction tube nm1-nmk is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1-nmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the non-inverting input end NMOS transistor nm0 of the operational amplifier is controlled by the switch control signal cal_n+[k:1] of the corresponding control end;

[0015] The fourth transistor array is a reverse input end NMOS offset correction tube array, and the fourth transistor array includes k NMOS offset correction tubes nm1'~nmk', the gate of each NMOS offset correction tube nm1'~nmk' is respectively connected to the gate of the NMOS transistor nm0' at the reverse input end of the operational amplifier, the source of each NMOS offset correction tube nm1'~nmk' is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1'~nmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the NMOS transistor nm0' at the reverse input end of the operational amplifier is controlled by the switch control signal cal_n-[k:1] of the corresponding control end.

[0016] Further, the sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier are equal, and among the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk', the sizes of the PMOS offset correction tubes with the same sequence number are equal, and the sizes of the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk' used for compensation are set much smaller than the sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier, and the sizes of the k PMOS offset correction tubes are set proportionally from small to large;

[0017] The NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier are equal in size; among the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk', the NMOS offset correction tubes with the same serial number are equal in size; and the sizes of the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk' used for compensation are set much smaller than the sizes of the NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier; the sizes of the k NMOS offset correction tubes are set proportionally from small to large.

[0018] Further, the correction control circuit includes a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit;

[0019] The output end of the k-bit P counter is connected to the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends a cal_p+[k:1] control signal to the first transistor array, and the output end of the P decoding latch circuit sends a cal_p-[k:1] control signal to the second transistor array.

[0020] The output end of the k-bit N counter is connected to the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends a cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends a cal_n-[k:1] control signal to the fourth transistor array.

[0021] Furthermore, the correction control circuit further comprises a reset signal terminal cal_pen of a k-bit P counter, wherein the reset signal terminal cal_pen of the k-bit P counter is connected to an input terminal of the k-bit P counter.

[0022] The correction control circuit further comprises a reset signal terminal cal_nen of a k-bit N counter, and the reset signal terminal cal_nen of the k-bit N counter is connected to an input terminal of the k-bit N counter;

[0023] The correction control circuit further includes a clock driving signal terminal cal_clk, wherein the clock driving signal terminal cal_clk adds 1 to the counting result at the rising edge of each clock, and the input terminal of the k-bit P counter and the input terminal of the k-bit N counter are respectively connected to the clock driving signal terminal cal_clk;

[0024] The correction control circuit further comprises a latch control signal terminal cal_end, to which the input terminal of the k-bit P counter, the input terminal of the P decoding latch circuit, the input terminal of the k-bit N counter and the input terminal of the N decoding latch circuit are respectively connected;

[0025] The correction control circuit further comprises a control signal terminal cal_dir of a decoding circuit, and an input terminal of the P decoding latch circuit and an input terminal of the N decoding latch circuit are respectively connected to the control signal terminal cal_dir of the decoding circuit.

[0026] Furthermore, the correction mark generating circuit includes an output signal adjustment circuit, a correction end detection circuit and a correction direction judgment circuit, the input of the output signal adjustment circuit is connected to the output end Vout of the operational amplifier main circuit, the input of the correction end detection circuit and the input of the correction direction judgment circuit are respectively connected to the output of the output signal adjustment circuit, the output of the correction end detection circuit is connected to the correction control circuit through the latch control signal terminal cal_end, and the output of the correction direction judgment circuit is connected to the correction control circuit through the control signal terminal cal_dir of the decoding circuit.

[0027] Furthermore, the present invention also provides an operating method of an operational amplifier offset voltage automatic correction circuit, which is applied to the operational amplifier offset voltage automatic correction circuit. The operating method of the operational amplifier offset voltage automatic correction circuit comprises the following steps:

[0028] S100, if the PMOS differential pair is in an imbalanced state, correct the imbalance of the PMOS differential pair;

[0029] S200, if the NMOS differential pair is in an imbalanced state, correct the imbalance of the NMOS differential pair;

[0030] S300, latching the correction result, so that the offsets of the PMOS differential pair and the NMOS differential pair of the operational amplifier are corrected and compensated to within the entire input range, and the offset of the main circuit of the operational amplifier is less than an offset correction step value.

[0031] Further, the step S100 includes:

[0032] S110, the reset signal terminal cal_pen of the k-bit P counter is set to 0, so that the output of the k-bit P counter and the P decoding latch circuit of the correction control circuit is cleared to 0, and the PMOS transistor is corrected and reset;

[0033] S120, the reset signal terminal cal_pen of the k-bit P counter is set to 1, at this time the level selection switches s1, s2, s3 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, enabling PMOS correction;

[0034] S130, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the PMOS transistor pm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the PMOS transistor pm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+ is connected to the compensation transistor;

[0035] S140, under the drive of the clock driving signal terminal cal_clk, the k-bit P counter starts to count cumulatively from 0;

[0036] S150, based on the accumulated result of the k-bit P counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the PMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to 0, and the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the reverse input end of the PMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to 0, and the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the PMOS differential pair is increased in real time according to the counting result;

[0037] S160. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latch circuit is latched to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the PMOS differential pair is increased.

[0038] Further, the step S200 includes:

[0039] S210, the reset signal terminal cal_nen of the k-bit N counter is set to 0, so that the outputs of the k-bit N counter and the N decoding latch circuit of the correction control circuit are cleared to 0, and the NMOS transistor is corrected and reset;

[0040] S220, the reset signal terminal cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2, s4 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the NMOS correction common mode level Vcm_n, enabling NMOS correction;

[0041] S230, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the NMOS transistor nm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the compensation transistor is connected to the NMOS transistor nm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+;

[0042] S240, under the driving of the clock driving signal terminal cal_clk, the k-bit N counter starts counting cumulatively from 0;

[0043] S250, based on the accumulated result of the k-bit N counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the NMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to 0, and the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to be equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of offset correction tubes at the reverse input end of the NMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to 0, and the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the NMOS differential pair is increased in real time according to the counting result;

[0044] S260. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and latches the output result of the N decoding latch circuit to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the NMOS differential pair is increased.

[0045] The beneficial effects of the present invention are:

[0046] The operational amplifier offset voltage automatic correction circuit and method can adapt to a wide power supply voltage range and have high offset correction accuracy. The proposed offset voltage automatic correction circuit does not require additional analog circuits such as comparators and filters, and only uses digital logic to complete automatic correction control, thereby reducing circuit complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 FIG. 1 is a schematic diagram of an overall circuit of an automatic offset voltage correction circuit for an operational amplifier according to the present invention.

[0048] Figure 2 FIG. 1 is a circuit diagram of an embodiment of an operational amplifier main circuit in an operational amplifier offset voltage automatic correction circuit according to the present invention.

[0049] Figure 3 FIG. 1 is a circuit diagram of an embodiment of a correction control circuit in an automatic correction circuit for offset voltage of an operational amplifier according to the present invention.

[0050] Figure 4 FIG. 1 is a circuit diagram of an embodiment of a correction flag generating circuit in an automatic correction circuit for offset voltage of an operational amplifier according to the present invention.

[0051] Figure 5 FIG. 1 is a flow chart showing an operation method of the automatic offset voltage correction circuit for an operational amplifier according to the present invention.

[0052] Figure 6 The flowchart shown is a method for correcting the offset of a PMOS differential pair of transistors in the operation method of the automatic offset voltage correction circuit of an operational amplifier according to the present invention.

[0053] Figure 7 The flowchart shown is a method for correcting the offset of an NMOS differential pair of transistors in the operation method of the automatic offset voltage correction circuit of an operational amplifier according to the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of the present invention, so as to fully understand the purpose, scheme and effect of the present invention. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0055] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature, or it may be indirectly fixed or connected to the other feature. In addition, the descriptions of up, down, left, right, top, bottom, etc. used in the present invention are only relative to the relative positional relationship of the components of the present invention in the drawings.

[0056] In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art. The terms used in this specification are only for describing specific embodiments, not for limiting the present invention. The term "and / or" used herein includes any combination of one or more related listed items.

[0057] It should be understood that, although the terms first, second, third, etc. may be used to describe various elements in the present disclosure, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0058] Reference Figures 1 to 7 In some embodiments, the present invention provides an operational amplifier offset voltage automatic correction circuit, referring to Figure 1 , the operational amplifier offset voltage automatic correction circuit comprises:

[0059] An operational amplifier main circuit, the operational amplifier main circuit comprising an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, the operational amplifier main circuit comprising at least a non-inverting input terminal Vi+, a reverse input terminal Vi- and an output terminal Vout;

[0060] An automatic correction circuit, the automatic correction circuit includes a correction control circuit and a correction mark generating circuit connected in sequence, the correction control circuit is electrically connected to the operational amplifier main circuit, and the correction mark generating circuit is electrically connected to the output terminal Vout of the operational amplifier main circuit.

[0061] The beneficial effects of the present invention are:

[0062] The operational amplifier offset voltage automatic correction circuit and method can adapt to a wide power supply voltage range and have high offset correction accuracy. The proposed offset voltage automatic correction circuit does not require additional analog circuits such as comparators and filters, and only uses digital logic to complete automatic correction control, thereby reducing circuit complexity and cost.

[0063] Specifically, refer to Figure 1 , the signal names are explained as follows:

[0064] 1) Vi+ and Vi- are a set of differential input signal terminals of the op amp;

[0065] 2) Vout is the output signal of the op amp;

[0066] 3) Vcm_p is the common mode voltage level of the PMOS differential pair offset correction;

[0067] 4) Vcm_n is the common mode level of the NMOS differential pair offset correction;

[0068] 5) cal_pen is the PMOS differential pair offset correction enable signal;

[0069] 6) cal_nen is the NMOS differential pair offset correction enable signal;

[0070] 7) cal_en is the differential pair calibration enable signal, which is obtained by OR logic of cal_pen and cal_nen. That is, no matter whether the PMOS differential pair or the NMOS differential pair starts calibration, cal_en will be set to 1;

[0071] 8) cal_clk is the clock signal for offset correction;

[0072] 9) cal_dir is the sign signal of the offset correction direction;

[0073] 10) cal_end is the sign signal of offset correction completion;

[0074] 11) cal_p+[k:1] is the control signal of the PMOS offset correction tube at the same-direction input end of the k-bit operational amplifier;

[0075] 12) cal_p-[k:1] is the control signal of the PMOS offset correction tube at the reverse input end of the k-bit op amp;

[0076] 13) cal_n+[k:1] is the control signal of the NMOS offset correction tube at the same-direction input end of the k-bit operational amplifier;

[0077] 14) cal_n-[k:1] is the control signal of the NPMOS offset correction tube at the reverse input terminal of the k-bit operational amplifier.

[0078] Among them, the size of Vcm_p is set to be smaller than the NMOS tube threshold voltage Vthn, so that only the PMOS differential pair is turned on and the NMOS differential pair is turned off; the size of Vcm_n is set to be smaller than the power supply voltage VDD and larger than the difference between the absolute value of VDD and the PMOS tube threshold voltage Vthp, so that only the NMOS differential pair is turned on and the PMOS differential pair is turned off.

[0079] Further, refer to Figure 2 , the operational amplifier basic circuit includes an input differential pair tube and an output array, the input differential pair tube includes a PMOS differential pair tube and an NMOS differential pair tube; wherein,

[0080] The PMOS differential pair includes an operational amplifier PMOS transistor pm0 at the same-direction input end and an operational amplifier PMOS transistor pm0' at the reverse input end. The source of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the first transistor array of the output array; the source of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the second transistor array of the output array;

[0081] The NMOS differential pair includes an NMOS transistor nm0 at the same-direction input end of the op amp and an NMOS transistor nm0' at the reverse input end of the op amp. The source of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the third transistor array of the output array; the source of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the fourth transistor array of the output array.

[0082] Specifically, refer to Figure 2 The basic circuit of the operational amplifier includes an input differential pair and an output stage; the input differential pair is composed of a group of PMOS differential pairs pm0 and pm0' and a group of NMOS differential pairs nm0 and nm0', pm0 is a PMOS transistor at the same-direction input end of the operational amplifier, pm0' is a PMOS transistor at the reverse input end of the operational amplifier, nm0 is an NMOS transistor at the same-direction input end of the operational amplifier, and nm0' is an NMOS transistor at the reverse input end of the operational amplifier.

[0083] Further, refer to Figure 2 , the output array includes a first transistor array, a second transistor array, a third transistor array and a fourth transistor array,

[0084] The first transistor array is a PMOS offset correction tube array at the same direction input end, and the first transistor array includes k PMOS offset correction tubes pm1-pmk, the gate of each PMOS offset correction tube pm1-pmk is respectively connected to the gate of the PMOS transistor pm0 at the same direction input end of the operational amplifier, the source of each PMOS offset correction tube pm1-pmk is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1-pmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect the PMOS transistor pm0 at the same direction input end of the operational amplifier in parallel is controlled by the switch control signal cal_p+[k:1] of the corresponding control end;

[0085] The second transistor array is a reverse input end PMOS offset correction tube array, the second transistor array includes k PMOS offset correction tubes pm1'-pmk', the gate of each PMOS offset correction tube pm1'-pmk' is respectively connected to the gate of the reverse input end PMOS transistor pm0' of the operational amplifier, the source of each PMOS offset correction tube pm1'-pmk' is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1'-pmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the reverse input end PMOS transistor pm0' of the operational amplifier is controlled by the switch control signal cal_p-[k:1] of the corresponding control end;

[0086] The third transistor array is a non-inverting input end NMOS offset correction tube array, and the third transistor array includes k NMOS offset correction tubes nm1-nmk, the gate of each NMOS offset correction tube nm1-nmk is respectively connected to the gate of the non-inverting input end NMOS transistor nm0 of the operational amplifier, the source of each NMOS offset correction tube nm1-nmk is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1-nmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the non-inverting input end NMOS transistor nm0 of the operational amplifier is controlled by the switch control signal cal_n+[k:1] of the corresponding control end;

[0087] The fourth transistor array is a reverse input end NMOS offset correction tube array, and the fourth transistor array includes k NMOS offset correction tubes nm1'~nmk', the gate of each NMOS offset correction tube nm1'~nmk' is respectively connected to the gate of the NMOS transistor nm0' at the reverse input end of the operational amplifier, the source of each NMOS offset correction tube nm1'~nmk' is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1'~nmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the NMOS transistor nm0' at the reverse input end of the operational amplifier is controlled by the switch control signal cal_n-[k:1] of the corresponding control end.

[0088] Specifically, refer to Figure 2 , the output array consists of 4 transistor arrays:

[0089] The first transistor array: a PMOS offset correction transistor array at the same-direction input end, pmk-pm1 are k offset correction transistors of the PMOS pm0 at the same-direction input end, and whether they are connected in parallel to pm0 is controlled by a switch control signal cal_p+[k:1].

[0090] Specifically, cal_p+[k:1] is a k-bit control signal of the PMOS offset correction tube at the same-inverting input end of the op amp. If one of the bits cal_p+[i]=1, the corresponding switch is closed, and the i-th P-type offset correction tube pmi of the first transistor array is connected in parallel to the input tube pm0 at the same-inverting input end; if cal_p+[i]=0, the corresponding switch is opened, and the i-th P-type offset correction tube pmi of the first transistor array is disconnected from the input tube pm0 at the same-inverting input end; where i=1,2,…,k.

[0091] The second transistor array: a reverse input end PMOS offset correction transistor array, pmk'-pm1' are k offset correction transistors of the reverse input end PMOS pm0', and whether to be connected in parallel to pm0' is controlled by a switch control signal cal_p-[k:1].

[0092] Specifically, cal_p-[k:1] is a k-bit control signal of the PMOS offset correction tube at the inverting input end of the op amp. If one of the bits cal_p-[i]=1, the corresponding switch is closed, and the i-th P-type offset correction tube pmi' of the second transistor array is connected in parallel to the inverting input end input tube pm0'; if cal_p-[i]=0, the corresponding switch is opened, and the i-th P-type offset correction tube pmi' of the second transistor array is disconnected from the inverting input end input tube pm0'; where i=1, 2,…, k.

[0093] The third transistor array: a non-inverting input end NMOS offset correction transistor array, nmk~nm1 are k offset correction transistors of the non-inverting input end NMOSnm0, and whether they are connected in parallel to nm0 is controlled by a switch control signal cal_n+[k:1].

[0094] Specifically, cal_n+[k:1] is a k-bit control signal of the NMOS offset correction tube at the same-inverting input end of the op amp. If one of the bits cal_n+[i]=1, the corresponding switch is closed, and the i-th N-type offset correction tube nmi of the third transistor array is connected in parallel to the input tube nm0 at the same-inverting input end; if cal_n+[i]=0, the corresponding switch is opened, and the i-th N-type offset correction tube nmi of the third transistor array is disconnected from the input tube nm0 at the same-inverting input end; where i=1,2,…,k.

[0095] The fourth transistor array: a reverse input end NMOS offset correction transistor array, nmk'-nm1' are k offset correction transistors of the reverse input end NMOS nm0', and whether to be connected in parallel to nm0' is controlled by a switch control signal cal_n-[k:1].

[0096] Specifically, cal_n-[k:1] is a k-bit control signal of the NMOS offset correction tube at the inverting input end of the op amp. If one of the bits cal_n-[i]=1, the corresponding switch is closed, and the i-th N-type offset correction tube nmi' of the fourth transistor array is connected in parallel to the inverting input end input tube nm0'; if cal_n-[i]=0, the corresponding switch is opened, and the i-th N-type offset correction tube nmi' of the fourth transistor array is disconnected from the inverting input end input tube nm0'; where i=1, 2,…, k.

[0097] Further, refer to Figure 2 , the sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier are equal, among the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk', the sizes of the PMOS offset correction tubes with the same sequence number are equal, and the sizes of the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk' used for compensation are set much smaller than the sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier, and the sizes of the k PMOS offset correction tubes are set proportionally from small to large;

[0098] The NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier are equal in size; among the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk', the NMOS offset correction tubes with the same serial number are equal in size; and the sizes of the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk' used for compensation are set much smaller than the sizes of the NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier; the sizes of the k NMOS offset correction tubes are set proportionally from small to large.

[0099] Specifically, the PMOS differential pair tubes pm0 and pm0' are of equal size, the PMOS offset correction tubes pmk~pm1 and pmk'~pm1' of the same serial number are of equal size, and the offset correction tubes pmk~pm1 and pmk'~pm1' used for compensation are set to be much smaller than the PMOS differential pair tubes pm0 and pm0'. The size of the offset correction tube can be set proportionally from small to large. The NMOS differential pair tubes nm0 and nm0' are of equal size, the NMOS offset correction tubes nmk~nm1 and nmk'~nm1' of the same serial number are of equal size, and the offset correction tubes nmk~nm1 and nmk'~nm1' used for compensation are set to be much smaller than the NMOS differential pair tubes nm0 and nm0'. The size of the offset correction tube can be set proportionally from small to large.

[0100] Further, refer to Figure 3 , the correction control circuit includes a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit;

[0101] The output end of the k-bit P counter is connected to the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends a cal_p+[k:1] control signal to the first transistor array, and the output end of the P decoding latch circuit sends a cal_p-[k:1] control signal to the second transistor array.

[0102] The output end of the k-bit N counter is connected to the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends a cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends a cal_n-[k:1] control signal to the fourth transistor array.

[0103] Further, refer to Figure 3 , the correction control circuit also includes a reset signal terminal cal_pen of the k-bit P counter, the reset signal terminal cal_pen of the k-bit P counter is connected to the input terminal of the k-bit P counter,

[0104] The correction control circuit further comprises a reset signal terminal cal_nen of a k-bit N counter, and the reset signal terminal cal_nen of the k-bit N counter is connected to an input terminal of the k-bit N counter;

[0105] The correction control circuit further includes a clock driving signal terminal cal_clk, wherein the clock driving signal terminal cal_clk adds 1 to the counting result at the rising edge of each clock, and the input terminal of the k-bit P counter and the input terminal of the k-bit N counter are respectively connected to the clock driving signal terminal cal_clk;

[0106] The correction control circuit further comprises a latch control signal terminal cal_end, to which the input terminal of the k-bit P counter, the input terminal of the P decoding latch circuit, the input terminal of the k-bit N counter and the input terminal of the N decoding latch circuit are respectively connected;

[0107] The correction control circuit further comprises a control signal terminal cal_dir of a decoding circuit, and an input terminal of the P decoding latch circuit and an input terminal of the N decoding latch circuit are respectively connected to the control signal terminal cal_dir of the decoding circuit.

[0108] Specifically, refer to Figure 3 ,

[0109] cal_clk is used as the clock driving signal for the two counters, and the counting result is increased by 1 at the rising edge of each clock.

[0110] cal_pen serves as the reset signal of the k-bit P counter. When cal_pen=0, the PMOS differential pair correction is turned off, and the output result cal_pi[k:1] of the k-bit P counter is reset to 0. When cal_pen=1, the counting function of the k-bit P counter 1 is turned on.

[0111] cal_nen is used as the reset signal of the k-bit N counter. When cal_nen=0, the NMOS differential pair correction is turned off and the output result cal_ni[k:1] of the k-bit N counter is reset to 0. When cal_nen=1, the counting function of the k-bit N counter is turned on.

[0112] cal_end serves as the control signal of the counter and the latch control signal of the decoding latch circuit. When the correction is not completed, cal_end=0, and the counter counts normally; when the correction is completed, cal_end is set to 1, the counter stops counting, the counting result is maintained, and the correction result is latched.

[0113] cal_dir serves as the control signal of the two decoding circuits. If cal_dir=0, it means that the op amp currently has a positive offset voltage and needs negative compensation. Therefore, cal_p+[k:1] and cal_n+[k:1] are both set to 0, and the coding control cal_p-[k:1]=cal_pi[k:1], cal_n-[k:1]=cal_ni[k:1]; conversely, if cal_dir=1, it means that the op amp currently has a negative offset voltage and needs positive compensation. Therefore, cal_p-[k:1] and cal_n-[k:1] are both set to 0, and the coding control cal_p+[k:1]=cal_pi[k:1], cal_n+[k:1]=cal_ni[k:1].

[0114] Further, refer to Figure 4 The correction mark generating circuit includes an output signal adjustment circuit, a correction end detection circuit and a correction direction judgment circuit. The input of the output signal adjustment circuit is connected to the output end Vout of the operational amplifier main circuit. The input of the correction end detection circuit and the input of the correction direction judgment circuit are respectively connected to the output of the output signal adjustment circuit. The output of the correction end detection circuit is connected to the correction control circuit through the latch control signal terminal cal_end. The output of the correction direction judgment circuit is connected to the correction control circuit through the control signal terminal cal_dir of the decoding circuit.

[0115] Specifically, refer to Figure 4 , the correction end detection circuit is used to detect the edge flip of the op amp output Vout during the correction process. If Vout does not flip during the correction process, cal_end=0, indicating that the correction is not completed and the correction continues. If Vout changes level during the correction process, cal_end will be set to 1, indicating that the correction is completed and the correction stops. The correction direction judgment circuit is used to obtain the correction direction. Define the offset voltage Vos=Vi+-Vi-. If Vout is at a high level when the correction is just turned on, it means that Vos=Vi+-Vi->0, indicating that the op amp currently has a positive offset voltage and needs to be compensated negatively. Set cal_dir to 0 and control the correction control circuit to generate a negative compensation control signal; conversely, if Vout is at a low level when the correction is just turned on, it means that Vos=Vi+-Vi-<0, indicating that the op amp currently has a negative offset voltage and needs to be compensated positively. Set cal_dir to 1 and control the correction control circuit to generate a positive compensation control signal.

[0116] Using the offset correction direction flag signal cal_dir to control the correction direction can reduce the correction steps and improve the correction efficiency.

[0117] In the output signal adjustment circuit, Vout is an analog signal that needs to pass through the output signal adjustment circuit to achieve the purpose of shaping and level conversion, and then connected to the following two digital circuits (detection circuit and judgment circuit). A two-stage inverter is used here to achieve this.

[0118] Further, refer to Figure 5 The present invention also provides an operation method of an operational amplifier offset voltage automatic correction circuit, which is applied to the operational amplifier offset voltage automatic correction circuit. The operation method of the operational amplifier offset voltage automatic correction circuit comprises the following steps:

[0119] S100, if the PMOS differential pair is in an imbalanced state, correct the imbalance of the PMOS differential pair;

[0120] S200, if the NMOS differential pair is in an imbalanced state, correct the imbalance of the NMOS differential pair;

[0121] S300, latching the correction result, so that the offsets of the PMOS differential pair and the NMOS differential pair of the operational amplifier are corrected and compensated to within the entire input range, and the offset of the main circuit of the operational amplifier is less than an offset correction step value.

[0122] Specifically, regarding step S100 and step S200, in actual engineering, when chips are tested in large quantities on a machine, the cost will not be increased to determine whether the PMOS tube is misaligned or the NMOS is misaligned, but the misalignments of the PMOS and NMOS are corrected in sequence at one time.

[0123] Further, refer to Figure 6 , the step S100 comprises:

[0124] S110, the reset signal terminal cal_pen of the k-bit P counter is set to 0, so that the output of the k-bit P counter and the P decoding latch circuit of the correction control circuit is cleared to 0, and the PMOS transistor is corrected and reset;

[0125] S120, the reset signal terminal cal_pen of the k-bit P counter is set to 1, at this time the level selection switches s1, s2, s3 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, enabling PMOS correction;

[0126] S130, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the PMOS transistor pm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the PMOS transistor pm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+ is connected to the compensation transistor;

[0127] S140, under the drive of the clock driving signal terminal cal_clk, the k-bit P counter starts to count cumulatively from 0;

[0128] S150, based on the accumulated result of the k-bit P counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the PMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to 0, and the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the reverse input end of the PMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to 0, and the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the PMOS differential pair is increased in real time according to the counting result;

[0129] S160. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latch circuit is latched to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the PMOS differential pair is increased.

[0130] Further, refer to Figure 7 , the step S200 comprises:

[0131] S210, the reset signal terminal cal_nen of the k-bit N counter is set to 0, so that the outputs of the k-bit N counter and the N decoding latch circuit of the correction control circuit are cleared to 0, and the NMOS transistor is corrected and reset;

[0132] S220, the reset signal terminal cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2, s4 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the NMOS correction common mode level Vcm_n, enabling NMOS correction;

[0133] S230, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the NMOS transistor nm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the compensation transistor is connected to the NMOS transistor nm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+;

[0134] S240, under the driving of the clock driving signal terminal cal_clk, the k-bit N counter starts counting cumulatively from 0;

[0135] S250, based on the accumulated result of the k-bit N counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the NMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to 0, and the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to be equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of offset correction tubes at the reverse input end of the NMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to 0, and the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the NMOS differential pair is increased in real time according to the counting result;

[0136] S260. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and latches the output result of the N decoding latch circuit to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the NMOS differential pair is increased.

[0137] Specifically, s1, s2, s3, and s4 are level selection switches, wherein the control terminals of s1 and s2 are connected to cal_en, the control terminal of s3 is connected to cal_pen, and the control terminal of s4 is connected to cal_nen. When the control terminal level of the switch is 1, the switch is turned on, otherwise the switch is turned off.

[0138] In a specific embodiment, in step S300, the control signals cal_p+[k:1], cal_p-[k:1], cal_n+[k:1], cal_n-[k:1] of the offset correction transistors are latched when the correction is completed and loaded into the input offset correction transistor array.

[0139] At this point, the offsets of the PMOS differential pair and NMOS differential pair of op amps have been corrected and compensated. In normal operation, the offset of the op amp will be less than one offset correction step in the entire input range. The size of the correction step determines the size of the final offset voltage after correction. Setting the size of the offset correction tube smaller and increasing the correction bit k can make the correction more precise.

[0140] In addition, in step S100 and step S200, there is no order of precedence for the PMOS differential pair offset calibration and the NMOS differential pair offset calibration, but they must be performed separately, and one can be calibrated after the other is completed.

[0141] Under normal circumstances, the chip only needs to be calibrated once at the factory and the calibration result can be saved. When used subsequently, only the factory calibration result needs to be loaded to keep the op amp in a low offset state after compensation.

[0142] The above is only a preferred embodiment of the present invention. The present invention is not limited to the above implementation. As long as the technical effect of the present invention is achieved by the same means, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure. All should belong to the protection scope of the present invention. Within the protection scope of the present invention, its technical scheme and / or implementation method can have various modifications and changes.

Claims

1. An operational amplifier offset voltage automatic correction circuit, characterized in that: include: An operational amplifier main circuit, the operational amplifier main circuit comprising an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, the operational amplifier main circuit comprising at least a non-inverting input terminal Vi+, a reverse input terminal Vi- and an output terminal Vout; An automatic correction circuit, the automatic correction circuit includes a correction control circuit and a correction mark generating circuit connected in sequence, the correction control circuit is electrically connected to the operational amplifier main circuit, and the correction mark generating circuit is electrically connected to the output terminal Vout of the operational amplifier main circuit.

2. The operational amplifier offset voltage automatic correction circuit according to claim 1, characterized in that: The operational amplifier basic circuit includes an input differential pair of transistors and an output array, wherein the input differential pair of transistors includes a PMOS differential pair of transistors and an NMOS differential pair of transistors; wherein, The PMOS differential pair includes an operational amplifier PMOS transistor pm0 at the same-direction input end and an operational amplifier PMOS transistor pm0' at the reverse input end. The source of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0 at the same-direction input end is connected to the first transistor array of the output array; the source of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end of the first current source Ip, the drain of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the output end Vout, and the gate of the operational amplifier PMOS transistor pm0' at the reverse input end is connected to the second transistor array of the output array; The NMOS differential pair includes an NMOS transistor nm0 at the same-direction input end of the op amp and an NMOS transistor nm0' at the reverse input end of the op amp. The source of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0 at the same-direction input end of the op amp is connected to the third transistor array of the output array; the source of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end of the second current source In, the drain of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the output end Vout, and the gate of the NMOS transistor nm0' at the reverse input end of the op amp is connected to the fourth transistor array of the output array.

3. The automatic offset voltage correction circuit for an operational amplifier according to claim 2, characterized in that: The output array includes a first transistor array, a second transistor array, a third transistor array and a fourth transistor array, The first transistor array is a PMOS offset correction tube array at the same direction input end, and the first transistor array includes k PMOS offset correction tubes pm1-pmk, the gate of each PMOS offset correction tube pm1-pmk is respectively connected to the gate of the PMOS transistor pm0 at the same direction input end of the operational amplifier, the source of each PMOS offset correction tube pm1-pmk is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1-pmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect the PMOS transistor pm0 at the same direction input end of the operational amplifier in parallel is controlled by the switch control signal cal_p+[k:1] of the corresponding control end; The second transistor array is a reverse input end PMOS offset correction tube array, the second transistor array includes k PMOS offset correction tubes pm1'-pmk', the gate of each PMOS offset correction tube pm1'-pmk' is respectively connected to the gate of the reverse input end PMOS transistor pm0' of the operational amplifier, the source of each PMOS offset correction tube pm1'-pmk' is respectively connected to the output end of the first current source Ip, the drain of each PMOS offset correction tube pm1'-pmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the reverse input end PMOS transistor pm0' of the operational amplifier is controlled by the switch control signal cal_p-[k:1] of the corresponding control end; The third transistor array is a non-inverting input end NMOS offset correction tube array, and the third transistor array includes k NMOS offset correction tubes nm1-nmk, the gate of each NMOS offset correction tube nm1-nmk is respectively connected to the gate of the non-inverting input end NMOS transistor nm0 of the operational amplifier, the source of each NMOS offset correction tube nm1-nmk is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1-nmk is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the non-inverting input end NMOS transistor nm0 of the operational amplifier is controlled by the switch control signal cal_n+[k:1] of the corresponding control end; The fourth transistor array is a reverse input end NMOS offset correction tube array, and the fourth transistor array includes k NMOS offset correction tubes nm1'~nmk', the gate of each NMOS offset correction tube nm1'~nmk' is respectively connected to the gate of the NMOS transistor nm0' at the reverse input end of the operational amplifier, the source of each NMOS offset correction tube nm1'~nmk' is respectively connected to the input end of the second current source In, the drain of each NMOS offset correction tube nm1'~nmk' is respectively connected to the corresponding control end of the correction control circuit, and whether to connect in parallel to the NMOS transistor nm0' at the reverse input end of the operational amplifier is controlled by the switch control signal cal_n-[k:1] of the corresponding control end.

4. The operational amplifier offset voltage automatic correction circuit according to claim 3, characterized in that: The sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier are equal, and among the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk', the sizes of the PMOS offset correction tubes with the same sequence number are equal, and the sizes of the k PMOS offset correction tubes pm1-pmk and the k PMOS offset correction tubes pm1'-pmk' used for compensation are set much smaller than the sizes of the PMOS transistor pm0 at the same-direction input terminal of the operational amplifier of the PMOS differential pair tube and the PMOS transistor pm0' at the reverse input terminal of the operational amplifier, and the sizes of the k PMOS offset correction tubes are set proportionally from small to large; The NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier are equal in size; among the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk', the NMOS offset correction tubes with the same serial number are equal in size; and the sizes of the k NMOS offset correction tubes nm1~nmk and the k NMOS offset correction tubes nm1'~nmk' used for compensation are set much smaller than the sizes of the NMOS transistor nm0 at the same-direction input terminal of the operational amplifier of the NMOS differential pair and the NMOS transistor nm0' at the reverse input terminal of the operational amplifier; the sizes of the k NMOS offset correction tubes are set proportionally from small to large.

5. The operational amplifier offset voltage automatic correction circuit according to claim 1, characterized in that: The correction control circuit includes a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit; The output end of the k-bit P counter is connected to the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends a cal_p+[k:1] control signal to the first transistor array, and the output end of the P decoding latch circuit sends a cal_p-[k:1] control signal to the second transistor array. The output end of the k-bit N counter is connected to the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends a cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends a cal_n-[k:1] control signal to the fourth transistor array.

6. The automatic offset voltage correction circuit for an operational amplifier according to claim 5, characterized in that: The correction control circuit further includes a reset signal terminal cal_pen of a k-bit P counter, wherein the reset signal terminal cal_pen of the k-bit P counter is connected to an input terminal of the k-bit P counter. The correction control circuit further comprises a reset signal terminal cal_nen of a k-bit N counter, and the reset signal terminal cal_nen of the k-bit N counter is connected to an input terminal of the k-bit N counter; The correction control circuit further includes a clock driving signal terminal cal_clk, wherein the clock driving signal terminal cal_clk adds 1 to the counting result at the rising edge of each clock, and the input terminal of the k-bit P counter and the input terminal of the k-bit N counter are respectively connected to the clock driving signal terminal cal_clk; The correction control circuit further comprises a latch control signal terminal cal_end, to which the input terminal of the k-bit P counter, the input terminal of the P decoding latch circuit, the input terminal of the k-bit N counter and the input terminal of the N decoding latch circuit are respectively connected; The correction control circuit further comprises a control signal terminal cal_dir of a decoding circuit, and an input terminal of the P decoding latch circuit and an input terminal of the N decoding latch circuit are respectively connected to the control signal terminal cal_dir of the decoding circuit.

7. The operational amplifier offset voltage automatic correction circuit according to claim 1, characterized in that: The correction mark generating circuit includes an output signal adjustment circuit, a correction end detection circuit and a correction direction judgment circuit. The input of the output signal adjustment circuit is connected to the output end Vout of the operational amplifier main circuit, the input of the correction end detection circuit and the input of the correction direction judgment circuit are respectively connected to the output of the output signal adjustment circuit, the output of the correction end detection circuit is connected to the correction control circuit through the latch control signal terminal cal_end, and the output of the correction direction judgment circuit is connected to the correction control circuit through the control signal terminal cal_dir of the decoding circuit.

8. An operating method of an operational amplifier offset voltage automatic correction circuit, characterized in that: Applied to the automatic offset voltage correction circuit of an operational amplifier according to any one of claims 1 to 7, the operating method of the automatic offset voltage correction circuit of an operational amplifier comprises the following steps: S100, if the PMOS differential pair is in an imbalanced state, correct the PMOS differential pair imbalance; S200, if the NMOS differential pair is in an imbalanced state, correct the imbalance of the NMOS differential pair; S300, latching the correction result, so that the offsets of the PMOS differential pair and the NMOS differential pair of the operational amplifier are corrected and compensated to within the entire input range, and the offset of the main circuit of the operational amplifier is less than an offset correction step value.

9. The operating method of the operational amplifier offset voltage automatic correction circuit according to claim 8, characterized in that: The step S100 includes: S110, the reset signal terminal cal_pen of the k-bit P counter is set to 0, so that the output of the k-bit P counter and the P decoding latch circuit of the correction control circuit is cleared to 0, and the PMOS transistor is corrected and reset; S120, the reset signal terminal cal_pen of the k-bit P counter is set to 1, at this time the level selection switches s1, s2, s3 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, enabling PMOS correction; S130, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the PMOS transistor pm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the PMOS transistor pm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+ is connected to the compensation transistor; S140, under the drive of the clock driving signal terminal cal_clk, the k-bit P counter starts to count cumulatively from 0; S150, based on the accumulated result of the k-bit P counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the PMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to 0, and the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the reverse input end of the PMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_p-[k:1] of the PMOS offset correction tube at the reverse input end to 0, and the control signal cal_p+[k:1] of the PMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the PMOS differential pair is increased in real time according to the counting result; S160. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latch circuit is latched to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the PMOS differential pair is increased.

10. The operating method of the operational amplifier offset voltage automatic correction circuit according to claim 8, characterized in that: The step S200 includes: S210, the reset signal terminal cal_nen of the k-bit N counter is set to 0, so that the outputs of the k-bit N counter and the N decoding latch circuit of the correction control circuit are cleared to 0, and the NMOS transistor is corrected and reset; S220, the reset signal terminal cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2, s4 are closed, the in-phase input terminal Vi+ and the reverse input terminal Vi- of the operational amplifier main circuit are shorted to the NMOS correction common mode level Vcm_n, enabling NMOS correction; S230, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtain the correction direction, if the output terminal Vout is at a high level, set the control signal terminal cal_dir of the decoding circuit to 0, negative compensation is required, and the compensation transistor is connected to the NMOS transistor nm0' at the reverse input terminal of the operational amplifier main circuit at the reverse input terminal Vi-; if the output terminal Vout is at a low level, set the control signal terminal cal_dir of the decoding circuit to 1, positive compensation is required, and the compensation transistor is connected to the NMOS transistor nm0 at the same input terminal of the operational amplifier main circuit at the same input terminal Vi+; S240, under the driving of the clock driving signal terminal cal_clk, the k-bit N counter starts counting cumulatively from 0; S250, based on the accumulated result of the k-bit N counter, control the number of offset correction tubes incorporated into the same-direction input end or the reverse input end of the NMOS differential pair tube; if the control signal terminal cal_dir of the decoding circuit is 0, set the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to 0, and the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to be equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of offset correction tubes at the reverse input end of the NMOS differential pair is increased in real time according to the counting result; conversely, if the control signal terminal cal_dir of the decoding circuit is 1, set the control signal cal_n-[k:1] of the NMOS offset correction tube at the reverse input end to 0, and the control signal cal_n+[k:1] of the NMOS offset correction tube at the same-direction input end to be equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes at the same-direction input end of the NMOS differential pair is increased in real time according to the counting result; S260. Determine whether the offset correction is completed based on the change in the output result of the operational amplifier main circuit. The correction mark generating circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time. If it is detected that the output level of the operational amplifier main circuit is reversed, the latch control signal terminal cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and latches the output result of the N decoding latch circuit to keep the number of connected compensation transistors unchanged. If it is detected that the output level of the operational amplifier main circuit is not reversed, the latch control signal terminal cal_end remains at 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latch circuit continue to accumulate, and the number of offset correction transistors incorporated into the NMOS differential pair is increased.

Images