Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of power semiconductor devices, and more specifically, to a transistor with high electron mobility and a method for manufacturing the same. Background Art

[0002] Group III nitride semiconductors are an important new type of semiconductor material, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, Al InGaN, etc. Taking advantage of the direct band gap, wide bandgap, high breakdown electric field strength and other advantages of the Group III nitride semiconductors, through the optimization design of device structure and process, Group III nitride semiconductors have great prospects in the field of power semiconductors. An important device type of Group III nitride semiconductors is high electron mobility transistors, and it is desirable to develop high electron mobility transistors with high withstand voltage, high power and low on-resistance and other high performance.

[0003] Existing high electron mobility transistors have problems such as complex structure, complex process, and high cost. In addition, the structure in the high electron mobility transistor, for example, the nucleation layer can be strip-shaped. During the growth process, these strip-shaped structures are prone to some gaps or uneven surfaces; the semiconductor layer structure of the epitaxial high electron mobility transistor is usually layered, which is prone to problems such as excessive internal stress; and such a layered structure is not conducive to realizing a device structure with specific functions. Based on this, the present disclosure provides a novel semiconductor device structure and a manufacturing method thereof, aiming to overcome the above defects and provide a semiconductor device with simple structure, simple process, low cost and excellent electrical performance. Summary of the invention

[0004] A brief overview of the present disclosure will be given below in order to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is simply to give certain concepts in a simplified form as a prelude to a more detailed description discussed later.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device comprising:

[0006] Silicon substrate;

[0007] forming a first insulating layer on a first surface of the silicon substrate;

[0008] forming an opening on the first insulating layer to expose a portion of the substrate;

[0009] forming a groove on the substrate corresponding to the opening;

[0010] forming a single crystal nucleation layer in the groove;

[0011] forming a polycrystalline or amorphous nucleation material on the first insulating layer;

[0012] Taking the single crystal nucleation layer as the nucleation center, a first semiconductor layer is grown laterally epitaxially.

[0013] Furthermore, the single crystal nucleation layer is single crystal AlN, and the polycrystalline or amorphous nucleation material is polycrystalline or amorphous AlN.

[0014] Furthermore, the first insulating layer is a SiO2 layer or a Si3N4 layer.

[0015] Furthermore, the first semiconductor layer is a nitride semiconductor layer.

[0016] Furthermore, the depth of the groove is 0.2-10 microns.

[0017] Furthermore, the depth of the groove is about 1 micron.

[0018] Furthermore, an insulating protection layer is formed on both side walls of the groove and the opening.

[0019] Furthermore, the insulating protective layer is a SiO2 insulating protective layer.

[0020] Furthermore, wherein the semiconductor device is a high mobility transistor, the opening corresponds to the drain of the high mobility transistor.

[0021] The present application also provides a semiconductor device, comprising:

[0022] Silicon substrate;

[0023] forming a first insulating layer on a first surface of the silicon substrate;

[0024] forming an opening on the first insulating layer to expose a portion of the substrate;

[0025] a groove formed on the substrate corresponding to the opening;

[0026] a single crystal nucleation layer formed in the groove;

[0027] forming a polycrystalline or amorphous nucleation material on the first insulating layer; or not forming a nucleation material on the first insulating layer;

[0028] Taking the single crystal nucleation layer as the nucleation center, epitaxially growing a first semiconductor layer laterally;

[0029] The second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;

[0030] forming a second semiconductor layer on the second surface of the first semiconductor layer and the third surface;

[0031] forming a third semiconductor layer on the second surface of the second semiconductor layer and on the third surface;

[0032] A fourth semiconductor layer is formed on a first surface of the first semiconductor layer, a first surface of the second semiconductor layer, and a first surface of the third semiconductor layer.

[0033] Furthermore, a two-dimensional charge carrier gas is formed at the interface between the fourth semiconductor layer and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer.

[0034] Furthermore, an unintentionally doped or low-doped fifth semiconductor layer is included between the fourth semiconductor layer and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, and a two-dimensional charge carrier gas is formed at the interface between the fourth semiconductor layer and the fifth semiconductor layer.

[0035] Furthermore, the doping concentration of the low-doped fifth semiconductor layer is <2E18 / cm 3 .

[0036] Furthermore, the angle is between 30-75 degrees.

[0037] Furthermore, the second semiconductor layer is a P-type buried layer.

[0038] Furthermore, the doping concentration of the P-type buried layer is 1E17-5E19 / cm 3 .

[0039] Furthermore, the first surface of the first semiconductor layer, the first surface of the second semiconductor layer and the first surface of the third semiconductor layer are approximately on the same plane.

[0040] Furthermore, the material of the fourth semiconductor layer is selected from AlGaN, InAlGaN or InAlN.

[0041] Furthermore, a first electrode, a second electrode and a third electrode are formed on the first surface of the fourth semiconductor layer.

[0042] Furthermore, the range of the first end of the second semiconductor layer projected onto the first surface of the substrate overlaps with the range of the second electrode projected onto the substrate; or the range of the first end of the second semiconductor layer projected onto the substrate is within the range of the second electrode projected onto the first surface of the substrate.

[0043] Furthermore, the range of the second end of the second semiconductor layer projected onto the first surface of the substrate overlaps with the range of the first electrode projected onto the substrate; or the range of the second end of the second semiconductor layer projected onto the substrate is within the range of the first electrode projected onto the first surface of the substrate.

[0044] Furthermore, there is also a fourth electrode which forms an ohmic contact with the second semiconductor layer.

[0045] Furthermore, there is also a second insulating layer formed on the fourth semiconductor layer and below the second electrode.

[0046] Furthermore, there is also a buffer layer formed on the nucleation layer.

[0047] Further, the second semiconductor layer includes at least two sub-layers, wherein the first sub-layer has a weak P-type doping concentration relative to the second sub-layer, and the second sub-layer has a strong P-type doping concentration relative to the first sub-layer;

[0048] A first electrode, a second electrode, and a third electrode are formed on the first surface of the fourth semiconductor layer.

[0049] Furthermore, the first sublayer is closer to the third electrode than the second sublayer.

[0050] Furthermore, the doping concentration of the second semiconductor layer is sufficient to deplete 95%-100% of the two-dimensional charge carrier gas in at least a portion of the area overlapping with the second electrode projection area in the absence of device bias.

[0051] Furthermore, when the bias voltage of the second electrode is 0, the two-dimensional charge carrier gas corresponding to at least a portion of the second electrode is less than 5E+11 / cm 2 .

[0052] Furthermore, the doping concentration of the second semiconductor layer is uniform, or the doping concentration of the second semiconductor layer decreases gradually or in steps along the direction from the second electrode to the third electrode; or the doping concentrations of the first sublayer and the second sublayer are respectively uniform, or the doping concentrations of the first sublayer and the second sublayer decrease gradually or in steps along the direction from the second electrode to the third electrode.

[0053] The present application also provides a method for manufacturing a semiconductor device, comprising:

[0054] Step 100: providing a silicon substrate;

[0055] Step 200: forming a first insulating layer on a first surface of the silicon substrate;

[0056] Step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate;

[0057] Step 400: etching the exposed silicon substrate to form a groove on the silicon substrate;

[0058] Step 500: depositing a nucleation material to fill the groove to form a nucleation layer;

[0059] Step 600: Taking the nucleation layer as the nucleation center, epitaxially growing a first semiconductor layer, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;

[0060] Step 700: Taking the first semiconductor layer as the nucleation center, P- impurities are doped in lateral epitaxy to form a second semiconductor material layer;

[0061] Step 800: Continue to laterally epitaxially grow the third semiconductor material layer, remove the second and third semiconductor material layers on the first surface of the first semiconductor layer, and form a second semiconductor layer and a third semiconductor layer;

[0062] Step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at the interface between the fourth semiconductor layer and the first to third semiconductor layers.

[0063] Furthermore, the angle is between 30-75 degrees.

[0064] Furthermore, the doping concentration of the P-impurity is 1E17-5E19 / cm 3 .

[0065] Furthermore, step 1000 is also included: through a doping process, an N+ doped first region and a second region are formed, which form an ohmic contact with the two-dimensional charge carrier gas, and then a first electrode and a third electrode are respectively formed on the fourth semiconductor layer corresponding to the first and second regions, and a second electrode is formed between the first electrode and the third electrode.

[0066] Furthermore, the range of the first end of the second semiconductor layer projected to the first surface of the substrate overlaps with the range of the second electrode projected to the first surface of the substrate; or the range of the first end of the second semiconductor layer projected to the substrate is within the range of the second electrode projected to the first surface of the substrate.

[0067] Furthermore, the range of the second end of the second semiconductor layer projected to the first surface of the substrate overlaps with the range of the first electrode projected to the first surface of the substrate; or the range of the second end of the second semiconductor layer projected to the first surface of the substrate is within the range of the first electrode projected to the first surface of the substrate.

[0068] Furthermore, the opening is formed at a position corresponding to where the third electrode is formed.

[0069] Furthermore, it also includes forming an insulating protection layer on the side walls of the groove and the opening and the bottom surface of the groove by a deposition process, and then removing the insulating protection layer on the bottom surface of the groove by anisotropic etching processes to expose the substrate.

[0070] Furthermore, in the growth atmosphere containing chlorine gas, the nucleation is performed by filling the AlN material so that the nucleation material AlN is almost not deposited on the first surface of the first insulating layer, and the nucleation layer is only formed at the opening and / or the groove.

[0071] Furthermore, the method further includes etching on the second surface of the substrate to form a through hole reaching the second portion of the second semiconductor layer, and depositing an electrode material in the through hole to form a fourth electrode.

[0072] Furthermore, the method further includes etching from the first surface of the fourth semiconductor layer to form a through hole directly reaching the second portion of the second semiconductor layer, and depositing an electrode material in the hole to form a fourth electrode.

[0073] Furthermore, the method further includes forming a second insulating material layer to fully cover the fourth semiconductor layer, or forming a second insulating material on the fourth semiconductor layer and then retaining the second insulating material at the second electrode region to form a second insulating material layer.

[0074] Furthermore, the method further includes depositing a buffer layer on the nucleation layer before forming the first semiconductor layer.

[0075] Furthermore, it also includes adjusting the doping dosage of P-type impurities introduced into the second surface and the third surface of the first semiconductor layer, and sequentially epitaxially forming a first sublayer with a weak P-type doping concentration and a second sublayer with a strong P-type doping concentration of the second semiconductor layer.

[0076] Furthermore, the doping concentration of the first sublayer is less than 5E18 / cm 3 ; The doping concentration of the second sublayer is 1E17-5E19 / cm 3 .

[0077] Furthermore, a first electrode, a second electrode and a third electrode are formed on the first surface of the fourth semiconductor layer, and the doping concentrations in the first sublayer and the second sublayer are uniform, or decrease gradually from the second electrode to the third electrode, or decrease in steps from the second electrode to the third electrode.

[0078] According to another aspect of the present disclosure, an electronic device is provided, which includes the semiconductor device in the present disclosure.

[0079] Furthermore, the electronic device is a power supply device, a mobile phone, or a power amplifier in a communication system.

[0080] The solution of the present disclosure can at least help achieve one of the following effects: the semiconductor device can reduce gate leakage current, has high threshold voltage, high power, and high reliability, can achieve low on-resistance and a normally-off state of the device, and can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer in use.

[0081] The structure and preparation process of the semiconductor device are relatively simple, and can effectively reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The specific contents of the present disclosure are described below with reference to the accompanying drawings, which will help to more easily understand the above and other purposes, features and advantages of the present disclosure. The accompanying drawings are only for illustrating the principles of the present disclosure. The sizes and relative positions of the units in the accompanying drawings are not necessarily drawn to scale. In the accompanying drawings:

[0083] Figure 1-2 A schematic cross-sectional view showing a structure of a semiconductor device according to a first embodiment;

[0084] Figure 3 A schematic cross-sectional view showing a structure of a semiconductor device according to a second embodiment;

[0085] Figure 4 A schematic cross-sectional view showing a structure of a semiconductor device according to a third embodiment;

[0086] Figure 5 A schematic cross-sectional view showing a structure of a semiconductor device according to a fourth embodiment;

[0087] Figure 6A schematic cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment;

[0088] Figure 7 A schematic cross-sectional view showing a structure of a semiconductor device according to a sixth embodiment;

[0089] Figure 8-Figure 15 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a seventh embodiment;

[0090] Figure 16-Figure 19 A schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an eighth embodiment. DETAILED DESCRIPTION

[0091] Exemplary disclosures of the present disclosure are described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of implementing the present disclosure are described in the specification. However, it should be understood that many decisions specific to the present disclosure may be made in the process of developing any such implementation of the present disclosure in order to achieve the developer's specific goals, and these decisions may vary from one disclosure to another.

[0092] It should also be noted here that in order to avoid obscuring the contents of the present disclosure due to unnecessary details, only device structures closely related to the solutions according to the contents of the present disclosure are shown in the drawings, while other details that are not closely related to the contents of the present disclosure are omitted.

[0093] It should be understood that the present disclosure is not limited to the described implementation forms due to the following description with reference to the accompanying drawings. Herein, where feasible, features between different embodiments may be replaced or borrowed, and one or more features may be omitted in one embodiment.

[0094] Specifically, the semiconductor device of the present disclosure is a compound semiconductor device including a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a transistor in which a nitride semiconductor material is used. Furthermore, the transistor is a GaN transistor including a GaN semiconductor material. In particular, the GaN transistor is a normally closed transistor GaN-HEMT.

[0095] First embodiment

[0096] Reference Figure 1-Figure 2 A semiconductor device according to a first embodiment will be described.

[0097] like Figure 1As shown, in the first embodiment, the semiconductor device, exemplarily such as a normally-off HEMT device, includes a substrate 100. The material of the substrate 100 can be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Optionally, the substrate 100 can be sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAl LiO, GaN, Al2O3 or single crystal silicon, etc.; further, the Al2O3 substrate can be Al2O3 with a (0001) plane; further, the single crystal silicon substrate can be a silicon substrate with a (111) plane. A first insulating layer 102 is provided on the first surface 1001 of the substrate 100. Exemplarily, the first insulating layer 102 is a SiO2 layer or a Si3N4 layer. The opening formed on the first insulating layer 102 exposes the substrate 100, and a nucleation layer 103 is formed on the substrate exposed by the opening. Optionally, the opening on the first insulating layer 102 is formed at a position corresponding to the subsequent formation of a source electrode or a drain electrode of the semiconductor device.

[0098] Preferably, when the opening on the first insulating layer 102 is formed at a position corresponding to the subsequent formation of a drain electrode of the semiconductor device, a first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and on the first surface of the nucleation layer 103 .

[0099] Alternatives such as Figure 2 As shown, a nucleation layer 103' is formed on the first surface 1001 of the substrate 100 to fully cover it, and a first insulating layer 102 is formed on the nucleation layer 103'. Exemplarily, the first insulating layer 102 is a SiO2 layer or a Si3N4 layer. An opening is formed on the first insulating layer 102 to expose the nucleation layer 103'. A first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and the exposed first surface 1031' of the nucleation layer 103'. The first semiconductor layer 104 may be a nitride, such as an intrinsic GaN layer (i-GaN) or an unintentionally doped GaN layer. The GaN layer is parallel to the first surface 1001 of the substrate 100 and is approximately parallel to the

[0001] orientation in the epitaxial direction.

[0100] The second surface 1042 and the third surface 1043 of the first semiconductor layer 104 form an angle with the first surface 1021 of the first insulating layer 102. Optionally, the angle is between 30 and 75 degrees, so that the projections of the upper and lower ends on the insulating layer 102 are located in different areas.

[0101] A second semiconductor layer 105 is formed on the second surface 1042 and the third surface 1043 of the first semiconductor layer 104. Exemplarily, the second semiconductor layer 105 is a P-type buried layer, and the doping concentration of the P-type buried layer is exemplarily 1E17-5E19 / cm 3 Furthermore, the second semiconductor layer 105 is a P-type doped GaN layer.

[0102] A third semiconductor layer 106 is formed on the second surface 1052 and the third surface 1053 of the second semiconductor layer 105. The first surface 1041 of the first semiconductor layer 104, the first surface 1051 of the second semiconductor layer 105, and the first surface 1061 of the third semiconductor layer 106 are approximately on the same plane. The materials of the first semiconductor layer 104 and the third semiconductor layer 106 may be the same or different.

[0103] A fourth semiconductor layer 107 is formed on the first semiconductor layer 104, the second semiconductor layer 105 and the third semiconductor layer 106. Optionally, the fourth semiconductor layer 107 may be AlGaN, InAlGaN, InAlN layer, etc. The first semiconductor layer 104, the second semiconductor layer 105 and the third semiconductor layer 106 have a smaller bandgap than the fourth semiconductor layer 107, so that a two-dimensional charge carrier gas, such as a two-dimensional electron gas 2DEG, is formed between the fourth semiconductor layer 107 and the interface of the first semiconductor layer 104, the second semiconductor layer 105 and the third semiconductor layer 106.

[0104] A second electrode 202 is formed on the first surface 1051 of the second semiconductor layer 105 and the first surface 1071 of the fourth semiconductor 107 corresponding to the fourth semiconductor 107, and the second electrode 202 is a gate electrode. The gate electrode forms a Schottky contact with the fourth semiconductor layer 107 to reduce off-state leakage current. Optionally, the range of the first end of the second semiconductor layer 105 away from the first surface 1001 of the substrate projected onto the first surface 1001 of the substrate overlaps with the range of the second electrode 202 projected onto the substrate. Preferably, the range of the first end of the second semiconductor layer 105 projected onto the first surface 1001 of the substrate may be located within the range of the second electrode 202 projected onto the substrate.

[0105] The second semiconductor layer 105 can be formed into a very thin layer by precisely controlling the process parameters such as the epitaxial time during the lateral epitaxy. Since the resistance of the depletion region is usually relatively high, reducing the width of this part can effectively reduce the on-state resistance of the device, and is also conducive to reducing the size of the device and improving the area utilization of the wafer.

[0106] The configuration of the second semiconductor layer 105, such as its thickness, length, width, and the amount of P-type doping concentration, can be specifically configured through device parameters. Exemplarily, the two-dimensional charge carrier gas at the interface between the second semiconductor layer 105 and the fourth semiconductor 107 can be less than 5E11 / cm2 when the gate bias is 0. It should be understood that the second semiconductor layer 105 only depletes the two-dimensional charge carrier gas in the partial area where the projection of the second electrode 202 overlaps, and does not deplete the two-dimensional charge carrier gas in other areas. This results in the device having a higher threshold voltage, a lower on-resistance, and a normally closed state of the device, which results in the device having good switching characteristics.

[0107] A first electrode 201 and a third electrode 203 are formed on the fourth semiconductor layer 107. The materials of the first and third electrodes may be TiN, Ni, ITO, Au, etc. The first electrode 201 may be a source electrode, which forms an ohmic contact with the two-dimensional charge carrier gas. The second electrode 203 may be a drain electrode, which forms an ohmic contact with the two-dimensional charge carrier gas. The range of the second end of the second semiconductor layer 105 close to the first surface 1001 of the substrate projected to the first surface 1001 of the substrate may be within the range of the first electrode projected to the substrate; or the range of the second end of the second semiconductor layer 105 projected to the first surface 1001 of the substrate overlaps with the range of the first electrode projected to the substrate.

[0108] In this embodiment, relative to the nucleation layer being formed at a position corresponding to the subsequent formation of the source electrode of the semiconductor device, it is preferred that the nucleation layer be formed at a position corresponding to the subsequent formation of the drain electrode of the semiconductor device. In this embodiment, the second surface 1042 and the third surface 1043 where the first semiconductor layer 104 intersects with the first surface 1021 of the first insulating layer 102 are inclined, thereby making the corresponding surface of the second semiconductor layer 105 also inclined. Through the specific projection relationship between the first electrode 201, the second electrode 202 and the end face of the second semiconductor layer 105 designed in this embodiment, the inclined second semiconductor layer 105 can be formed, and at the same time, the second semiconductor layer 105 can be used to better realize the normally-off semiconductor device and control the potential of the semiconductor device.

[0109] Second embodiment

[0110] like Figure 3 As shown in the second embodiment, the semiconductor device, exemplarily a normally-off HEMT

[0111] The device includes a silicon substrate 100. A first insulating layer 102 is formed on the first surface of the substrate 100, and the first insulating layer 102 is exemplarily a SiO2 layer or Si3N4. An opening is formed on the first insulating layer 102 at a position corresponding to a subsequent third electrode 203 or a position corresponding to a subsequent first electrode 201 to expose the substrate 100, preferably corresponding to the subsequent third electrode 203. Then the exposed substrate 100 is etched to form a groove with a depth of 0.2-10 microns on the substrate 100, and typically, the depth of the groove is about 1 micron. An insulating protection layer 1003 is formed on both side walls of the groove of the substrate 100 and the opening of the first insulating layer 102, such as an SiO2 insulating protection layer. A nucleation layer 103 is formed on the substrate exposed at the bottom of the groove. The material of the nucleation layer 103 is AlN. A first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and on the first surface of the nucleation layer 103. The second surface and the third surface of the first semiconductor layer 104 form an angle with the first surface of the first insulating layer 102. Optionally, the angle is between 30 and 75 degrees. Other structural features are the same as those of the first embodiment and are not described here.

[0112] In this embodiment, the arrangement of the trench on the substrate 100 can increase the distance between the third electrode and the substrate 100, effectively reducing leakage current. In addition, the arrangement of the insulating protection layer on both side walls of the trench can further reduce leakage current.

[0113] Third embodiment

[0114] See also Figure 4 , based on the first or second embodiment, further comprising a fourth electrode 204, wherein the fourth electrode 204 is a body electrode, and forms an ohmic contact with the second end of the second semiconductor layer 105 to control the potential of the semiconductor device. The fourth electrode 204 may be an independent electrode to independently control the potential; or the fourth electrode 204 may be connected to the first electrode 201.

[0115] Fourth Implementation Method

[0116] See also Figure 5 On the basis of the first to third embodiments, a second insulating layer 108 is formed under the second electrode 202. The second insulating layer 108 is used to reduce gate leakage current.

[0117] Fifth Implementation Method

[0118] See also Figure 6On the basis of the first embodiment or the second embodiment, before forming the first semiconductor layer, a buffer layer 300 is formed on the nucleation layer to improve crystal quality and reduce leakage current between the third electrode and the substrate.

[0119] Sixth Implementation Method

[0120] See also Figure 7 , based on the first embodiment or the second embodiment, the second semiconductor layer 105 can be divided into at least two sublayers. The first sublayer 1055 has a lower P-type doping concentration relative to the second sublayer 1056, and its specific doping concentration is based on the design of specific device parameters, so that it is not enough to completely deplete the two-dimensional electrons in the channel without device bias, and is exemplarily <5E18 / CM3. The second sublayer 1056 has a higher P-type doping concentration relative to the first sublayer 1055, and the specific doping concentration of the second sublayer is based on the design of specific device parameters, so that it is enough to basically completely deplete the two-dimensional charge carrier gas projected with the second electrode without device bias, and is exemplarily 1E17-5E19 / CM3. Preferably, the first sublayer is closer to the third electrode 203 than the second sublayer to adjust the electric field distribution. It can be understood that the number of the sublayers is not limited to two, and can be set to multiple.

[0121] Alternatively, the second semiconductor layer 105 may be a single semiconductor layer as described in Embodiment 1 and Embodiment 2, and its doping concentration presents a unilateral gradient decrease or a unilateral step decrease along the direction from the second electrode 202 to the third electrode 203. It is further understood that the doping concentrations of the first and second sub-layers may be uniform, or present a regular or irregular change along the direction from the second electrode 202 to the third electrode 203, such as a unilateral gradient decrease or a unilateral step decrease.

[0122] Seventh Implementation Plan

[0123] Now refer to Figure 8-15 A manufacturing method for manufacturing the semiconductor device of the first embodiment will be exemplarily described.

[0124] A substrate 100 is provided. The selection of the material of the substrate 100 refers to the description in the first embodiment and will not be repeated here. A first insulating layer 102 is formed on the first surface 1001 of the substrate 100. Optionally, the first insulating layer 102 is formed by a deposition process; optionally, when the substrate 100 is a silicon substrate and the first insulating layer 102 is a SiO2 layer, the first insulating layer 102 can be formed by an oxidation process. An opening is formed on the first insulating layer 102 to expose the substrate 100. The opening on the first insulating layer 102 can be formed at a position corresponding to the subsequent formation of the first electrode of the semiconductor device, or at a position where the third electrode is formed.

[0125] When the opening on the first insulating layer 102 is formed at a position corresponding to the formation of the first electrode of the subsequent semiconductor device, since the first electrode 201 (source electrode) is used as a reference point in the high electron mobility transistor, the high electron mobility transistor presents a symmetrical structure, that is, the first electrode 201 (source electrode) has a second electrode 202 (gate electrode) and a third electrode 203 (drain electrode) on both sides. The distance from the first electrode 201 (source electrode) to the second electrode 202 (gate electrode) is much smaller than the distance from the second electrode 202 (gate electrode) to the third electrode 203 (drain electrode). Therefore, it is conducive to the production of various fine and complex structures at the first electrode 201 and the second electrode 202 by epitaxy. At the same time, since the voltage of the first electrode region (source region) is very low, and the crystal quality of the nucleation layer region is poor, therefore, the nucleation layer is formed at the corresponding first electrode (source electrode) formation, and the influence can be minimized due to the low voltage of the source region.

[0126] When the opening on the first insulating layer 102 is formed at a position corresponding to the position where the third electrode 203 of the subsequent semiconductor device is to be formed, it is avoided that when the high electron mobility transistor realizes the P-type buried layer at the second electrode through lateral epitaxy from the first electrode region, and then controls the electric potential of the P-type buried layer, it is necessary to extend the P-type buried layer to the position of the third electrode 203 (drain electrode) through a complex modulation doping lateral epitaxial structure, and realize ohmic contact and potential control of the P-type buried layer near the third electrode 203 (drain electrode), thereby reducing the complex structure of the device, reducing costs and simplifying the process.

[0127] Specifically, a nucleation layer 103 is formed on the substrate 100 exposed at the opening. The material of the nucleation layer can be selected as a material that can serve as the growth core of the first semiconductor layer 104. Exemplarily, on an Al2O3 substrate, gallium nitride can be used as a nucleation material. Due to its excellent selectivity, polycrystalline or amorphous gallium nitride can be decomposed at high temperature in a hydrogen atmosphere, so that the nucleation layer 103 can be selectively grown on the exposed Al2O3 substrate instead of growing on the first insulating layer 102. Exemplarily, on a silicon substrate, the material of the nucleation layer 103 can be AlN. Usually, after the nucleation material AlN is deposited on the first insulating layer 102 to fill the opening, the nucleation material AlN on the first surface 1021 of the first insulating layer 102 is removed by etching or grinding to form the nucleation layer 103 in the opening. Further, on the silicon substrate, the material of the nucleation layer 103 may be AlN, and under the assistance of the atmosphere containing chlorine gas, the nucleation material AlN has no obvious nitride growth on the first surface 1021 of the first insulating layer 102, or the nucleation material AlN is deposited very little on the first surface 1021 of the first insulating layer 102, and the nucleation layer 103 is formed only at the opening. Therefore, it is unnecessary to perform the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102, thereby saving process costs. Further, on the silicon substrate, the material of the nucleation layer 103 may be AlN, and the AlN layer formed by the nucleation material AlN on the first surface 1021 of the first insulating layer 102 is polycrystalline or amorphous through process adjustment, and the nucleation layer formed by the nucleation material on the substrate surface at the opening is single crystal AlN. Therefore, in the subsequent lateral epitaxy, the first semiconductor layer 103 can be nucleated and grown only from the nucleation layer of the opening instead of growing on the polycrystalline or amorphous AlN layer on the insulating layer, so that the polycrystalline AlN or amorphous layer also plays an insulating role, and there is no need to perform the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102, thereby saving process costs.

[0128] Alternatively, a nucleation layer 103' is formed to fully cover the first surface 101 of the substrate 100, and a first insulating layer 102 is deposited on the nucleation layer 103'. An opening is formed on the first insulating layer 102 to expose the nucleation layer 103'.

[0129] A first semiconductor layer 104 (e.g., an intrinsic i-GaN or unintentionally doped GaN layer) is formed on the first surface of the first insulating layer 102 and the first surface of the exposed nucleation layer 103' by lateral epitaxy. The second surface and the third surface of the first semiconductor layer 104 formed by lateral epitaxy are at an angle to the first surface of the first insulating layer 102. Optionally, the angle is between 30 and 90 degrees.

[0130] The second semiconductor layer is formed by doping P- impurities in a lateral epitaxial process on the second surface and the third surface of the first semiconductor layer 104. Exemplarily, the doping concentration of the second semiconductor layer is 1E17-5E19 / cm3.

[0131] The third semiconductor material is formed on the second semiconductor layer by lateral epitaxy through the lateral epitaxy process. The third semiconductor material covers the first to third surfaces of the second semiconductor layer. A portion of the third semiconductor material and the upper surface of the second semiconductor layer are removed to form the discrete third semiconductor layer 106 and the second semiconductor 105. Exemplarily, a portion of the third semiconductor material and the second semiconductor layer is removed by a grinding process until the first surface of the first semiconductor layer is exposed.

[0132] A fourth semiconductor layer 107 is formed on the third semiconductor layer 106. Optionally, the fourth semiconductor layer 107 is AlGaN, InAlGaN, InAlN, etc. The first semiconductor layer 104, the second semiconductor layer 105, and the third semiconductor 106 have a smaller bandgap than the fourth semiconductor layer 107, so that a two-dimensional charge carrier gas, such as 2DEG, is formed between the fourth semiconductor layer 107 and the first semiconductor layer 104-third semiconductor layer 106.

[0133] Exemplarily, by a doping process such as ion implantation, an N+ doped first region and a second region (source / drain region) are formed at corresponding positions, which form an ohmic contact with the two-dimensional charge carrier gas, and then a first electrode is formed on the first region by a process such as sputtering, evaporation, etc., and a third electrode is formed on the second region by a process such as sputtering, evaporation, etc. The first and third electrode materials can be TiN, Ni, ITO, Au, etc., and a second electrode is formed on the fourth semiconductor layer between the first and third electrodes.

[0134] Eighth Implementation Method

[0135] Now refer to Figure 16-19 A method for manufacturing the semiconductor device of the second embodiment will be exemplarily described.

[0136] A silicon substrate 100 is provided, and a first insulating layer 102 is formed on a first surface 1001 of the silicon substrate 100. Optionally, the first insulating layer 102 is formed by a deposition or oxidation process, etc.; an opening is formed on the first insulating layer 102 to expose a portion of the silicon substrate 100, and the silicon substrate 100 is etched through the opening to form a groove with a depth of 0.2-10 microns on the silicon substrate 100, and typically, the depth of the groove is 1 micron. Optionally, the opening on the first insulating layer 102 can be formed at a position corresponding to the subsequent formation of a third electrode of a semiconductor device. Optionally, the opening on the first insulating layer 102 can also be formed at a position corresponding to the subsequent formation of a first electrode of a semiconductor device. An insulating protective layer is formed on the sidewall and bottom surface of the groove by an oxidation or deposition process, for example, SiO2 or Si3N4. Then, the insulating protective layer on the bottom surface of the groove is removed by an anisotropic etching process to expose the silicon substrate 100. Optionally, AlN material is deposited on the substrate 100 exposed at the opening to fill the groove, so as to form a nucleation layer 103 in the opening. Further, AlN material can be deposited on the substrate 100 exposed at the opening to fill the opening in a growth atmosphere containing chlorine gas. In this case, the nucleation material AlN does not grow significantly on the first surface 1021 of the first insulating layer 102, or the nucleation material AlN is deposited very little on the first surface 1021 of the first insulating layer 102, and the nucleation layer 103 is formed only at the opening. Therefore, it is unnecessary to perform the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102, saving process costs. Further, the material of the nucleation layer 103 on the silicon substrate can be AlN, and the AlN layer formed by the nucleation material AlN on the first surface 1021 of the first insulating layer 102 is polycrystalline or amorphous, while the nucleation layer formed by the nucleation material on the substrate surface at the opening is single crystal AlN. Therefore, in the subsequent lateral epitaxy, the first semiconductor layer 103 can be nucleated and grown only from the nucleation layer of the opening instead of growing on the polycrystalline AlN layer on the insulating layer, so that the polycrystalline AlN layer also plays an insulating role, and there is no need to perform the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102, thereby saving process costs.

[0137] Alternatively, a nucleation layer 103' is formed to fully cover the first surface 101 of the substrate 100, and a first insulating layer 102 is deposited on the nucleation layer 103'. An opening is formed on the first insulating layer 102 to expose the nucleation layer 103'.

[0138] The subsequent formation methods of various structural features are carried out with reference to the seventh implementation scheme and will not be repeated here.

[0139] Ninth Implementation Plan

[0140] On the basis of the seventh and eighth embodiments, a through hole reaching the second portion of the second semiconductor layer 105 is formed by etching on the second surface of the substrate, and an electrode material is deposited in the hole to form a fourth electrode.

[0141] Alternatively, a through hole reaching the second portion of the second semiconductor layer 105 is formed by etching on the first surface of the fourth semiconductor layer 107, and an electrode material is deposited in the hole to form a fourth electrode.

[0142] It is understandable that the formation method of the fourth electrode is not limited thereto, and the fourth electrode may also be led out from the side of the second semiconductor layer 105 by etching and depositing a metal material.

[0143] Tenth Implementation Plan

[0144] On the basis of the seventh embodiment or the eighth embodiment, a second insulating material is formed on the fourth semiconductor layer 107 , and the second insulating material outside the subsequent second electrode 202 region is removed to form the second insulating layer 108 .

[0145] Eleventh Embodiment

[0146] Based on the seventh or eighth embodiment, before forming the first semiconductor layer, a buffer layer is deposited on the nucleation layer.

[0147] Twelfth Implementation Method

[0148] On the second surface 1042 and the third surface 1043 of the first semiconductor layer 104 formed in the first embodiment or the second embodiment, the concentration of the dopant is adjusted in the MOCVD epitaxial process to sequentially form a first sublayer 1055 of a second semiconductor layer 105 with a lower P-type doping concentration and a second sublayer 1056 of the second semiconductor layer 105 with a higher P-type doping concentration. Alternatively, the concentration of the dopant is adjusted in the MOCVD epitaxial process so that the doping concentration of the second semiconductor layer 105 decreases gradually along the direction from the second electrode 202 to the third electrode 203.

[0149] It is understandable that the sub-layers can be arranged as multiple layers rather than being limited to two layers by adjusting the concentration of dopants during the epitaxial growth process.

[0150] Furthermore, the doping concentration within a single sublayer can be set by adjusting the concentration of the dopant during the epitaxial process so that it is uniform, regular or irregular within a single sublayer along the direction from the second electrode 202 to the third electrode 203, such as a unilateral gradient decrease or a step change between each sublayer.

[0151] The manufacturing process of the remaining parts refers to the seventh or eighth implementation scheme and will not be described in detail here.

[0152] Thirteenth Implementation Plan

[0153] A power supply device includes any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, and a transformer, wherein both the primary circuit and the secondary circuit include a switching element, wherein the switching element adopts any one of the semiconductor devices in the above embodiments.

[0154] Fourteenth Implementation Plan

[0155] A mobile phone includes any one of the semiconductor devices in the above embodiments. The mobile phone includes a display screen, a charging unit, etc., wherein the charging unit includes any one of the semiconductor devices in the above embodiments.

[0156] Fifteenth Implementation Plan

[0157] An amplifier can be used as a power amplifier in the fields of mobile phone base stations, optical communication systems, etc. The power amplifier can include any one of the semiconductor devices in the above embodiments.

[0158] The present disclosure is described above in conjunction with specific implementation schemes, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present disclosure. Those skilled in the art can make various modifications and variations to the present disclosure based on the spirit and principles of the present disclosure, and these modifications and variations are also within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming an opening on the first insulating layer to expose a portion of the substrate; forming a groove on the substrate corresponding to the opening; forming a single crystal nucleation layer in the groove; forming a polycrystalline or amorphous nucleation material on the first insulating layer; Taking the single crystal nucleation layer as the nucleation center, a first semiconductor layer is grown laterally epitaxially.

2. A semiconductor device comprising: Silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming an opening on the first insulating layer to expose a portion of the substrate; a groove formed on the substrate corresponding to the opening; a single crystal nucleation layer formed in the groove; forming a polycrystalline or amorphous nucleation material on the first insulating layer; or no nucleation material is formed on the first insulating layer; Taking the single crystal nucleation layer as the nucleation center, epitaxially growing a first semiconductor layer laterally; The second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the second surface of the first semiconductor layer and the third surface; forming a third semiconductor layer on the second surface of the second semiconductor layer and on the third surface; A fourth semiconductor layer is formed on a first surface of the first semiconductor layer, a first surface of the second semiconductor layer, and a first surface of the third semiconductor layer. 3 . The semiconductor device of claim 2 , wherein a two-dimensional charge carrier gas is formed at interfaces between the fourth semiconductor layer and the first, second and third semiconductor layers.

4. The semiconductor device of claim 2, further comprising an unintentionally doped or low-doped fifth semiconductor layer between the fourth semiconductor layer and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, wherein a two-dimensional charge carrier gas is formed at an interface between the fourth semiconductor layer and the fifth semiconductor layer. 5 . The semiconductor device according to claim 2 , wherein a first electrode, a second electrode, and a third electrode are formed on the first surface of the fourth semiconductor layer. 6 . The semiconductor device according to claim 5 , further comprising a fourth electrode which forms an ohmic contact with the second semiconductor layer. 7 . The semiconductor device according to claim 6 , further comprising a second insulating layer formed on the fourth semiconductor layer and under the second electrode.

8. A method for manufacturing a semiconductor device, comprising: Step 100: providing a silicon substrate; Step 200: forming a first insulating layer on a first surface of the silicon substrate; Step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate; Step 400: etching the exposed silicon substrate to form a groove on the silicon substrate; Step 500: depositing a nucleation material to fill the groove to form a nucleation layer; Step 600: Taking the nucleation layer as the nucleation center, epitaxially growing a first semiconductor layer, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; Step 700: Taking the first semiconductor layer as the nucleation center, P- impurities are doped in lateral epitaxy to form a second semiconductor material layer; Step 800: Continue to laterally epitaxially grow the third semiconductor material layer, remove the second and third semiconductor material layers on the first surface of the first semiconductor layer, and form a second semiconductor layer and a third semiconductor layer; Step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at the interface between the fourth semiconductor layer and the first to third semiconductor layers.

9. The manufacturing method as described in claim 8 also includes step 1000: forming an N+ doped first region and a second region through a doping process, which form an ohmic contact with the two-dimensional charge carrier gas, and then forming a first electrode and a third electrode on the fourth semiconductor layer corresponding to the first and second regions, respectively, and forming a second electrode between the first electrode and the third electrode.

10. An electronic device comprising the semiconductor device according to any one of claims 1 to 7 or a semiconductor device obtained by the method for manufacturing a semiconductor device according to any one of claims 8 to 9.

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