Gallium nitride power device and manufacturing method thereof

Abstract

The invention discloses a gallium nitride power device and a manufacturing method thereof, and the device comprises a substrate on which a GaN buffer layer, an AlGaN layer and a P-GaN layer are sequentially formed; a source electrode is in direct contact with two-dimensional electron gas at the top of the GaN buffer layer to form first ohmic contact; the first part of the drain electrode is in direct contact with the two-dimensional electron gas at the top of the GaN buffer layer to form second ohmic contact, and the second part of the drain electrode is in contact with the P-GaN layer to form a hole injection structure. According to the gallium nitride power device and the manufacturing method thereof provided by the invention, the source electrode is directly contacted with the two-dimensional electron gas at the top of the GaN buffer layer to form the first ohmic contact, and the first part of the drain electrode is directly contacted with the two-dimensional electron gas at the top of the GaN buffer layer to form the second ohmic contact; and the second part of the drain electrode is in contact with the P-GaN layer to form a hole injection structure, and when the device is turned off, holes are injected into a channel region through the drain end P-GaN to be compounded with trapped electrons, so that the on-resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride power device and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN) materials have a series of material performance advantages such as large bandgap, high breakdown field strength, high polarization coefficient, high electron mobility and high electron saturation drift rate, and are the preferred materials for preparing a new generation of high-performance electronic power devices. As the industry's demand for low energy consumption, high efficiency and high power density of semiconductor devices becomes more and more significant, gallium nitride (GaN)-based gallium nitride power devices (such as field effect transistors and other switching devices) are gaining more and more attention.

[0003] In the prior art enhanced GaN HEMT devices, under large off-state stress, traps in the material interface or GaN buffer layer easily capture electrons. However, when the device is turned on, the trapped electrons cannot be released in time, so that the two-dimensional electron gas (2DEG) cannot be restored in time, resulting in an increase in the dynamic on-resistance RDSon and a decrease in the drain saturation current. In the process of turning on the GaN HEMT device, especially when a high voltage is applied between the source and the drain, the defect states near the channel (mainly the surface layer defects of the AlGaN material and the deep energy level defects of the GaN buffer layer crystal) easily capture electrons, which causes the formation of a negative charge region near the channel when the device is turned off, thereby changing the electric field distribution of the channel when the device is turned on, and disrupting the flow of the two-dimensional electron gas. The above may cause the "current collapse" phenomenon in gallium nitride power devices. Here, the current collapse phenomenon refers to the greatly increased on-resistance when the source and drain of the GaN HEMT device are subjected to high voltage. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] The present invention provides a gallium nitride power device, characterized by comprising:

[0006] A substrate, on which a GaN buffer layer, an AlGaN layer and a P-GaN layer are sequentially formed;

[0007] The source electrode is in direct contact with the two-dimensional electron gas on the top of the GaN buffer layer to form a first ohmic contact;

[0008] The first part of the drain electrode directly contacts the two-dimensional electron gas on the top of the GaN buffer layer to form a second ohmic contact, and the second part of the drain electrode contacts the P-GaN layer to form a hole injection structure.

[0009] Exemplarily, a first P-GaN layer is formed between the second portion of the drain electrode and the GaN buffer layer, and when the device is turned off and withstands voltage, the second portion of the drain electrode contacts the first P-GaN layer to form a hole injection structure;

[0010] A second P-GaN layer is formed between the gate and the GaN buffer layer.

[0011] Exemplarily, the hole injection structure includes a strip-shaped hole injection structure located on one side or both sides of the drain edge:

[0012] When the hole injection structure includes a strip-shaped hole injection structure located on one side of the drain edge, the strip-shaped hole injection structure is located on a side close to the source;

[0013] When the hole injection structure includes strip-shaped hole injection structures located at both sides of the edge of the drain electrode, the spacing between the strip-shaped hole injection structures is greater than 0.5 μm.

[0014] Exemplarily, the hole injection structure includes a plurality of island-shaped hole injection structures, and the plurality of island-shaped hole injection structures are located at the edge of the drain, or the plurality of island-shaped hole injection structures are located in a middle region of the drain.

[0015] Exemplarily, the drain electrode comprises a strip-shaped drain electrode, the plurality of island-shaped hole injection structures are arranged in sequence along an extension direction of the strip-shaped drain electrode, and in the extension direction of the strip-shaped drain electrode, a spacing between adjacent island-shaped hole injection structures is greater than 1 μm.

[0016] Exemplarily, the bottom of the source extends into the GaN buffer layer and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a first ohmic contact, the first part of the drain extends into the GaN buffer layer and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a second ohmic contact, and the depth range of the source and the drain extending into the GaN buffer layer includes 5nm to 60nm.

[0017] Exemplarily, the thickness of the first P-GaN layer ranges from 10 nm to 70 nm, the thickness of the second P-GaN layer is greater than the thickness of the first P-GaN layer, and the thickness of the second P-GaN layer ranges from 70 nm to 100 nm.

[0018] Exemplarily, the thickness of the AlGaN layer is less than the thickness of the P-GaN layer, and the thickness of the AlGaN layer ranges from 10 nm to 30 nm.

[0019] The present invention also provides a method for manufacturing a gallium nitride power device, comprising:

[0020] Providing a substrate, and sequentially forming a GaN buffer layer, an AlGaN layer, and a P-GaN layer on the substrate;

[0021] etching the P-GaN layer, the AlGaN layer, and the GaN buffer layer to form a first ohmic contact hole and a second ohmic contact hole in the GaN buffer layer;

[0022] forming a source electrode and a drain electrode, wherein the source electrode extends into the first ohmic contact hole, and a first portion of the drain electrode extends into the second ohmic contact hole;

[0023] Wherein, the second portion of the drain electrode contacts the P-GaN layer to form a hole injection structure.

[0024] Exemplarily, etching the P-GaN layer, the AlGaN layer, and the GaN buffer layer to form a first ohmic contact hole and a second ohmic contact hole in the GaN buffer layer includes:

[0025] Etching the P-GaN layer to form a first P-GaN layer located in the drain region and a second P-GaN layer located in the gate region;

[0026] forming a patterned mask layer on the AlGaN layer, wherein the patterned mask layer exposes a source region and a drain region;

[0027] The first P-GaN layer, the AlGaN layer, and the GaN buffer layer are etched until the etching depth of the GaN buffer layer reaches 5 nm to 60 nm.

[0028] According to the gallium nitride power device and the manufacturing method thereof provided by the present invention, the source electrode is directly in contact with the two-dimensional electron gas at the top of the GaN buffer layer to form a first ohmic contact, the first part of the drain electrode is directly in contact with the two-dimensional electron gas at the top of the GaN buffer layer to form a second ohmic contact, and the second part of the drain electrode is in contact with the P-GaN layer to form a hole injection structure. When the device is turned off, holes are injected into the channel region through the drain end P-GaN and recombine with the captured electrons to reduce the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0030] In the attached figure:

[0031] Figure 1 is a flow chart of a method for manufacturing a gallium nitride power device according to an embodiment of the present invention;

[0032] Figures 2A-2D A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for manufacturing a gallium nitride power device according to an embodiment of the present invention;

[0033] Figure 2E , 2F A bottom view schematically shows a hole injection structure of a gallium nitride power device according to an embodiment of the present invention;

[0034] Figures 3A-3D A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for manufacturing a gallium nitride power device according to another embodiment of the present invention;

[0035] Figure 3E FIG. 1 is a bottom view schematically showing a hole injection structure of a gallium nitride power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0037] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0042] In view of the above problems, the present invention provides a method for manufacturing a gallium nitride power device, such as Figure 1 As shown, the following steps are included:

[0043] Step S110: providing a substrate, and sequentially forming a GaN buffer layer, an AlGaN layer, and a P-GaN layer on the substrate;

[0044] Step S120: etching the P-GaN layer, the AlGaN layer and the GaN buffer layer to form a first ohmic contact hole and a second ohmic contact hole in the GaN buffer layer;

[0045] Step S130: forming a source and a drain, wherein the source extends into the first ohmic contact hole, and the first portion of the drain extends into the second ohmic contact hole; wherein the second portion of the drain contacts the P-GaN layer to form a hole injection structure.

[0046] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0047] Below, reference FIG. 2A to FIG. 2F , FIG. 3A to FIG. 3E The manufacturing method of the gallium nitride power device of the present invention is described in detail, wherein 2A to Figure 2D , FIG. 3A to FIG. 3D The cross-sectional view of the waveguide structure obtained by sequentially implementing the method for manufacturing the gallium nitride power device according to the embodiment of the present invention is shown. Figure 2E , Figure 2F and Figure 3E A top view of a gallium nitride power device according to an embodiment of the present invention is shown.

[0048] Exemplarily, the method for manufacturing a gallium nitride power device of the present invention comprises the following steps:

[0049] First, execute step S110, such as Figure 2A and 3A As shown, a substrate 110 is provided, and a GaN buffer layer 120 , an AlGaN layer 130 , and a P-GaN layer 140 are sequentially formed on the substrate.

[0050] In one embodiment, the substrate 110 may be any suitable semiconductor substrate, such as a bulk silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (DSP), or may be ceramic substrates such as alumina, quartz (e.g., sapphire) or glass substrates, or may be self-supporting substrates, which are not limited in the present application.

[0051] In one embodiment, the formation process of the GaN buffer layer 120, the AlGaN layer 130 and the P-GaN layer 140 can adopt any existing technology known to those skilled in the art, preferably chemical vapor deposition (CVD), such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD). Specifically, the GaN buffer layer 120 is an i-GaN layer. The thickness of the P-GaN layer 140 is 70nm to 100nm.

[0052] Next, step S120 is performed, such as Figure 2A-2B , Figure 3A-3B As shown, the P-GaN layer 140 , the AlGaN layer 130 , and the GaN buffer layer 120 are etched to form a first ohmic contact hole 150 and a second ohmic contact hole 160 in the GaN buffer layer 120 .

[0053] In one embodiment, a mask layer (not shown) is first formed on the P-GaN layer 140 and patterned, and then the P-GaN layer 140 is etched using the patterned mask layer as a mask to form a first P-GaN layer located in the drain region and a second P-GaN layer located in the gate region. At this time, the thickness of the first P-GaN layer and the second P-GaN layer are consistent, both of which are 70nm to 100nm. Figure 2A and Figure 3A Next, a patterned mask layer 101 is formed on the AlGaN layer 130, and the patterned mask layer 101 exposes the source region and the drain region. Next, as Figure 2B and Figure 3BAs shown, the first P-GaN layer (i.e., the P-GAN layer for forming a hole injection structure), the exposed AlGaN layer and the GaN buffer layer thereunder are simultaneously etched with the patterned mask layer 101 as a mask until the etching depth of the GaN buffer layer 120 reaches 5nm to 60nm, so as to form a first ohmic contact hole 150 and a second ohmic contact hole 160 in the GaN buffer layer 120, wherein the first ohmic contact hole 150 is used to form a source electrode in a subsequent step, and the second ohmic contact hole 160 is used to form a drain electrode in a subsequent step, Figure 2B In the example shown, the second ohmic contact hole 160 includes a contact hole. Figure 3B In the example shown, the second ohmic contact hole 160 includes two contact holes.

[0054] exist Figure 2B and Figure 3B In the etching process shown, since the thickness of the AlGaN layer 130 is less than the thickness of the P-GaN layer 140, when the first P-GAN is etched and thinned, not only the exposed AlGaN layer is completely removed, but also a portion of the GaN buffer layer thereunder is removed. Specifically, the thickness of the first P-GAN layer is thinned from 70nm to 100nm to 10nm to 70nm, the exposed AlGaN layer (thickness 10nm to 30nm) is completely removed, and the etching depth of the GaN buffer layer thereunder reaches 5nm to 60nm.

[0055] By setting a P-GaN layer of appropriate thickness between the drain and the GaN buffer layer, it is ensured that the two-dimensional electron gas below the hole injection structure will not be affected, and therefore will not affect the on-resistance of the device in the on state. By making the drain contact the P-GaN layer to form a hole injection structure, holes are injected under the extremely high field of the drain and recombine with the trapped electrons in the active area, thereby solving the problem of increased dynamic on-resistance and optimizing the dynamic resistance.

[0056] Next, step S130 is performed to form a source 170 and a drain 180, wherein the source 170 extends into the first ohmic contact hole 150, and the first portion of the drain 180 extends into the second ohmic contact hole 160; wherein the second portion of the drain 180 contacts the P-GaN layer to form a hole injection structure.

[0057] In one embodiment, Figure 2C and 3CAs shown, a metal layer is formed on the epitaxial wafer formed in the above step S120 to fill the first ohmic contact hole 150 and the second ohmic contact hole 160, respectively serving as the source 170 and the drain 180. The metal layer can be formed by any prior art known to those skilled in the art, such as physical vapor deposition (PVD) (e.g., evaporation, sputtering), chemical vapor deposition (CVD), or selective epitaxial growth (SEG), and the present invention is not limited thereto.

[0058] Next, if Figure 2D and 3D As shown, the patterned mask layer 101 is removed and a gate 190 is formed. It should be noted that, in this embodiment, the formation of the gate 190 is asynchronous with the formation of the source 170 and the drain 180, however, the formation of the gate 190 may also be synchronous with the formation of the source 170 and the drain 180, and the present invention is not limited thereto.

[0059] In one embodiment, a top view of a gallium nitride power device formed by the above steps is as follows: Figure 2E As shown, the drain is a strip drain, and the hole injection structure includes strip hole injection structures located on both sides of the drain edge, and the extension direction of the strip hole injection structure is consistent with the extension direction of the strip drain. Further, the spacing between the two strip hole injection structures is greater than 0.5μm. It should be noted that the hole injection structure can also include a strip hole injection structure located only on one side of the drain edge. When there is only one conditional structure, the strip hole injection structure is located on the side close to the source.

[0060] By forming a strip-shaped hole injection structure on both sides of the edge of the metal strip-shaped drain, the manufacturing process steps are simple, which is conducive to the injection of holes into the channel when the device is turned on, alleviates the current collapse effect, and takes into account both performance and manufacturing cost.

[0061] In one embodiment, a top view of a gallium nitride power device formed by the above steps is as follows: Figure 2F As shown, the drain is a strip drain, and the hole injection structure includes a plurality of island hole injection structures located at the edge of the drain. The arrangement of the island hole injection structures is similar to that of the above-mentioned strip hole injection structures, and the extension direction is consistent with the extension direction of the strip drain. The island hole injection structures can be located on both sides of the drain edge or on one side close to the drain. In the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 1 μm, and in the orthogonal direction of the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 0.5 μm.

[0062] In one embodiment, a top view of a gallium nitride power device formed by the above steps is as follows: Figure 3EAs shown, the drain is a strip drain, and the hole injection structure includes a plurality of island hole injection structures located in the middle region of the drain. The extension direction of the island hole injection structure is consistent with the extension direction of the strip drain. In the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 1 μm. In the orthogonal direction of the extension direction of the strip drain, the distance from the island hole injection structure to the edge of the drain is greater than 0.5 μm.

[0063] The key steps of the method for manufacturing the gallium nitride power device of the present invention have been introduced so far. For the complete device preparation, multiple other process steps may be required, which will not be described one by one here.

[0064] The present invention also provides a gallium nitride power device, the cross-sectional view of which is as follows Figure 2D Or 3D, the top view is as follows Figure 2E , 2F or as shown in 3E, including:

[0065] A substrate 110 , on which a GaN buffer layer 120 , an AlGaN layer 130 , and a P-GaN layer 140 are sequentially formed;

[0066] The source electrode 170 is in direct contact with the two-dimensional electron gas on the top of the GaN buffer layer 120 to form a first ohmic contact;

[0067] The first portion of the drain electrode 180 is in direct contact with the two-dimensional electron gas on the top of the GaN buffer layer to form a second ohmic contact, and a hole injection structure is formed between the second portion of the drain electrode 180 and the GaN buffer layer.

[0068] In one embodiment, the substrate 110 may be any suitable semiconductor substrate, such as a bulk silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (DSP), or may be ceramic substrates such as alumina, quartz (e.g., sapphire) or glass substrates, or may be self-supporting substrates, which are not limited in the present application.

[0069] In one embodiment, the GaN buffer layer 120 is an i-GaN layer.

[0070] Exemplarily, the bottom of the source 170 extends into the GaN buffer layer 120 and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a first ohmic contact, the first portion of the drain 180 extends into the GaN buffer layer 120 and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a second ohmic contact, and the source 170 and the drain 180 extend into the GaN buffer layer 120 to a depth range of 5nm to 60nm.

[0071] Exemplarily, a first P-GaN layer is formed between the second portion of the drain 180 and the GaN buffer layer, and when the device is turned off and withstands voltage, the first P-GaN layer serves as the hole injection structure; a second P-GaN layer is formed between the gate 190 and the GaN buffer layer.

[0072] In one embodiment, the thickness of the first P-GaN layer ranges from 10nm to 70nm, the thickness of the second P-GaN layer is greater than the thickness of the first P-GaN layer, and the thickness of the second P-GaN layer ranges from 70nm to 100nm. At the drain, the thinner P-GaN layer does not lead to depletion of the two-dimensional electron gas, ensuring an ideal Rc contact resistance of the drain.

[0073] By setting a P-GaN layer between the drain and the GaN buffer layer, it is ensured that the two-dimensional electron gas below the hole injection structure will not be affected, and therefore will not affect the on-resistance of the device in the on state. By making the drain contact the P-GaN layer to form a hole injection structure, holes are injected under the extremely high field of the drain and recombine with the trapped electrons in the active area, thereby solving the problem of increased dynamic on-resistance and optimizing the dynamic resistance.

[0074] In one embodiment, the thickness of the AlGaN layer 130 is less than the thickness of the P-GaN layer 140. Specifically, the thickness of the AlGaN layer ranges from 10 nm to 30 nm, so as to ensure that when etching and thinning the first P-GaN, not only the exposed AlGaN layer but also a portion of the GaN buffer layer thereunder is completely removed.

[0075] Exemplarily, the hole injection structure includes a strip hole injection structure located on one side or both sides of the drain edge: when the hole injection structure includes a strip hole injection structure located on one side of the drain edge, the strip hole injection structure is located on the side close to the source; when the hole injection structure includes a strip hole injection structure located on both sides of the drain edge, the spacing between the strip hole injection structures is greater than 0.5μm.

[0076] In one embodiment, Figure 2EAs shown, the drain is a strip-shaped drain, and the hole injection structure includes strip-shaped hole injection structures located on both sides of the drain edge, and the extension direction of the strip-shaped hole injection structure is consistent with the extension direction of the strip-shaped drain. Further, the spacing between the two strip-shaped hole injection structures is greater than 0.5 μm. It should be noted that the hole injection structure may also include a strip-shaped hole injection structure located only on one side of the drain edge, and when there is only one strip-shaped structure, the strip-shaped hole injection structure is located on the side close to the source.

[0077] By forming a strip-shaped hole injection structure on both sides of the edge of the metal strip-shaped drain, the manufacturing process steps are simple, which is conducive to the injection of holes into the channel when the device is turned on, alleviates the current collapse effect, and takes into account both performance and manufacturing cost.

[0078] Exemplarily, the hole injection structure includes a plurality of island-shaped hole injection structures, and the plurality of island-shaped hole injection structures are located at the edge of the drain, or the plurality of island-shaped hole injection structures are located in a middle region of the drain.

[0079] In one embodiment, Figure 2F As shown, the drain is a strip drain, and the hole injection structure includes a plurality of island hole injection structures located at the edge of the drain. The arrangement of the island hole injection structures is similar to that of the above-mentioned strip hole injection structures, and the extension direction is consistent with the extension direction of the strip drain. The island hole injection structures can be located on both sides of the drain edge or on one side close to the drain. In the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 1 μm, and in the orthogonal direction of the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 0.5 μm.

[0080] In one embodiment, Figure 3E As shown, the drain is a strip drain, and the hole injection structure includes a plurality of island hole injection structures located in the middle region of the drain. The extension direction of the island hole injection structure is consistent with the extension direction of the strip drain. In the extension direction of the strip drain, the spacing between adjacent island hole injection structures is greater than 1 μm. In the orthogonal direction of the extension direction of the strip drain, the distance from the island hole injection structure to the edge of the drain is greater than 0.5 μm.

[0081] According to the gallium nitride power device and the manufacturing method thereof provided by the present invention, a first ohmic contact is formed by making the source electrode directly contact with the two-dimensional electron gas at the top of the GaN buffer layer, a second ohmic contact is formed by making the first part of the drain electrode directly contact with the two-dimensional electron gas at the top of the GaN buffer layer, and a hole injection structure is formed between the second part of the drain electrode and the GaN buffer layer. When the device is turned off, holes are injected into the channel region through the drain end P-GaN and recombine with the captured electrons to reduce the on-resistance.

[0082] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A gallium nitride power device, characterized in that: include: A substrate, on which a GaN buffer layer, an AlGaN layer and a P-GaN layer are sequentially formed; The source electrode is in direct contact with the two-dimensional electron gas on the top of the GaN buffer layer to form a first ohmic contact; The first part of the drain electrode directly contacts the two-dimensional electron gas on the top of the GaN buffer layer to form a second ohmic contact, and the second part of the drain electrode contacts the P-GaN layer to form a hole injection structure.

2. The gallium nitride power device according to claim 1, characterized in that: A first P-GaN layer is formed between the second portion of the drain electrode and the GaN buffer layer, and when the device is turned off and withstands voltage, the second portion of the drain electrode contacts the first P-GaN layer to form a hole injection structure; A second P-GaN layer is formed between the gate and the GaN buffer layer.

3. The gallium nitride power device according to claim 1, characterized in that: The hole injection structure includes a strip-shaped hole injection structure located on one side or both sides of the drain edge: When the hole injection structure includes a strip-shaped hole injection structure located on one side of the drain edge, the strip-shaped hole injection structure is located on a side close to the source; When the hole injection structure includes strip-shaped hole injection structures located at both sides of the edge of the drain electrode, the spacing between the strip-shaped hole injection structures is greater than 0.5 μm.

4. The gallium nitride power device according to claim 1, characterized in that: The hole injection structure includes a plurality of island-shaped hole injection structures, and the plurality of island-shaped hole injection structures are located at the edge of the drain electrode, or the plurality of island-shaped hole injection structures are located in the middle area of ​​the drain electrode.

5. The gallium nitride power device according to claim 4, characterized in that: The drain electrode comprises a strip-shaped drain electrode, and the plurality of island-shaped hole injection structures are arranged in sequence along an extension direction of the strip-shaped drain electrode. In the extension direction of the strip-shaped drain electrode, a distance between adjacent island-shaped hole injection structures is greater than 1 μm.

6. The gallium nitride power device according to claim 1, characterized in that: The bottom of the source electrode extends into the GaN buffer layer and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a first ohmic contact. The first part of the drain electrode extends into the GaN buffer layer and directly contacts the two-dimensional electron gas at the top of the GaN buffer layer to form a second ohmic contact. The depth range of the source electrode and the drain electrode extending into the GaN buffer layer includes 5nm to 60nm.

7. The gallium nitride power device according to claim 2, characterized in that: The thickness of the first P-GaN layer ranges from 10 nm to 70 nm, the thickness of the second P-GaN layer is greater than that of the first P-GaN layer, and the thickness of the second P-GaN layer ranges from 70 nm to 100 nm.

8. The gallium nitride power device according to claim 7, characterized in that: The thickness of the AlGaN layer is smaller than that of the P-GaN layer, and the thickness of the AlGaN layer ranges from 10 nm to 30 nm.

9. A method for manufacturing a gallium nitride power device, characterized in that: include: Providing a substrate, and sequentially forming a GaN buffer layer, an AlGaN layer, and a P-GaN layer on the substrate; etching the P-GaN layer, the AlGaN layer, and the GaN buffer layer to form a first ohmic contact hole and a second ohmic contact hole in the GaN buffer layer; forming a source electrode and a drain electrode, wherein the source electrode extends into the first ohmic contact hole, and a first portion of the drain electrode extends into the second ohmic contact hole; Wherein, the second portion of the drain electrode contacts the P-GaN layer to form a hole injection structure.

10. The method for manufacturing a gallium nitride power device according to claim 9, wherein: Etching the P-GaN layer, the AlGaN layer, and the GaN buffer layer to form a first ohmic contact hole and a second ohmic contact hole in the GaN buffer layer includes: Etching the P-GaN layer to form a first P-GaN layer located in the drain region and a second P-GaN layer located in the gate region; forming a patterned mask layer on the AlGaN layer, wherein the patterned mask layer exposes a source region and a drain region; The first P-GaN layer, the AlGaN layer, and the GaN buffer layer are etched until the etching depth of the GaN buffer layer reaches 5 nm to 60 nm.

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