Silicon-based heterogeneous device monolithic integration method and silicon-based heterogeneous device monolithic

Abstract

The invention relates to the technical field of semiconductor device preparation, and discloses a silicon-based heterogeneous device monolithic integration method and a silicon-based heterogeneous device monolithic, and the method comprises the steps: depositing a dielectric material on the surface of a silicon substrate, forming an isolation groove above an N well and a P well, and forming an epitaxial lamination in the groove; depositing a hard mask layer and carrying out graphical process treatment, forming a reserved mask layer above the epitaxial lamination layer, and then preparing two different types of vertical devices in the isolation groove; depositing a dielectric material in the isolation groove, and exposing the surface of the vertical device in an external environment by adopting a sinking process; hKMG deposition and graphical process processing are carried out on the surface of the vertical device to form a high-K metal gate, then interlayer dielectric deposition is carried out to form an interlayer dielectric layer, through hole etching is carried out on the interlayer dielectric layer, and conductive metal is filled to form a silicon-based heterogeneous device single chip. According to the method, high-density integration of different types of vertical devices is realized, and the performance, the reliability and the integration degree of the device are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a silicon-based heterogeneous device monolithic integration method and a silicon-based heterogeneous device monolithic chip. Background Art

[0002] As the size of various electronic devices continues to shrink and gradually approach physical limits, the integration density is also increasing. However, high integration will lead to interconnection delays and increased power consumption, making the manufacturing process more complicated and expensive.

[0003] Specifically, the integration of transistors made of multiple different materials faces problems such as poor material compatibility, high process complexity, and difficulty in performance optimization, which lead to interface defects and stress problems, affecting the overall performance and reliability of the device, and further limiting the development of high-performance, high-integration integrated circuits. Summary of the invention

[0004] In view of this, the present application provides a silicon-based heterogeneous device monolithic integration method and a silicon-based heterogeneous device monolithic chip, the main purpose of which is to solve the technical problems in the prior art that heterogeneous integrated materials of different devices have poor compatibility, complex preparation process and low performance.

[0005] The present invention provides a method for monolithic integration of silicon-based heterogeneous devices, comprising:

[0006] Depositing a dielectric material on the surface of a silicon substrate, opening isolation grooves above an N-well and a P-well of the silicon substrate respectively, and forming an epitaxial stack in the isolation grooves;

[0007] Depositing a hard mask layer on the epitaxial stack and patterning the hard mask layer to form a reserved mask layer on the epitaxial stack, and preparing two different types of vertical devices in isolation grooves corresponding to the N-well and the P-well of the silicon substrate based on the epitaxial stack and the reserved mask layer;

[0008] Depositing a dielectric material in the isolation groove, using a recess process to make the dielectric material lower than the height of the vertical device, and exposing the surface of the vertical device to the external environment;

[0009] HKMG deposition and patterning process are performed on the surfaces of the two different types of vertical devices to form a high-K metal gate, interlayer dielectric deposition is performed on the high-K metal gate to form an interlayer dielectric layer, and through-holes are etched on the interlayer dielectric layer based on a preset layout position and filled with conductive metal to form a silicon-based heterogeneous device monolithic chip.

[0010] Optionally, before depositing the dielectric material on the surface of the silicon substrate, the method includes:

[0011] A well region is formed on the surface of a silicon substrate by using an ion implantation process, wherein the well region includes an N-well and a P-well.

[0012] Optionally, the step of depositing a dielectric material on a surface of a silicon substrate, opening isolation trenches above an N-well and a P-well of the silicon substrate, and forming an epitaxial stack in the isolation trenches comprises:

[0013] Depositing a first dielectric material on a surface of a silicon substrate, opening a first isolation trench above an N-well of the silicon substrate, and forming a first epitaxial stack in the first isolation trench;

[0014] Depositing the first dielectric material again on the first epitaxial stack and the first dielectric material, and performing chemical mechanical polishing on the deposited first dielectric material;

[0015] Opening a second isolation trench above the P-well of the silicon substrate, and forming a second epitaxial stack in the second isolation trench, wherein the first epitaxial stack and the second epitaxial stack are made of different materials;

[0016] The first dielectric material is chemically mechanically polished to make the heights of the first epitaxial stack, the second epitaxial stack, and the first dielectric material equal.

[0017] Optionally, depositing a hard mask layer on the epitaxial stack and performing a patterning process on the hard mask layer to form a reserved mask layer on the epitaxial stack includes:

[0018] depositing a hard mask layer over the first epitaxial stack and the second epitaxial stack;

[0019] Performing pattern photolithography and etching processing on the hard mask layer in sequence to form a first local mask layer above the first epitaxial stack and a second local mask layer above the second epitaxial stack respectively;

[0020] The first local mask layer and the second local mask layer are sequentially subjected to sidewall deposition and etching processes to form a first reserved mask layer above the first epitaxial stack and a second reserved mask layer above the second epitaxial stack.

[0021] Optionally, based on the epitaxial stack and the retained mask layer, two different types of vertical devices are prepared in isolation trenches corresponding to the N-well and the P-well of the silicon substrate, respectively, including:

[0022] Depositing a second dielectric material on a surface of the first dielectric material corresponding to the P-well of the silicon substrate, so that the second dielectric material covers the second reserved mask layer;

[0023] Performing photolithography and development processing on the first epitaxial stack, and preparing a first vertical device in the first isolation trench based on the first epitaxial stack and the first reserved mask layer;

[0024] removing the second dielectric material above the second reserved mask layer, and depositing the second dielectric material in the first isolation trench so that the second dielectric material covers the first vertical device;

[0025] The second epitaxial stack is subjected to photolithography and development processing, and based on the second epitaxial stack and the second reserved mask layer, a second vertical device is prepared in the second isolation trench, and the second dielectric material covering the surface of the first vertical device is removed.

[0026] Optionally, the step of depositing the dielectric material in the isolation groove, using a recess process to make the dielectric material lower than the height of the vertical device, and exposing the surface of the vertical device to the external environment includes:

[0027] Depositing a first dielectric material in the first isolation trench and the second isolation trench, and performing chemical mechanical polishing on the first dielectric material to make the heights of the first vertical device, the second vertical device, and the first dielectric material equal;

[0028] The first dielectric material is etched back to a height lower than that of the first vertical device and the second vertical device by using a recess process, and surfaces of the first vertical device and the second vertical device are exposed to an external environment.

[0029] Optionally, the step of performing HKMG deposition and patterning process on surfaces of two different types of vertical devices to form a high-K metal gate includes:

[0030] Performing HKMG deposition on the surfaces of the first vertical device and the second vertical device simultaneously, so that the surfaces of the first vertical device and the second vertical device are covered with a high-K layer, and the surfaces of the high-K layer are covered with a metal gate layer;

[0031] The metal gate layer is subjected to photolithography and etching processes based on a preset pattern to form a high-K metal gate.

[0032] Optionally, depositing an interlayer dielectric on the high-K metal gate to form an interlayer dielectric layer, etching through holes on the interlayer dielectric layer based on a preset layout position and filling the interlayer dielectric layer with a conductive metal to form a silicon-based heterogeneous device monolithic chip, including:

[0033] Depositing an interlayer dielectric on the surface of the high-K metal gate to form an interlayer dielectric layer;

[0034] Based on the preset layout position, etching is performed from the top of the interlayer dielectric layer to form a through hole, and a conductive metal is filled in the through hole to form a silicon-based heterogeneous device monolithic chip, wherein the bottom of the through hole is in contact with the first vertical device and the second vertical device respectively.

[0035] Another aspect of the present invention provides a silicon-based heterogeneous device monolithic chip, which is prepared based on any of the above-mentioned silicon-based heterogeneous device monolithic integration methods, comprising:

[0036] A silicon substrate, wherein an N-well and a P-well are arranged on the surface of the silicon substrate;

[0037] a first vertical device, the first vertical device being disposed above the N-well;

[0038] A second vertical device, the second vertical device is arranged above the P well, and surfaces of the first vertical device and the second vertical device are both covered with a high-K metal gate layer;

[0039] A dielectric material layer, wherein the dielectric material layer is laid on the surface of the silicon substrate and covers the bottom of the first vertical device and the second vertical device;

[0040] An interlayer dielectric layer, the interlayer dielectric layer covering the surfaces of the first vertical device and the second vertical device;

[0041] A plurality of through holes are opened in the interlayer dielectric layer along a vertical direction until the bottom of the through hole contacts the surface of the first vertical device or the second vertical device, and the through hole is filled with a conductive metal.

[0042] Optionally, the first vertical device is an NMOS tube, and the second vertical device is a PMOS tube.

[0043] Or the first vertical device is a MOS tube, and the second vertical device is a laser or a detector.

[0044] The silicon-based heterogeneous device monolithic integration method and silicon-based heterogeneous device monolithic provided by the present invention can realize heterogeneous integration of different devices, for example, can realize heterogeneous integration of vertical devices and optoelectronic devices with matching structural features, significantly improving the integration density; specifically, in the isolation groove opened based on the dielectric material, the stacked epitaxy of the device can be carried out, the isolation groove can limit the body defects in the thin film heteroepitaxial growth, and then obtain high-quality device stacked thin film, and the isolation groove structure can also apply pressure stress to the device, thereby greatly improving the performance of the device; at the same time, the film layer structure of different devices can grow independently, the preparation process of a single device is flexible, and different devices can be prepared independently without affecting the preparation process of another device; further, the prepared device can also be continuously stacked and integrated in the vertical direction, without occupying more area, which is more conducive to industrial application; through high-K metal gate deposition, interlayer dielectric deposition, through-hole etching and conductive metal filling and other technologies, the manufacturing process is optimized, the electrical and optical performance of the device is improved, and the consistency and reliability of the device are improved. In summary, the above method realizes high-density integration of different types of vertical devices, significantly improving the performance, reliability and integration of the device.

[0045] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0047] Figure 1 A schematic diagram of the process of a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0048] Figure 2 A schematic diagram showing well implantation on a silicon substrate in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0049] Figure 3 A schematic diagram showing dielectric deposition and opening of a first isolation trench in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0050] Figure 4 A schematic diagram showing the formation of a first epitaxial stack in the monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0051] Figure 5A schematic diagram showing dielectric deposition and opening of a second isolation trench in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0052] Figure 6 A schematic diagram showing the formation of a second epitaxial stack in the monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0053] Figure 7 A schematic diagram of chemical mechanical polishing in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0054] Figure 8 A schematic diagram of hard mask layer deposition in a silicon-based heterogeneous device monolithic integration method provided by an embodiment of the present invention is shown;

[0055] Fig. 9 A schematic diagram showing the photolithography and etching of the hard mask layer pattern in the monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0056] Fig.10 A schematic diagram showing the deposition and etching of a local hard mask layer sidewall in a silicon-based heterogeneous device monolithic integration method provided by an embodiment of the present invention is shown;

[0057] Fig.11 A schematic diagram of dielectric deposition, photolithography and etching in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0058] Fig.12 A schematic diagram of preparing a first vertical device in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0059] Fig.13 A schematic diagram showing dielectric deposition, photolithography and development in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0060] Fig.14 A schematic diagram of preparing a second vertical device in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0061] Fig.15 A schematic diagram showing the removal of dielectric materials in the monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0062] Fig.16 A schematic diagram showing shallow trench isolation deposition and chemical mechanical polishing in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0063] Fig.17 A schematic diagram showing the back engraving of dielectric materials by a recess process in the monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0064] Fig.18 A schematic diagram of HKMG deposition in a monolithic integration method of a silicon-based heterogeneous device provided by an embodiment of the present invention is shown;

[0065] Fig.19 A schematic diagram of MG lithography and etching in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0066] Fig. 20 A schematic diagram of ILD deposition and chemical mechanical polishing in a monolithic integration method of silicon-based heterogeneous devices provided by an embodiment of the present invention is shown;

[0067] Fig.21 A schematic diagram of the structure of a silicon-based heterogeneous device monolithic chip provided by an embodiment of the present invention is shown.

[0068] In the figure:

[0069] 1. Silicon substrate; 101. N-well; 102. P-well;

[0070] 2. The first dielectric material;

[0071] 3. The first isolation groove;

[0072] 4. The first epitaxial stack;

[0073] 5. The second isolation groove;

[0074] 6. Second epitaxial stack;

[0075] 7, hard mask layer; 701, first local mask layer; 702, second local mask layer; 703, first reserved mask layer; 704, second reserved mask layer;

[0076] 8. Second dielectric material;

[0077] 9. A first vertical device;

[0078] 10. A second vertical device;

[0079] 11. High K layer;

[0080] 12. Metal grid layer;

[0081] 13. Interlayer dielectric layer;

[0082] 14. Through hole. DETAILED DESCRIPTION

[0083] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0084] The present invention provides a method for monolithic integration of silicon-based heterogeneous devices, such as Figure 1 As shown, first, a dielectric material is deposited on the surface of a silicon substrate, isolation grooves are opened above the N-well and P-well of the silicon substrate, and an epitaxial stack is formed in the isolation grooves; then, a hard mask layer is deposited above the epitaxial stack, and the hard mask layer is patterned to form a reserved mask layer above the epitaxial stack, and based on the epitaxial stack and the reserved mask layer, two different types of vertical devices are prepared in the isolation grooves corresponding to the N-well and P-well of the silicon substrate, respectively; then, a dielectric material is deposited in the isolation grooves, and a recess process is used to make the dielectric material lower than the height of the vertical device, and the surface of the vertical device is exposed to the external environment; finally, HKMG deposition and patterning process are performed on the surfaces of the two different types of vertical devices to form a high-K metal gate, and interlayer dielectric deposition is performed on the high-K metal gate to form an interlayer dielectric layer, and through-hole etching is performed on the interlayer dielectric layer based on a preset layout position and filled with conductive metal to form a silicon-based heterogeneous device monolith.

[0085] The silicon-based heterogeneous device monolithic integration method provided by the present invention can realize heterogeneous integration of different devices, for example, it can realize heterogeneous integration of vertical devices and optoelectronic devices with matching structural features, significantly improving the integration density; specifically, in the isolation grooves opened based on dielectric materials, the stacked epitaxy of the device can be carried out, and the isolation grooves can limit the body defects in the heterogeneous epitaxy of the thin film, thereby obtaining high-quality device stacked thin films, and the isolation groove structure can also apply pressure stress to the device, thereby greatly improving the performance of the device; at the same time, the film layer structures of different devices can grow independently, the preparation process of a single device is flexible, and different devices can be prepared independently without affecting the preparation process of another device; further, the prepared devices can also be continuously stacked and integrated in the vertical direction, without occupying more area, which is more conducive to industrial application; through high-K metal gate deposition, interlayer dielectric deposition, through-hole etching and conductive metal filling and other technologies, the manufacturing process is optimized, the electrical and optical performance of the device is improved, and the consistency and reliability of the device are improved. In summary, the above method realizes high-density integration of different types of vertical devices, significantly improving the performance, reliability and integration of the device.

[0086] The specific operation steps of the monolithic integration method of silicon-based heterogeneous devices provided by the present invention are as follows:

[0087] Step 1: Perform well implantation on the silicon substrate 1.

[0088] Specifically, a well region is formed on the surface of the silicon substrate 1 by using an ion implantation process, wherein the well region includes an N-well 101 and a P-well 102 .

[0089] Among them, the N-well 101 and the P-well 102 are commonly used doping regions in semiconductor manufacturing, mainly used to form different types of transistors and isolate different functional areas. The conductivity type of the material is changed by introducing different types of dopants into the silicon substrate 1. The N-well 101 is a region formed by doping n-type dopants into the p-type silicon substrate 1, and the majority of carriers in the N-well 101 are electrons; the P-well 102 is a region formed by doping p-type dopants into the n-type silicon substrate 1, and the majority of carriers in the P-well 102 are holes.

[0090] In this embodiment, if Figure 2 As shown, an N-well 101 and a P-well 102 are formed on the surface of a silicon substrate 1 by an ion implantation process, providing necessary doping regions for the subsequent preparation of vertical devices and optoelectronic devices; specific process steps include coating a layer of photoresist on the silicon substrate 1, then irradiating the photoresist with a mask and an exposure light source, removing the unexposed photoresist with a developer to expose the area where ions need to be implanted, and then using an ion implanter to implant doped ions into specific areas of the silicon substrate 1 to form an N-well 101 and a P-well 102, and finally removing the remaining photoresist.

[0091] Step 2: Dielectric deposition and opening of the first isolation trench 3.

[0092] Specifically, the first dielectric material 2 is deposited on the surface of the silicon substrate 1 , and the first isolation trench 3 is opened above the N-well 101 of the silicon substrate 1 .

[0093] The first dielectric material 2 may be silicon oxide or silicon nitride, and the deposition method may be chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition or the like.

[0094] In this embodiment, if Figure 3 As shown, a layer of dielectric material is deposited on the surface of the silicon substrate 1 to provide a basis for the subsequent opening of isolation grooves and epitaxial growth. An isolation groove is opened above the N-well 101 of the silicon substrate 1 to provide a clear boundary for the subsequent epitaxial stacking growth and reduce parasitic effects. The opening of the isolation groove can effectively isolate different types of devices, reduce parasitic effects, and improve the performance and reliability of the device. The isolation groove can also limit the body defects in the heteroepitaxial growth of the thin film, so as to obtain a high-quality epitaxial film. The isolation groove structure can also apply stress to the device to further improve the performance of the device. The first dielectric material 2 has high insulation performance, which can effectively isolate different functional areas and reduce electrical interference.

[0095] Step 3: forming a first epitaxial stack 4.

[0096] Specifically, the first epitaxial stack 4 is formed in the first isolation trench 3 .

[0097] In this embodiment, if Figure 4 As shown, an epitaxial stack is grown in the first isolation trench 3 to achieve heterogeneous integration of different materials and provide high-quality thin films for subsequent device preparation. The epitaxial stack is specifically composed of three film layers, wherein the upper and lower film layers are Si (silicon), GeSi (germanium silicon alloy), GaAs (gallium arsenide), and Ge (germanium), and the middle film layer is Si (silicon), GeSi (germanium silicon alloy), and InGaAs (indium gallium arsenic); and the method for generating the epitaxial stack specifically adopts RPCVD (remote plasma chemical vapor deposition) technology, that is, through remote activation of plasma, high-quality, low-defect epitaxial film growth can be achieved, thereby improving the quality of the epitaxial film. The epitaxial stack formed by the present application has a multi-layer structure, which can optimize the interface quality between the layers, reduce interface defects, and improve the performance of the device. The multi-film layer structure can optimize the stress distribution, reduce the stress problems caused by material mismatch, and improve the reliability and performance of the device. The remote plasma chemical vapor deposition technology can select different materials and process parameters according to specific needs to adapt to the preparation of different types of devices. And the epitaxial stack is formed in the isolation groove, which can realize the integration of different types of devices in the vertical direction and improve the integration density. The growth of the epitaxial stack can ensure the planarization of the surface, providing a good foundation for the subsequent process steps.

[0098] Step 4: Dielectric deposition and opening of the second isolation trench 5.

[0099] Specifically, the first dielectric material 2 is deposited again on the first epitaxial stack 4 and the first dielectric material 2 , and the deposited first dielectric material 2 is chemically mechanically polished, and the second isolation trench 5 is opened above the P-well 102 of the silicon substrate 1 .

[0100] In this embodiment, if Figure 5 As shown, a layer of dielectric material is deposited again on the first epitaxial stack 4 and the first dielectric material 2 to provide protection and support for the subsequent isolation groove opening and device preparation; and the deposited first dielectric material 2 is chemically mechanically polished to ensure the flatness of the surface, providing a good foundation for the subsequent process steps; after the chemical mechanical polishing of the first dielectric material 2, a second isolation groove 5 is opened above the P well 102 of the silicon substrate 1 to provide a clear boundary for the subsequent epitaxial stack growth and device preparation, thereby reducing parasitic effects.

[0101] Step 5: forming a second epitaxial stack 6.

[0102] Specifically, the second epitaxial stack 6 is formed in the second isolation trench 5 .

[0103] In this embodiment, if Figure 6 As shown, a second epitaxial stack 6 is formed in the opened second isolation groove 5. The formation process method of the second epitaxial stack 6 and the formation process method of the first epitaxial stack 4 can both adopt remote plasma chemical vapor deposition technology. However, considering that the devices prepared in the first isolation groove 3 and the second isolation groove 5 are different devices, for example, the device in the first isolation groove 3 is an NMOS tube, and the device in the second isolation groove 5 is a PMOS tube; or the device in the first isolation groove 3 is a MOS tube, and the device in the second isolation groove 5 is a laser or a detector, considering that the structures and processes of the two devices are different, the two devices need to be manufactured separately in the two isolation grooves.

[0104] Step 6: Chemical mechanical polishing.

[0105] Specifically, the first dielectric material 2 is subjected to chemical mechanical polishing to make the heights of the first epitaxial stack 4 , the second epitaxial stack 6 and the first dielectric material 2 equal.

[0106] In this embodiment, if Figure 7 As shown, after the second stack is formed, the first dielectric material 2 is chemically mechanically polished to make the heights of the first epitaxial stack 4, the second epitaxial stack 6 and the first dielectric material 2 equal, ensuring surface flatness. The flat surface can reduce defects in subsequent processes, improve the yield and performance of the device, provide a good foundation for subsequent preparation processes, and ensure the reliability and performance of interconnection.

[0107] Step 7: Deposition of a hard mask layer 7.

[0108] Specifically, the hard mask layer 7 is deposited over the first epitaxial stack 4 and the second epitaxial stack 6 .

[0109] In this embodiment, if Figure 8 As shown, by depositing a hard mask layer 7, protection and masking are provided for subsequent patterning processes and etching steps, wherein the hard mask layer 7 is also a three-layer structure, wherein the upper and lower layers may be oxide layers, and the middle layer is silicon nitride; the hard mask layer 7 protects the epitaxial stack in subsequent etching and process steps, prevents the epitaxial stack from being physically or chemically damaged, and ensures the integrity of the device structure; the hard mask layer 7 can also reduce the direct effect on the epitaxial layer during the etching process, reduce the generation of defects, and improve the performance and reliability of the device; and the hard mask layer 7 usually has a high etching selectivity, that is, during the etching process, the etching rate of the hard mask layer 7 is lower than that of the epitaxial stack, and the etching depth and shape can be more accurately controlled. Through photolithography and etching processes, the hard mask layer 7 can be patterned to form a desired mask pattern, providing an accurate mask for subsequent process steps.

[0110] Step 8: Photolithography and etching of the hard mask layer 7 pattern.

[0111] Specifically, the hard mask layer 7 is subjected to pattern lithography and etching processes in sequence to form a first local mask layer 701 on the first epitaxial stack 4 and a second local mask layer 702 on the second epitaxial stack 6 respectively.

[0112] In this embodiment, if Fig. 9 As shown, a desired pattern is formed on the hard mask layer 7 through a photolithography process to provide a mask for the subsequent etching step. The specific process can be to uniformly coat a layer of photoresist on the surface of the hard mask layer 7, use a mask and an exposure light source to irradiate the photoresist, so that the photoresist undergoes chemical changes in the exposure area, and then remove part of the photoresist through a developer to expose a part of the hard mask layer 7 to form the desired pattern, and then use an etching process, such as reactive ion etching and other dry etching techniques to remove the hard mask layer 7 not protected by the photoresist to form a local mask layer. Among them, the dry etching technology can achieve high-precision etching, ensure the edge of the local mask layer is clear, and reduce defects in the etching process.

[0113] Step 9: local hard mask layer 7 sidewall deposition and etching.

[0114] Specifically, the first local mask layer 701 and the second local mask layer 702 are sequentially subjected to sidewall deposition and etching processes to form a first reserved mask layer 703 above the first epitaxial stack 4 and a second reserved mask layer 704 above the second epitaxial stack 6 .

[0115] In this embodiment, if Fig.10 As shown, a layer of protective material is deposited on the side walls of the first local mask layer 701 and the second local mask layer 702 to form side walls. The side wall material is usually selected from materials with high etching selectivity and good mechanical strength, such as silicon nitride and silicon oxide. The side walls are deposited on the side walls of the local mask layers to provide additional protection for subsequent etching steps to prevent damage to the epitaxial stack during the etching process. The protective effect of the side walls can reduce defects generated during the etching process and improve the performance and reliability of the device. Through the side wall deposition and etching process, the pattern and size of the retained mask layer can be accurately controlled to ensure the consistency and reliability of the device.

[0116] Step 10: depositing the first dielectric material 2.

[0117] Specifically, the second dielectric material 8 is deposited on the surface of the first dielectric material 2 corresponding to the P-well 102 of the silicon substrate 1 , so that the second dielectric material 8 covers the second reserved mask layer 704 .

[0118] In this embodiment, if Fig.11As shown, the second dielectric material 8 can specifically be silicon oxide or silicon nitride. Considering that the devices in the two isolation grooves need to be prepared separately in sequence, before preparing the device in the first isolation groove 3, the second dielectric material 8 is used to deposit the second reserved mask layer 704 on the second epitaxial stack 6, that is, the protection of the second reserved mask layer 704 is achieved by photoresist.

[0119] Step 11: Prepare a first vertical device 9.

[0120] Specifically, the first epitaxial stack 4 is subjected to photolithography and development processing, and based on the first epitaxial stack 4 and the first reserved mask layer 703 , the first vertical device 9 is prepared in the first isolation trench 3 .

[0121] In this embodiment, if Fig.12 As shown, after the second epitaxial stack 6 and the second retained mask layer 704 are protected, the first epitaxial stack 4 is firstly subjected to photolithography and development treatment to expose the first epitaxial stack 4, and then the first vertical device 9 is prepared in the first isolation groove 3. The vertical device can be specifically a vertical nano-ring gate device (Vertical Gate-All-Around, VGAA), which is an advanced semiconductor device structure and is particularly suitable for future nanoscale integrated circuits. Specifically, nanowires or nanosheets are formed in the vertical direction as channels and the gate is wrapped around them to achieve all-round control of the channels, thereby significantly improving the performance and reliability of the devices.

[0122] Step 12: depositing the second dielectric material 8.

[0123] Specifically, the second dielectric material 8 above the second reserved mask layer 704 is removed, and the second dielectric material 8 is deposited in the first isolation trench 3 , so that the second dielectric material 8 covers the first vertical device 9 .

[0124] In this embodiment, if Fig.13 As shown, after the preparation of the first vertical device 9 is completed, the second vertical device 10 needs to be further prepared. At this time, the same method can be used to remove the second dielectric material 8 covering the second reserved mask layer 704, and deposit the second dielectric material 8 in the first isolation groove 3, so that the second dielectric material 8 covers the first vertical device 9, forming protection for the first vertical device 9, and preventing the preparation of the second vertical device 10 from affecting the first vertical device 9.

[0125] Step 13: Prepare a second vertical device 10.

[0126] Specifically, the second epitaxial stack 6 is subjected to photolithography and development processing, and based on the second epitaxial stack 6 and the second reserved mask layer 704 , the second vertical device 10 is prepared in the second isolation trench 5 .

[0127] In this embodiment, if Fig.14 As shown, after the first vertical device 9 is protected by the second dielectric material 8, the second epitaxial stack 6 is also subjected to photolithography and development to expose the second epitaxial stack 6, and then the second vertical device 10 is prepared in the second isolation groove 5. The first vertical device 9 and the second vertical device 10 are completely different devices, thus forming the basis for monolithic integration of silicon-based heterogeneous devices.

[0128] Step 14: Removal of dielectric material.

[0129] Specifically, the second dielectric material 8 covering the surface of the first vertical device 9 is removed.

[0130] In this embodiment, if Fig.15 As shown, after the preparation of the second vertical device 10 is completed, the second dielectric material 8 covering the surface of the first vertical device 9 needs to be removed. Specifically, dry etching or wet etching can be used for removal. At this time, the first vertical device 9 and the second vertical device 10 are respectively manufactured in the first isolation groove 3 and the second isolation groove 5.

[0131] Step 15: shallow trench isolation deposition and chemical mechanical polishing.

[0132] Specifically, the first dielectric material 2 is deposited in the first isolation trench 3 and the second isolation trench 5 , and the first dielectric material 2 is chemically mechanically polished to make the heights of the first vertical device 9 , the second vertical device 10 and the first dielectric material 2 equal.

[0133] In this embodiment, if Fig.16 As shown, a first dielectric material 2 is deposited in the first isolation groove 3 and the second isolation groove 5 to provide protection and support for subsequent process steps and to achieve isolation between devices. By chemically mechanically polishing the deposited first dielectric material 2, the surface is flattened to ensure that the heights of the first vertical device 9, the second vertical device 10 and the first dielectric material 2 are equal, providing a good foundation for subsequent process steps. The flat surface can reduce defects in subsequent processes and improve the yield and performance of the device.

[0134] Step 16: Recess process to etch back the dielectric material.

[0135] Specifically, the first dielectric material 2 is etched back to a height lower than the first vertical device 9 and the second vertical device 10 by using a recess process, and the surfaces of the first vertical device 9 and the second vertical device 10 are exposed to the external environment.

[0136] In this embodiment, if Fig.17As shown, the first dielectric material 2 is etched back to a height lower than the first vertical device 9 and the second vertical device 10 through an etching back process, exposing the surface of the vertical device, which facilitates subsequent process steps. At the same time, it is also necessary to ensure that the height of the first dielectric material 2 after etching back and the exposure of the surface of the vertical device meet the requirements.

[0137] Step 17: HKMG deposition.

[0138] Specifically, HKMG is deposited simultaneously on the surfaces of the first vertical device 9 and the second vertical device 10 , so that the surfaces of the first vertical device 9 and the second vertical device 10 are covered with the high-K layer 11 , and the surfaces of the high-K layer 11 are covered with the metal gate layer 12 .

[0139] In this embodiment, if Fig.18 As shown, High-K Metal Gate (HKMG) technology is an important technology in modern semiconductor devices, which aims to improve the performance and reliability of the devices. High-K materials can reduce gate leakage current, while metal gate materials can improve the working characteristics and reliability of the gate. By simultaneously depositing HKMG on the surfaces of the first vertical device 9 and the second vertical device 10, comprehensive optimization of the device can be achieved.

[0140] Among them, the operation steps include cleaning and pre-treating the surface of the first vertical device 9 and the second vertical device 10 to ensure that the device surface is clean and free of contaminants, providing a good foundation for the subsequent deposition process, and then depositing high-K material on the surface of the first vertical device 9 and the second vertical device 10 to form a gate insulation layer, and then depositing metal gate material on the surface of the high-K material to form a metal gate layer 12.

[0141] Step 18: MG photolithography and etching.

[0142] Specifically, the metal gate layer 12 is subjected to photolithography and etching processes based on a preset pattern to form a high-K metal gate.

[0143] In this embodiment, if Fig.19 As shown, after completing the previous steps, the surfaces of the first device and the second device are covered with a high-K layer 11 and a metal gate layer 12. It is further necessary to perform photolithography and etching on the metal gate layer 12 on the high-K layer 11 based on a preset pattern, and only retain a portion of the metal gate layer 12 to form a preset pattern, which is combined with the high-K layer 11 at the bottom to form a precise gate structure, which is crucial for controlling the channel potential, reducing leakage current and improving device performance.

[0144] Step 19: ILD deposition and chemical mechanical polishing.

[0145] Specifically, an interlayer dielectric deposition is performed on the surface of the high-K metal gate to form the interlayer dielectric layer 13 .

[0146] In this embodiment, if Fig. 20 As shown, in semiconductor manufacturing, the deposition of the interlayer dielectric (ILD) layer 13 is to provide insulation and isolation between metal interconnects at different levels, reduce parasitic capacitance, and improve device performance and reliability. Interlayer dielectric deposition on the surface of the high-K metal gate can ensure good insulation between the gate and other metal layers, and provide a flat surface for subsequent interconnection processes. The specific processing steps include cleaning and pretreatment to ensure that the surface of the high-K metal gate is clean and free of pollutants, providing a good foundation for subsequent deposition processes, and then depositing interlayer dielectric materials on the surface of the high-K metal gate to form an interlayer dielectric layer 13 to provide insulation and isolation. Finally, a chemical mechanical polishing process is used to flatten the surface of the interlayer dielectric layer 13, providing a good foundation for subsequent interconnection processes.

[0147] Step 20: etching and filling the through hole 14.

[0148] Specifically, based on the preset layout position, etching is performed from the top of the interlayer dielectric layer 13 to form a through hole 14, and a conductive metal is filled in the through hole 14 to form a silicon-based heterogeneous device monolithic chip, wherein the bottom of the through hole 14 is in contact with the first vertical device 9 and the second vertical device 10 respectively.

[0149] In this embodiment, if Fig.21 As shown, in semiconductor manufacturing, the formation of a via 14 (Via) is a key step in realizing metal interconnection at different levels. By etching the top of the interlayer dielectric layer 13 to form the via 14, and filling the via 14 with conductive metal, electrical connections between different levels can be realized, thereby forming a complete silicon-based heterogeneous device monolithic chip. The etching process can adopt dry etching, that is, using dry etching technology such as reactive ion etching to remove the interlayer dielectric material not protected by the photoresist to form the via 14. The etching process needs to accurately control the etching time and strip The first vertical device 9 and the second vertical device 10 are detected by optical or electrical methods to ensure that the bottom of the through hole 14 is accurately in contact with the first vertical device 9 and the second vertical device 10, and the remaining photoresist is removed to expose the complete through hole 14 structure. Finally, the inner wall of the through hole 14 is pretreated, such as cleaning and surface modification, to improve the adhesion of the metal. Conductive metals, such as tungsten and copper, are deposited in the through hole 14 by physical vapor deposition, chemical vapor deposition or electroplating, to complete the preparation of the silicon-based heterogeneous device monolithic.

[0150] On the other hand, the present invention provides a silicon-based heterogeneous device monolithic chip, which is prepared based on any of the above-mentioned silicon-based heterogeneous device monolithic integration methods, including a silicon substrate 1, a surface of the silicon substrate 1 is provided with an N-well 101 and a P-well 102; a first vertical device 9, the first vertical device 9 is arranged above the N-well 101; a second vertical device 10, the second vertical device 10 is arranged above the P-well 102, and the surfaces of the first vertical device 9 and the second vertical device 10 are both covered with a high-K metal gate layer 12; a dielectric material layer, the dielectric material layer is laid on the surface of the silicon substrate 1 and covers the bottom of the first vertical device 9 and the second vertical device 10; an interlayer dielectric layer 13, the interlayer dielectric layer 13 covers the surface of the first vertical device 9 and the second vertical device 10; a plurality of through holes 14, the plurality of through holes 14 are opened in the interlayer dielectric layer 13 along the vertical direction until the bottom of the through hole 14 contacts the surface of the first vertical device 9 or the second vertical device 10, and the through hole 14 is filled with a conductive metal.

[0151] Further, the first vertical device 9 is an NMOS tube, and the second vertical device 10 is a PMOS tube, or the first vertical device 9 is a MOS tube, and the second vertical device 10 is a laser or a detector.

[0152] Among them, Fig.21 As shown, there are five through holes on the silicon-based heterogeneous device. After filling with conductive metal, the five through holes are VSS, Vout, Vin, Vout and VDD according to the functions implemented. VSS is the reference potential point in the circuit, usually connected to the ground line of the power supply; Vout is used to indicate the output voltage; Vin is used to indicate the input voltage; VDD indicates the power supply voltage, usually connected to the positive pole of the power supply.

[0153] The silicon-based heterogeneous device monolithic chip provided by the present application has a high degree of integration. By respectively arranging a first vertical device 9 and a second vertical device 10 above the N-well 101 and the P-well 102, different types of device integration can be realized in the vertical direction, greatly improving the device density per unit area; the introduction of the interlayer dielectric layer 13 and the through hole 14 enables devices and interconnects at different levels to be efficiently integrated together, further improving the degree of integration; it also has high performance, the use of the high-K metal gate layer 12 can significantly reduce the gate leakage current, improve the electrical performance of the gate, thereby improving the switching speed and driving capability of the device, the use of the interlayer dielectric layer 13 can reduce the parasitic capacitance and resistance between different metal layers, and improve the frequency response and switching speed of the device; it also has high reliability, the interlayer dielectric layer 13 Good insulation and isolation are provided between metal interconnects at different levels, parasitic effects are reduced, and reliability and stability of the device are improved; and the silicon-based heterogeneous device monolithic chip provided in the present application can realize a variety of device combinations, wherein the first vertical device 9 can be an NMOS tube, and the second vertical device 10 can be a PMOS tube, or the first vertical device 9 can be a MOS tube, and the second vertical device 10 can be a laser or a detector, so that the monolithic chip can be applied to a variety of different application scenarios. Specifically, by integrating NMOS tubes and PMOS tubes on the same silicon substrate 1, high-performance logic circuits can be realized, which are suitable for high-performance computing and data center applications, and by integrating MOS tubes and lasers or detectors on the same silicon substrate 1, optoelectronic integration can be realized, which is suitable for high-speed optical communication systems.

Claims

1. A method for monolithic integration of silicon-based heterogeneous devices, characterized in that: include: Depositing a dielectric material on the surface of a silicon substrate, opening isolation grooves above an N-well and a P-well of the silicon substrate respectively, and forming an epitaxial stack in the isolation grooves; Depositing a hard mask layer on the epitaxial stack and patterning the hard mask layer to form a reserved mask layer on the epitaxial stack, and preparing two different types of vertical devices in isolation grooves corresponding to the N-well and the P-well of the silicon substrate based on the epitaxial stack and the reserved mask layer; Depositing a dielectric material in the isolation groove, using a recess process to make the dielectric material lower than the height of the vertical device, and exposing the surface of the vertical device to the external environment; HKMG deposition and patterning process are performed on the surfaces of the two different types of vertical devices to form a high-K metal gate, interlayer dielectric deposition is performed on the high-K metal gate to form an interlayer dielectric layer, and through-holes are etched on the interlayer dielectric layer based on a preset layout position and filled with conductive metal to form a silicon-based heterogeneous device monolithic chip.

2. The method according to claim 1, characterized in that Before depositing the dielectric material on the surface of the silicon substrate, the method includes: A well region is formed on the surface of a silicon substrate by using an ion implantation process, wherein the well region includes an N-well and a P-well.

3. The method according to claim 1, characterized in that The method of depositing a dielectric material on the surface of a silicon substrate, opening isolation grooves above an N-well and a P-well of the silicon substrate, and forming an epitaxial stack in the isolation grooves comprises: Depositing a first dielectric material on a surface of a silicon substrate, opening a first isolation trench above an N-well of the silicon substrate, and forming a first epitaxial stack in the first isolation trench; Depositing the first dielectric material again on the first epitaxial stack and the first dielectric material, and performing chemical mechanical polishing on the deposited first dielectric material; Opening a second isolation trench above the P-well of the silicon substrate, and forming a second epitaxial stack in the second isolation trench, wherein the first epitaxial stack and the second epitaxial stack are made of different materials; The first dielectric material is chemically mechanically polished to make the heights of the first epitaxial stack, the second epitaxial stack, and the first dielectric material equal.

4. The method according to claim 3, characterized in that The step of depositing a hard mask layer on the epitaxial stack and performing a patterning process on the hard mask layer to form a reserved mask layer on the epitaxial stack comprises: depositing a hard mask layer over the first epitaxial stack and the second epitaxial stack; Performing pattern photolithography and etching processing on the hard mask layer in sequence to form a first local mask layer above the first epitaxial stack and a second local mask layer above the second epitaxial stack respectively; The first local mask layer and the second local mask layer are sequentially subjected to sidewall deposition and etching processes to form a first reserved mask layer above the first epitaxial stack and a second reserved mask layer above the second epitaxial stack.

5. The method according to claim 4, characterized in that The method of preparing two different types of vertical devices in the isolation grooves corresponding to the N-well and the P-well of the silicon substrate based on the epitaxial stack and the reserved mask layer respectively includes: Depositing a second dielectric material on a surface of the first dielectric material corresponding to the P-well of the silicon substrate, so that the second dielectric material covers the second reserved mask layer; Performing photolithography and development processing on the first epitaxial stack, and preparing a first vertical device in the first isolation trench based on the first epitaxial stack and the first reserved mask layer; removing the second dielectric material above the second reserved mask layer, and depositing the second dielectric material in the first isolation trench so that the second dielectric material covers the first vertical device; The second epitaxial stack is subjected to photolithography and development processing, and based on the second epitaxial stack and the second reserved mask layer, a second vertical device is prepared in the second isolation trench, and the second dielectric material covering the surface of the first vertical device is removed.

6. The method according to claim 5, characterized in that The step of depositing the dielectric material in the isolation groove, using a recess process to make the dielectric material lower than the height of the vertical device, and exposing the surface of the vertical device to the external environment includes: Depositing a first dielectric material in the first isolation trench and the second isolation trench, and performing chemical mechanical polishing on the first dielectric material to make the heights of the first vertical device, the second vertical device, and the first dielectric material equal; The first dielectric material is etched back to a height lower than that of the first vertical device and the second vertical device by using a recess process, and surfaces of the first vertical device and the second vertical device are exposed to an external environment.

7. The method according to claim 6, characterized in that The method of performing HKMG deposition and patterning process on the surfaces of the two different types of vertical devices to form a high-K metal gate includes: Performing HKMG deposition on surfaces of the first vertical device and the second vertical device simultaneously, so that surfaces of the first vertical device and the second vertical device are covered with a high-K layer, and surfaces of the high-K layer are covered with a metal gate layer; The metal gate layer is subjected to photolithography and etching processes based on a preset pattern to form a high-K metal gate.

8. The method according to claim 7, characterized in that The method comprises depositing an interlayer dielectric on the high-K metal gate to form an interlayer dielectric layer, etching a through hole on the interlayer dielectric layer based on a preset layout position and filling the interlayer dielectric layer with a conductive metal to form a silicon-based heterogeneous device monolithic chip, including: Depositing an interlayer dielectric on the surface of the high-K metal gate to form an interlayer dielectric layer; Based on the preset layout position, etching is performed from the top of the interlayer dielectric layer to form a through hole, and a conductive metal is filled in the through hole to form a silicon-based heterogeneous device monolithic chip, wherein the bottom of the through hole is in contact with the first vertical device and the second vertical device respectively.

9. A silicon-based heterogeneous device monolithic chip, characterized in that: Prepared based on the monolithic integration method of silicon-based heterogeneous devices according to any one of claims 1 to 8, comprising: A silicon substrate (1), wherein an N-well (101) and a P-well (102) are arranged on the surface of the silicon substrate; A first vertical device (9), the first vertical device (9) being arranged above the N well (101); A second vertical device (10), the second vertical device (10) being arranged above the P well (102), and surfaces of the first vertical device (9) and the second vertical device (10) are both covered with a high-K metal gate layer; A dielectric material layer, the dielectric material layer is laid on the surface of the silicon substrate (1) and covers the bottom of the first vertical device and the second vertical device; An interlayer dielectric layer (13), the interlayer dielectric layer (13) covering the surfaces of the first vertical device (9) and the second vertical device (10); A plurality of through holes (14), wherein the plurality of through holes (14) are opened in the interlayer dielectric layer (13) along a vertical direction until the bottom of the through hole (14) contacts the surface of the first vertical device (9) or the second vertical device (10), and the through hole (14) is filled with a conductive metal.

10. The silicon-based heterogeneous device monolithic chip according to claim 9, characterized in that: The first vertical device (9) is an NMOS tube, and the second vertical device (10) is a PMOS tube. Or the first vertical device (9) is a MOS tube, and the second vertical device (10) is a laser or a detector.

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