Silicon-based Topcon solar cell and preparation method thereof

Abstract

The invention discloses a silicon-based Topcon solar cell and a preparation method thereof, and belongs to the technical field of solar cells. The silicon-based Topcon solar cell is based on the arrangement of a tunneling oxide layer, a first n-type semiconductor layer and a second n-type semiconductor layer which are sequentially stacked on the backlight surface of a silicon wafer, the first n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and antimony elements, and the second n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and germanium elements. The silicon-based Topcon solar cell solves the problem that the passivation effect of back passivation is reduced due to the fact that phosphorus in a phosphorus-doped silicon layer is diffused into a silicon wafer in the prior art, the passivation performance and the conductivity of the n-type semiconductor lamination layer can be improved, and then the silicon-based Topcon solar cell with excellent performance can be obtained.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a silicon-based Topcon solar cell and a preparation method thereof. Background Art

[0002] Silicon-based Topcon solar cells use N-type silicon wafers as light-absorbing matrix materials, and prepare PN junctions on the textured surface of silicon wafers by high-temperature boron diffusion. Silicon-based Topcon solar cells usually include a back conductive electrode, a back dielectric layer, a phosphorus-doped silicon layer, a tunneling oxide layer, a silicon wafer, a passivation film layer, a front dielectric layer, and a front conductive electrode stacked in sequence from the backlight side to the light-receiving side. The back passivation is mainly composed of a tunneling oxide layer, a phosphorus-doped silicon layer, and a back dielectric layer.

[0003] Among them, the passivation of the phosphorus-doped silicon layer is mainly achieved by doping a high dose of phosphorus in the silicon film to form field passivation, which requires high-temperature heat treatment to activate the phosphorus atoms so that the phosphorus atoms form bonds with silicon atoms to provide groups of excess unpaired electrons. In order to obtain a higher concentration of active phosphorus-doped atoms, the annealing temperature must reach above 870°C. However, under this temperature condition, the phosphorus element has a relatively high diffusion rate, so that the phosphorus atoms diffuse through the phosphorus-doped silicon layer and the tunneling oxide layer into the silicon wafer. When the phosphorus element entering the silicon wafer reaches a certain atomic concentration, the passivation effect of the back passivation will be sharply reduced. Summary of the invention

[0004] In view of the above analysis, the present invention aims to provide a silicon-based Topcon solar cell and a preparation method thereof, which solves the problem in the prior art that the phosphorus element in the phosphorus-doped silicon layer diffuses into the silicon wafer, resulting in reduced passivation effect of back passivation.

[0005] The purpose of the present invention is mainly achieved through the following technical solutions:

[0006] The present invention provides a silicon-based Topcon solar cell, comprising a tunneling oxide layer, a first n-type semiconductor layer and a second n-type semiconductor layer stacked in sequence on the backlight surface of a silicon wafer; the first n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and antimony elements, and the second n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and germanium elements.

[0007] In one possible design, the atomic concentration of active antimony atoms in the first n-type semiconductor layer is no greater than 7E19 atoms / cm 3 .

[0008] In one possible design, the atomic concentration of active phosphorus atoms in the second n-type semiconductor layer is not less than 1E20 atoms / cm 3 , the atomic number ratio of germanium atoms to silicon atoms is not greater than 4%.

[0009] In a possible design, a transitional n-type semiconductor layer is stacked between the first n-type semiconductor layer and the second n-type semiconductor layer, and the transitional n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon, antimony and germanium.

[0010] In one possible design, in the first n-type semiconductor layer, the atomic concentration of active phosphorus atoms is greater than the atomic concentration of active antimony atoms.

[0011] In one possible design, the total phosphorus atom concentration in the tunneling oxide layer is greater than the total phosphorus atom concentration in the first n-type semiconductor layer and the second n-type semiconductor layer; and / or, the total phosphorus atom concentration in the tunneling oxide layer is greater than the total phosphorus atom concentration in the first n-type semiconductor layer; and / or, the total phosphorus atom concentration in the tunneling oxide layer is greater than the total phosphorus atom concentration in the second n-type semiconductor layer.

[0012] In one possible design, the atomic concentration of active antimony atoms in the first n-type semiconductor layer gradually increases as it approaches the tunnel oxide layer; and / or, the total atomic concentration of active phosphorus atoms and active antimony atoms in the first n-type semiconductor layer gradually increases as it moves away from the tunnel oxide layer.

[0013] In a possible design, the thickness of the first n-type semiconductor layer is 30-200 nm; and / or the thickness of the second n-type semiconductor layer is 20-180 nm; and / or the thickness of the tunneling oxide layer is 1.5-2.0 nm.

[0014] The present invention also provides a method for preparing a silicon-based Topcon solar cell, which is used to prepare the above-mentioned silicon-based Topcon solar cell. The preparation method comprises the following steps:

[0015] Providing a silicon wafer;

[0016] A tunneling oxide layer, a first n-type semiconductor layer and a second n-type semiconductor layer are prepared on the backlight side of the silicon wafer.

[0017] In a possible design, during the preparation of the first n-type semiconductor layer and the second n-type semiconductor layer, the activation temperature of phosphorus atoms in the first n-type semiconductor layer and the second n-type semiconductor layer is 820-940°C.

[0018] Compared with the prior art, the present invention can at least achieve the following beneficial effects:

[0019] A) In the silicon-based Topcon solar cell provided by the present invention, a stacked structure is used to replace the existing single-layer structure as the back passivation, and the n-type semiconductor stack is doped with a variety of doping elements to improve the passivation performance and conductivity of the n-type semiconductor stack, thereby obtaining a silicon-based Topcon solar cell with excellent performance.

[0020] B) In the silicon-based Topcon solar cell provided by the present invention, a first n-type semiconductor layer is arranged on the surface of the tunneling oxide layer away from the side of the silicon wafer, and the first n-type semiconductor layer is doped with hydrogen, phosphorus, oxygen, carbon and antimony elements. Among them, on the one hand, hydrogen atoms can bond the dangling bonds at the interface between the silicon wafer and the tunneling oxide layer, thereby enhancing the passivation effect; on the other hand, the antimony element is introduced by in-situ doping. Considering that the atomic radius of the antimony element is large, the doping of the antimony element causes a large lattice distortion in the first n-type semiconductor layer, and the internal stress of the first n-type semiconductor layer increases, so that the diffusion rate of phosphorus atoms and the penetration probability of phosphorus atoms in the first n-type semiconductor layer and the tunneling oxide layer are reduced, thereby maintaining a good back passivation effect and improving the open circuit voltage and photoelectric conversion efficiency of the silicon-based Topcon solar cell; on the other hand, since the penetration probability of phosphorus atoms in the first n-type semiconductor layer and the tunneling oxide layer is reduced, in the preparation process of the silicon-based Topcon solar cell, the annealing temperature can be further increased, thereby increasing the concentration of doped atoms in the first n-type semiconductor layer and improving the passivation effect.

[0021] C) In the silicon-based Topcon solar cell provided by the present invention, a second n-type semiconductor layer is arranged on the surface of the first n-type semiconductor layer away from the silicon wafer, and the second n-type semiconductor layer is doped with hydrogen, phosphorus, oxygen, carbon and germanium elements. The germanium element is introduced by in-situ doping, and the second n-type semiconductor layer is doped with a small amount of germanium atoms, so that the band gap width of the second n-type semiconductor layer is slightly narrowed. Due to the flattening of the Fermi level, the conduction band energy level height of the second n-type semiconductor layer is slightly lower than the conduction band energy level height of the first n-type semiconductor layer under high phosphorus doping conditions, which is conducive to the conduction of electrons in the second n-type semiconductor layer, effectively optimizing the conductivity of the second n-type semiconductor layer, thereby improving the fill factor and photoelectric conversion efficiency of the silicon-based Topcon solar cell.

[0022] Other features and advantages of the present invention will be described in the following description, and part of them will become obvious from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0024] Figure 1 A schematic diagram of the structure of a silicon-based Topcon solar cell provided by the present invention;

[0025] Figure 2This is the XPS Ge 3d spectrum of the second n-type semiconductor layer prepared in Example 1;

[0026] Figure 3 The XPS Si 2p spectrum of the second n-type semiconductor layer prepared in Example 1;

[0027] Figure 4 This is the XPS P 2p spectrum of the second n-type semiconductor layer prepared in Example 1.

[0028] Reference numerals:

[0029] 1-back conductive electrode; 2-back dielectric layer; 3-first n-type semiconductor layer; 4-transition n-type semiconductor layer; 5-second n-type semiconductor layer; 6-tunneling oxide layer; 7-silicon wafer; 8-passivation film layer; 9-front dielectric layer; 10-front conductive electrode. DETAILED DESCRIPTION

[0030] Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present invention and are used to explain the principles of the present invention together with the embodiments of the present invention.

[0031] The present invention provides a silicon-based Topcon solar cell, see Figure 1 , including a back conductive electrode 1, a back dielectric layer 2 (for example, a silicon nitride layer or a silicon nitride oxide layer), an n-type semiconductor stack, a tunneling oxide layer 6, a silicon wafer 7 (for example, a boron diffused silicon wafer), a passivation film layer 8 (for example, an aluminum oxide film), a front dielectric layer 9 (for example, a silicon nitride layer or a silicon nitride oxide layer) and a front conductive electrode 10 stacked in sequence from the backlight surface to the light-receiving surface, wherein the n-type semiconductor stack includes a first n-type semiconductor layer 3 and a second n-type semiconductor layer 5 stacked in sequence from the tunneling oxide layer 6 to the back dielectric layer 2, the first n-type semiconductor layer 3 is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and antimony elements, the second n-type semiconductor layer 5 is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and germanium elements, and the first n-type semiconductor layer 3 and the tunneling oxide layer 6 together constitute a passivation stack.

[0032] Exemplarily, the crystallization rate of the first n-type semiconductor layer 3 is greater than 70%, for example, 80-98%, that is, the first n-type semiconductor layer 3 is mainly composed of a silicon film with a crystallization rate greater than 70%, and hydrogen, phosphorus, oxygen, carbon and antimony elements together constitute the doping elements. The crystallization rate of the second n-type semiconductor layer 5 is greater than 70%, for example, 80-98%, that is, the second n-type semiconductor layer 5 is mainly composed of a silicon film with a crystallization rate greater than 70%, and hydrogen, phosphorus, oxygen, carbon and germanium elements together constitute the doping elements.

[0033] Compared with the prior art, in the silicon-based Topcon solar cell provided by the present invention, a stacked structure is used to replace the existing single-layer structure as the back passivation, and the n-type semiconductor stack is doped with a variety of doping elements to improve the passivation performance and conductivity of the n-type semiconductor stack, thereby obtaining a silicon-based Topcon solar cell with excellent performance.

[0034] Specifically, a first n-type semiconductor layer 3 is arranged on the surface of the tunneling oxide layer 6 away from the side of the silicon wafer 7, and the first n-type semiconductor layer 3 is doped with hydrogen, phosphorus, oxygen, carbon and antimony elements. On the one hand, hydrogen atoms can bond to the dangling bonds at the interface between the silicon wafer 7 and the tunneling oxide layer, thereby enhancing the passivation effect; on the other hand, antimony elements are introduced by in-situ doping. Considering that the atomic radius of antimony elements is large, the doping of antimony elements causes a large lattice distortion in the first n-type semiconductor layer 3, and the internal stress of the first n-type semiconductor layer 3 increases, so that the diffusion rate of phosphorus atoms and the penetration probability of phosphorus atoms in the first n-type semiconductor layer 3 and the tunneling oxide layer 6 are reduced, thereby maintaining a good back passivation effect and improving the open circuit voltage and photoelectric conversion efficiency of the silicon-based Topcon solar cell; on the other hand, since the penetration probability of phosphorus atoms in the first n-type semiconductor layer 3 and the tunneling oxide layer 6 is reduced, the annealing temperature can be further increased during the preparation of the silicon-based Topcon solar cell, thereby increasing the concentration of doped atoms in the first n-type semiconductor layer 3 and improving the passivation effect.

[0035] A second n-type semiconductor layer 5 is disposed on the surface of the first n-type semiconductor layer 3 away from the silicon wafer 7, and the second n-type semiconductor layer 5 is doped with hydrogen, phosphorus, oxygen, carbon and germanium. The germanium element is introduced by in-situ doping, and the second n-type semiconductor layer 5 is doped with a small amount of germanium atoms, so that the band gap width of the second n-type semiconductor layer 5 is slightly narrowed. Due to the flattening of the Fermi level, the conduction band energy level height of the second n-type semiconductor layer 5 is slightly lower than the conduction band energy level height of the first n-type semiconductor layer 3 under high phosphorus doping conditions, which is conducive to the conduction of electrons in the second n-type semiconductor layer 5, and effectively optimizes the conductivity of the second n-type semiconductor layer 5, thereby improving the fill factor and photoelectric conversion efficiency of the silicon-based Topcon solar cell.

[0036] In order to further improve the filling factor of the silicon-based Topcon solar cell, a transitional n-type semiconductor layer 4 is stacked between the first n-type semiconductor layer 3 and the second n-type semiconductor layer 5. The transitional n-type semiconductor layer 4 is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon, antimony and germanium elements. It is formed by the diffusion of atoms between the layers during the preparation of the silicon-based Topcon solar cell. From the first n-type semiconductor layer 3 to the second n-type semiconductor layer 5, the atomic concentration of antimony atoms in the transitional n-type semiconductor layer 4 gradually decreases, and the atomic concentration of germanium atoms gradually increases. This is because the increase in the annealing temperature causes the mutual diffusion of atoms between the first n-type semiconductor layer 3 and the second n-type semiconductor layer 5, forming a gradual energy level structure at the interface between the two, which is more conducive to electron conduction and further improves the filling factor of the silicon-based Topcon solar cell.

[0037] Considering that the active phosphorus atoms play a leading role in the passivation of the first n-type semiconductor layer 3, the active antimony atoms play a leading role in slowing down the diffusion rate of the active phosphorus atoms. At the same time, the active antimony atoms can also play a passivation role together with the active phosphorus atoms. In order to ensure the passivation effect, in the first n-type semiconductor layer 3, the atomic concentration of the active phosphorus atoms is greater than the atomic concentration of the active antimony atoms.

[0038] Exemplarily, the atomic concentration of active phosphorus atoms is not less than 1E20 atoms / cm 3 , for example, 1E20~5E21atoms / cm 3 , the atomic concentration of active antimony atoms is not greater than 7E19atoms / cm 3 , for example, 1E17~7E19atoms / cm 3 .

[0039] Since the solubility of phosphorus in the tunneling oxide layer 6 is higher than that in the n-type semiconductor stack, the total phosphorus atom concentration in the tunneling oxide layer 6 is greater than the total phosphorus atom concentration in the n-type semiconductor stack, the total phosphorus atom concentration in the tunneling oxide layer 6 is greater than the total phosphorus atom concentration in the first n-type semiconductor layer 3, and the total phosphorus atom concentration in the tunneling oxide layer 6 is greater than the total phosphorus atom concentration in the second n-type semiconductor layer 5.

[0040] For example, the total phosphorus atomic concentration in the tunnel oxide layer 6 is greater than 1E21 atoms / cm 3 , for example, 1E21~8E21atoms / cm 3 .

[0041] In order to achieve a gradient setting of active antimony atoms and reduce the probability of phosphorus atoms diffusing from the first n-type semiconductor layer 3 into the tunneling oxide layer 6 , the atomic concentration of active antimony atoms in the first n-type semiconductor layer 3 gradually increases as it approaches the tunneling oxide layer 6 .

[0042] In order to reduce the conduction band energy level height of the first n-type semiconductor layer 3 and facilitate the transmission of electrons, the total atomic concentration of active phosphorus atoms and active antimony atoms gradually increases in a direction away from the tunneling oxide layer 6 .

[0043] For the second n-type semiconductor layer 5, the atomic concentration of active phosphorus atoms is greater than, equal to, or less than the atomic concentration of germanium atoms. For example, the atomic concentration of active phosphorus atoms is not less than 1E20 atoms / cm 3 , for example, 1E20~5E21atoms / cm 3 .

[0044] In order to ensure the bandgap width, the atomic number ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer 5 is not greater than 4%, for example, 0.01-4%.

[0045] In practical applications, considering both the passivation effect and the electron transmission capability, the thickness of the first n-type semiconductor layer 3 is 30 to 200 nm, the thickness of the second n-type semiconductor layer 5 is 20 to 180 nm, the thickness of the tunneling oxide layer is 1.5 to 2.0 nm (for example, 1.7 nm), the thickness of the passivation film layer 8 is 4 to 8 nm (for example, 6 nm), and the thickness of the front dielectric layer 9 is 75 to 80 nm (for example, 78 nm).

[0046] It should be noted that, for doping with other elements, the atomic concentration of oxygen in the first n-type semiconductor layer 3 is 2E18-1E20 atoms / cm 3 , the atomic concentration of carbon is greater than 2E18atoms / cm 3 , the atomic concentration of hydrogen is greater than 7E18atoms / cm 3 In the second n-type semiconductor layer 5, the atomic concentration of oxygen is 2E18 to 1E20 atoms / cm 3 The atomic concentration of carbon is greater than 2E18atoms / cm3, and the atomic concentration of hydrogen is greater than 7E18atoms / cm 3 .

[0047] The present invention also provides a method for preparing a silicon-based Topcon solar cell, which is used to prepare the above-mentioned silicon-based Topcon solar cell. The preparation method comprises the following steps:

[0048] Step 1: providing a silicon wafer 7, texturing and cleaning the silicon wafer 7, and then performing high-temperature boron diffusion on the surface of the texturing silicon wafer 7 to prepare a PN junction;

[0049] Step 2: planarizing the backlight surface of the silicon wafer 7, and sequentially preparing a tunneling oxide layer 6, an n-type semiconductor stack and a back dielectric layer 2 on the backlight surface of the silicon wafer 7;

[0050] Step 3: Clean the light-receiving surface of the silicon wafer 7 to remove the wrap-around tunneling oxide layer 6, wrap-around semiconductor stack, wrap-around back dielectric layer 2, borosilicate glass layer (BSG layer) and / or phosphosilicate glass layer (PSG layer) generated in the process of preparing the tunneling oxide layer 6, the n-type semiconductor stack and the front dielectric layer 9, and expose the light-receiving surface of the silicon wafer 7;

[0051] Step 4: sequentially preparing a passivation film layer 8 and a front dielectric layer 9 on the light-receiving surface of the silicon wafer 7;

[0052] Step 5: Silver paste is printed on the surface of the back dielectric layer 2 and the surface of the front dielectric layer 9 respectively to prepare the front conductive electrode 10 and the back conductive electrode 1. After drying, sintering and testing, a silicon-based Topcon solar cell is obtained.

[0053] Compared with the prior art, the beneficial effects of the method for preparing the silicon-based Topcon solar cell provided by the present invention are substantially the same as the beneficial effects of the silicon-based Topcon solar cell provided above, and are not described in detail herein.

[0054] Specifically, there are two ways to prepare n-type semiconductor stacks:

[0055] One method includes the following steps:

[0056] A first film layer and a second film layer are sequentially deposited on the surface of the tunnel oxide layer 6, wherein the first film layer is a silicon layer doped with hydrogen, oxygen, carbon and antimony elements, and a deposition reaction precursor of the first film layer is a mixed gas of a silicon source, triethyl antimony, methane, hydrogen and carbon dioxide; the second film layer is a silicon layer doped with hydrogen, oxygen, carbon and germanium elements, and a deposition reaction precursor of the second film layer is a mixed gas of a silicon source, germane, methane, hydrogen and carbon dioxide, and the silicon source is silane or disilane;

[0057] The first film layer and the second film layer are phosphorus diffused and activated by using a high temperature furnace tube. The phosphorus diffusion activation temperature is 820-940° C. and the phosphorus diffusion activation time is 5-120 min to obtain the first n-type semiconductor layer 3 and the second n-type semiconductor layer 5 .

[0058] Another method includes the following steps:

[0059] A first n-type semiconductor layer 3 and a second n-type semiconductor layer 5 are sequentially deposited on the surface of the tunneling oxide layer 6, wherein a deposition reaction precursor of the first n-type semiconductor layer 3 is a mixed gas of a silicon source, phosphine, triethyl antimony, methane, hydrogen and carbon dioxide, and a deposition reaction precursor of the second n-type semiconductor layer 5 is a mixed gas of a silicon source, phosphine, germane, methane, hydrogen and carbon dioxide, and the silicon source is silane or disilane;

[0060] The first n-type semiconductor layer 3 and the second n-type semiconductor layer 5 are subjected to high temperature annealing to activate phosphorus. The high temperature annealing temperature is 880-940° C. and the high temperature annealing time is 5-120 minutes.

[0061] It should be noted that in the above two methods for preparing the n-type semiconductor stack, the deposition can be carried out by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), and the deposition temperature is 200-800°C.

[0062] Embodiment 1

[0063] The main purpose of this embodiment is to characterize the chemical composition of the second n-type semiconductor layer and the feasibility of the preparation method, which includes the following steps:

[0064] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0065] Step b: polishing and cleaning the surface of the silicon wafer, wherein a potassium hydroxide alkaline solution with a mass fraction of 31% is used to isotropically etch the silicon wafer to obtain a relatively flat silicon wafer surface with a reflectivity greater than 35%;

[0066] Step c: growing tunnel oxide layers on two surfaces of the silicon wafer respectively, the thickness of the tunnel oxide layers being 1.7 nm;

[0067] Step d: depositing a second film layer on the surface of the tunnel oxide layer by PECVD, using a mixed gas of silane, germane, methane, hydrogen and carbon dioxide as a reaction precursor, and the flow ratio of SiH4:GeH4:CH4:H2:CO2 is 100:2:1:45:1, the pressure of the reaction chamber is 180Pa, the deposition temperature is 450°C, and a second film layer with a thickness of 120nm is obtained;

[0068] Step e: doping the second film layer with phosphorus using a high temperature furnace tube at a temperature of 880° C. for 120 min to obtain a second n-type semiconductor layer.

[0069] The second n-type semiconductor layer is subjected to XPS to measure its chemical composition, see Figures 2 to 4 , which respectively show the spectra of Ge 3d, Si 2p and P 2p, proving that the second n-type semiconductor layer contains germanium atoms, silicon atoms and phosphorus atoms, indicating that the second n-type semiconductor layer can be obtained by the method of this embodiment.

[0070] Embodiment 2

[0071] The main purpose of this embodiment is to characterize the passivation effect of the n-type semiconductor stack, and the steps are as follows:

[0072] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0073] Step b: polishing and cleaning the surface of the silicon wafer, wherein a potassium hydroxide alkaline solution with a mass fraction of 31% is used to isotropically etch the silicon wafer to obtain a relatively flat silicon wafer surface with a reflectivity greater than 35%;

[0074] Step c: growing tunnel oxide layers on two surfaces of the silicon wafer respectively, the thickness of the tunnel oxide layers being 1.7 nm;

[0075] Step d: Depositing the first film layer on the surface of the tunnel oxide layer by PECVD method, using a mixed gas of silane, triethylantimony, methane, hydrogen and carbon dioxide as a reaction precursor, and SiH4:C6H 15 The flow ratio of Sb:CH4:H2:CO2 was 100:0.5:1:48:0.8, the pressure of the reaction chamber was set to 220Pa, the deposition temperature was 450°C, and a first film layer with a thickness of 40nm was obtained;

[0076] Step e: depositing a second film layer on the surface of the first film layer by a PECVD method, using a mixed gas of silane, germane, methane, hydrogen and carbon dioxide as a reaction precursor, and the flow ratio of SiH4:GeH4:CH4:H2:CO2 is 100:2:1:45:1, the pressure of the reaction chamber is 180Pa, and the deposition temperature is 450°C, to obtain a second film layer with a thickness of 80nm;

[0077] Step f: using a high temperature furnace tube to perform phosphorus diffusion activation on the first film layer and the second film layer, the phosphorus diffusion activation temperature is 880° C., and the phosphorus diffusion activation time is 120 min, to obtain a first n-type semiconductor layer and a second n-type semiconductor layer.

[0078] The passivation effect test was conducted on the laminated structure obtained in this embodiment, see Table 1.

[0079] Comparative Example 1

[0080] This comparative example prepares a conventional phosphorus-doped polysilicon passivation film layer, including the following steps:

[0081] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0082] Step b: polishing and cleaning the surface of the silicon wafer, wherein a potassium hydroxide alkaline solution with a mass fraction of 31% is used to isotropically etch the silicon wafer to obtain a relatively flat silicon wafer surface with a reflectivity greater than 35%;

[0083] Step c: growing tunnel oxide layers on two surfaces of the silicon wafer respectively, the thickness of the tunnel oxide layers being 1.7 nm;

[0084] Step d: depositing a polysilicon film layer on the surface of the tunnel oxide layer by an LPCVD method, using silane gas as a reaction precursor, setting the pressure of the reaction chamber to 230 Pa, and the deposition temperature to 610° C., to obtain a polysilicon film layer with a thickness of 120 nm;

[0085] Step e: Use a high-temperature furnace tube to diffuse phosphorus into the polysilicon film layer to activate it, so that the atomic concentration of active phosphorus atoms in the polysilicon film layer reaches 4E20atoms / cm 3 above.

[0086] The passivation effect test was performed on the laminated structure obtained in this comparative example, see Table 1.

[0087] Table 1 Passivation effect of the laminated structure of Example 2 and Comparative Example 1

[0088]

[0089] It can be seen from Table 1 that the minority carrier lifetime value and the pseudo open circuit voltage of the stacked structure of Example 2 are higher than those of Comparative Example 1, and has a better passivation effect.

[0090] Embodiment 3

[0091] This embodiment provides a method for preparing a silicon-based Topcon solar cell, comprising the following steps:

[0092] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0093] Step b: texturing the surface of the silicon wafer, and preparing a PN junction by high-temperature boron diffusion on the surface of the textured silicon wafer. The square resistance after diffusion is 130Ω, wherein a sodium hydroxide alkaline solution with a mass fraction of 4% is selected to anisotropically etch the silicon wafer to obtain a textured silicon wafer surface with a reflectivity of 11.8%;

[0094] Step c: using a wet single-side etching device to etch and remove the boron-doped area on the backlight side of the silicon wafer, while retaining the borosilicate glass layer (BSG) on the light-receiving side;

[0095] Step d: growing a tunneling oxide layer on the backlight side of the silicon wafer by a furnace tube thermal oxidation method, wherein the thickness of the tunneling oxide layer is 1.7 nm;

[0096] Step e: Depositing the first film layer on the surface of the tunnel oxide layer by PECVD method, using a mixed gas of silane, triethylantimony, methane, hydrogen and carbon dioxide as a reaction precursor, and SiH4:C6H 15The flow ratio of Sb:CH4:H2:CO2 was 100:0.5:1:48:0.8, the pressure of the reaction chamber was set to 220Pa, the deposition temperature was 450°C, and a first film layer with a thickness of 40nm was obtained;

[0097] Step f: depositing a second film layer on the surface of the first film layer by a PECVD method, using a mixed gas of silane, germane, methane, hydrogen and carbon dioxide as a reaction precursor, and the flow ratio of SiH4:GeH4:CH4:H2:CO2 is 100:2:1:45:1, the pressure of the reaction chamber is 180Pa, and the deposition temperature is 450°C, to obtain a second film layer with a thickness of 80nm;

[0098] Step g: using a high temperature furnace tube to perform phosphorus diffusion activation on the first film layer and the second film layer, the phosphorus diffusion activation temperature is 840°C, the phosphorus diffusion activation time is 120min, and the first n-type semiconductor layer and the second n-type semiconductor layer are obtained, the crystallization rate of the first n-type semiconductor layer is 85%, the crystallization rate of the second n-type semiconductor layer is 85%, and the atomic concentration of active phosphorus atoms in the first n-type semiconductor layer and the second n-type semiconductor layer is 3E20atoms / cm 3 , the atomic concentration of oxygen is 8E19atoms / cm 3 , the atomic concentration of carbon is 5E19atoms / cm 3 , the atomic concentration of hydrogen is 7E20atoms / cm 3 The atomic concentration of active antimony atoms in the first n-type semiconductor layer is 3E19 atoms / cm 3 The atomic ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer is 1.5%, and the total phosphorus atomic concentration in the tunneling oxide layer is 1E21atoms / cm 3 ;

[0099] Step h: cleaning the light-receiving surface of the silicon wafer to remove the wrap-around tunneling oxide layer, wrap-around semiconductor stack, wrap-around back dielectric layer, borosilicate glass layer (BSG layer) and / or phosphosilicate glass layer (PSG layer) generated in the process of preparing the tunneling oxide layer, the n-type semiconductor stack and the front dielectric layer, and exposing the light-receiving surface of the silicon wafer;

[0100] Step i: a passivation film layer with a thickness of 8 nm and a front dielectric layer (silicon nitride layer) with a thickness of 78 nm are sequentially prepared on the light-receiving surface of the silicon wafer;

[0101] Step j: preparing a back dielectric layer (silicon nitride layer) on the surface of the second n-type semiconductor layer;

[0102] Step k: silver paste is printed on the surface of the back dielectric layer and the surface of the front dielectric layer respectively to prepare the front conductive electrode and the back conductive electrode. After drying, sintering and testing, the silicon-based Topcon solar cell of this embodiment is obtained.

[0103] See Table 2 for the performance test of the silicon-based Topcon solar cell of this embodiment.

[0104] Embodiment 4

[0105] This embodiment provides a method for preparing a silicon-based Topcon solar cell, comprising the following steps:

[0106] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0107] Step b: texturing the surface of the silicon wafer, and preparing a PN junction by high-temperature boron diffusion on the surface of the textured silicon wafer. The square resistance after diffusion is 130Ω, wherein a sodium hydroxide alkaline solution with a mass fraction of 4% is selected to anisotropically etch the silicon wafer to obtain a textured silicon wafer surface with a reflectivity of 11.8%;

[0108] Step c: using a wet single-side etching device to etch and remove the boron-doped area on the backlight side of the silicon wafer, while retaining the borosilicate glass layer (BSG) on the light-receiving side;

[0109] Step d: growing a tunneling oxide layer on the backlight side of the silicon wafer by a furnace tube thermal oxidation method, wherein the thickness of the tunneling oxide layer is 1.9 nm;

[0110] Step e: Depositing the first film layer on the surface of the tunnel oxide layer by PECVD method, using a mixed gas of silane, triethylantimony, methane, hydrogen and carbon dioxide as a reaction precursor, and SiH4:C6H 15 The flow ratio of Sb:CH4:H2:CO2 was 100:0.5:1:48:0.8, the pressure of the reaction chamber was set to 220Pa, the deposition temperature was 700°C, and the first film layer with a thickness of 180nm was obtained;

[0111] Step f: depositing a second film layer on the surface of the first film layer by a PECVD method, using a mixed gas of silane, germane, methane, hydrogen and carbon dioxide as a reaction precursor, and the flow ratio of SiH4:GeH4:CH4:H2:CO2 is 100:2:1:45:1, the pressure of the reaction chamber is 180Pa, and the deposition temperature is 700°C, to obtain a second film layer with a thickness of 170nm;

[0112] Step g: using a high temperature furnace tube to perform phosphorus diffusion activation on the first film layer and the second film layer, the phosphorus diffusion activation temperature is 890°C, the phosphorus diffusion activation time is 35 minutes, and the first n-type semiconductor layer and the second n-type semiconductor layer are obtained. The crystallization rate of the first n-type semiconductor layer is 95%, the crystallization rate of the second n-type semiconductor layer is 95%, and the atomic concentration of active phosphorus atoms in the first n-type semiconductor layer and the second n-type semiconductor layer is 5E20atoms / cm 3 , the atomic concentration of oxygen is 9E19atoms / cm 3 , the atomic concentration of carbon is 7E19atoms / cm 3 , the atomic concentration of hydrogen is 6E20atoms / cm 3 The atomic concentration of active antimony atoms in the first n-type semiconductor layer is 4E19atoms / cm 3 The atomic ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer is 1.6%, and the total phosphorus atomic concentration in the tunneling oxide layer is 7E21atoms / cm 3 ;

[0113] Step h: cleaning the light-receiving surface of the silicon wafer to remove the wrap-around tunneling oxide layer, wrap-around semiconductor stack, wrap-around back dielectric layer, borosilicate glass layer (BSG layer) and / or phosphosilicate glass layer (PSG layer) generated in the process of preparing the tunneling oxide layer, the n-type semiconductor stack and the front dielectric layer, and exposing the light-receiving surface of the silicon wafer;

[0114] Step i: a passivation film layer with a thickness of 4.5 nm and a front dielectric layer (silicon oxynitride layer) with a thickness of 75 nm are sequentially prepared on the light-receiving surface of the silicon wafer;

[0115] Step j: preparing a back dielectric layer (silicon oxynitride layer) on the surface of the second n-type semiconductor layer;

[0116] Step k: silver paste is printed on the surface of the back dielectric layer and the surface of the front dielectric layer respectively to prepare the front conductive electrode and the back conductive electrode. After drying, sintering and testing, the silicon-based Topcon solar cell of this embodiment is obtained.

[0117] See Table 2 for the performance test of the silicon-based Topcon solar cell of this embodiment.

[0118] Embodiment 5

[0119] This embodiment provides a method for preparing a silicon-based Topcon solar cell, comprising the following steps:

[0120] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0121] Step b: texturing the surface of the silicon wafer, and preparing a PN junction by high-temperature boron diffusion on the surface of the textured silicon wafer. The square resistance after diffusion is 130Ω, wherein a sodium hydroxide alkaline solution with a mass fraction of 4% is selected to anisotropically etch the silicon wafer to obtain a textured silicon wafer surface with a reflectivity of 11.8%;

[0122] Step c: using a wet single-side etching device to etch and remove the boron-doped area on the backlight side of the silicon wafer, while retaining the borosilicate glass layer (BSG) on the light-receiving side;

[0123] Step d: growing a tunneling oxide layer on the backlight side of the silicon wafer by a furnace tube thermal oxidation method, wherein the thickness of the tunneling oxide layer is 1.5 nm;

[0124] Step e: Depositing the first film layer on the surface of the tunnel oxide layer by PECVD method, using a mixed gas of silane, triethylantimony, methane, hydrogen and carbon dioxide as a reaction precursor, and SiH4:C6H 15 The flow ratio of Sb:CH4:H2:CO2 was 100:0.5:1:48:0.8, the pressure of the reaction chamber was set to 220Pa, the deposition temperature was 250°C, and the first film layer with a thickness of 90nm was obtained;

[0125] Step f: depositing a second film layer on the surface of the first film layer by a PECVD method, using a mixed gas of silane, germane, methane, hydrogen and carbon dioxide as a reaction precursor, and the flow ratio of SiH4:GeH4:CH4:H2:CO2 is 100:2:1:45:1, the pressure of the reaction chamber is 180Pa, and the deposition temperature is 250°C, to obtain a second film layer with a thickness of 110nm;

[0126] Step g: using a high temperature furnace tube to perform phosphorus diffusion activation on the first film layer and the second film layer, the phosphorus diffusion activation temperature is 930°C, the phosphorus diffusion activation time is 10 minutes, and the first n-type semiconductor layer and the second n-type semiconductor layer are obtained. The crystallization rate of the first n-type semiconductor layer is 91%, the crystallization rate of the second n-type semiconductor layer is 91%, and the atomic concentration of active phosphorus atoms in the first n-type semiconductor layer and the second n-type semiconductor layer is 6E20atoms / cm 3 , the atomic concentration of oxygen is 1E20atoms / cm 3 , the atomic concentration of carbon is 8E19atoms / cm 3 , the atomic concentration of hydrogen is 5E20atoms / cm 3 The atomic concentration of active antimony atoms in the first n-type semiconductor layer is 7E19 atoms / cm 3 The atomic ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer is 1.7%, and the total phosphorus atomic concentration in the tunneling oxide layer is 5E21atoms / cm3 ;

[0127] Step h: cleaning the light-receiving surface of the silicon wafer to remove the wrap-around tunneling oxide layer, wrap-around semiconductor stack, wrap-around back dielectric layer, borosilicate glass layer (BSG layer) and / or phosphosilicate glass layer (PSG layer) generated in the process of preparing the tunneling oxide layer, the n-type semiconductor stack and the front dielectric layer, and exposing the light-receiving surface of the silicon wafer;

[0128] Step i: a passivation film layer with a thickness of 6.5 nm and a front dielectric layer (silicon nitride layer) with a thickness of 80 nm are sequentially prepared on the light-receiving surface of the silicon wafer;

[0129] Step j: preparing a back dielectric layer (silicon nitride layer) on the surface of the second n-type semiconductor layer;

[0130] Step k: silver paste is printed on the surface of the back dielectric layer and the surface of the front dielectric layer respectively to prepare the front conductive electrode and the back conductive electrode. After drying, sintering and testing, the silicon-based Topcon solar cell of this embodiment is obtained.

[0131] See Table 2 for the performance test of the silicon-based Topcon solar cell of this embodiment.

[0132] Comparative Example 2

[0133] This comparative example provides a conventional method for preparing a silicon-based Topcon solar cell, comprising the following steps:

[0134] Step a: providing a silicon wafer, wherein the silicon wafer is a single crystal n-type silicon wafer and has a bulk resistivity of 2.0 Ω·cm;

[0135] Step b: texturing the surface of the silicon wafer, and preparing a PN junction by high-temperature boron diffusion on the surface of the textured silicon wafer. The square resistance after diffusion is 130Ω, wherein a sodium hydroxide alkaline solution with a mass fraction of 4% is selected to anisotropically etch the silicon wafer to obtain a textured silicon wafer surface with a reflectivity of 11.8%;

[0136] Step c: using a wet single-side etching device to etch and remove the boron-doped area on the backlight side of the silicon wafer, while retaining the borosilicate glass layer (BSG) on the light-receiving side;

[0137] Step d: growing a tunneling oxide layer on the backlight side of the silicon wafer by a furnace tube thermal oxidation method, wherein the thickness of the tunneling oxide layer is 1.7 nm;

[0138] Step e: depositing a polysilicon film layer on the surface of the tunnel oxide layer by an LPCVD method, using silane gas as a reaction precursor, setting the pressure of the reaction chamber to 230 Pa, and the deposition temperature to 610° C., to obtain a polysilicon film layer with a thickness of 120 nm;

[0139] Step f: Use a high temperature furnace tube to perform phosphorus diffusion activation on the polysilicon film layer. The phosphorus diffusion activation temperature is 880°C and the phosphorus diffusion activation time is 120 minutes, so that the atomic concentration of active phosphorus atoms in the polysilicon film layer reaches 4E20atoms / cm 3 above;

[0140] Step g: cleaning the light-receiving surface of the silicon wafer to remove the wrap-around tunneling oxide layer, wrap-around semiconductor stack, wrap-around back dielectric layer, borosilicate glass layer (BSG layer) and / or phosphosilicate glass layer (PSG layer) generated in the process of preparing the tunneling oxide layer, the n-type semiconductor stack and the front dielectric layer, and exposing the light-receiving surface of the silicon wafer;

[0141] Step h: sequentially preparing a passivation film layer with a thickness of 8 nm and a front dielectric layer (silicon nitride layer) with a thickness of 78 nm on the light-receiving surface of the silicon wafer;

[0142] Step i: preparing a back dielectric layer (silicon nitride layer) on the surface of the polysilicon film layer;

[0143] Step j: Silver paste is printed on the surface of the back dielectric layer and the surface of the front dielectric layer respectively to prepare the front conductive electrode and the back conductive electrode. After drying, sintering and testing, the silicon-based Topcon solar cell of this comparative example is obtained.

[0144] See Table 2 for the performance test of the silicon-based Topcon solar cell of this comparative example.

[0145] Table 2 Performance parameters of silicon-based Topcon solar cells of Example 3 and Comparative Example 2

[0146]

[0147]

[0148] Note: The parameters of Examples 3 to 5 in the above table are converted into percentages based on the parameters of Comparative Example 2.

[0149] It can be seen from Table 2 that the open circuit voltage, fill factor and photoelectric conversion efficiency of the silicon-based Topcon solar cells of Examples 3 to 5 are higher than those of Comparative Example 2, and the series resistance is lower than that of Comparative Example 2. Examples 3 to 5 have better electrical properties.

[0150] It should be noted that in the above embodiments and comparative examples, the crystallization rate is calculated as follows: the peaks of crystalline silicon and amorphous silicon are measured respectively by laser Raman spectroscopy, the peaks of crystalline silicon and amorphous silicon are integrated, the contents of crystalline silicon and amorphous silicon are calculated, and then the crystallization rate is calculated.

[0151] The calculation method of the atomic number ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer is as follows: the second n-type semiconductor layer is tested by secondary ion mass spectrometry to obtain the number of germanium atoms and the number of silicon atoms, and then the atomic number ratio of germanium atoms to silicon atoms in the second n-type semiconductor layer is calculated.

[0152] For the atomic concentration test of elements, the atomic concentrations of C, H, O and total phosphorus were measured using secondary ion mass spectrometry, and the active phosphorus atomic concentration was measured using an ECV tester. The doping concentration distribution was measured using the electrochemical capacitance-voltage method.

[0153] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A silicon-based Topcon solar cell, characterized in that: It includes a tunneling oxide layer, a first n-type semiconductor layer and a second n-type semiconductor layer which are sequentially stacked on the backlight surface of the silicon wafer; The first n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and antimony elements, and the second n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon and germanium elements.

2. The silicon-based Topcon solar cell according to claim 1, characterized in that: The atomic concentration of active antimony atoms in the first n-type semiconductor layer is not greater than 7E19 atoms / cm 3 .

3. The silicon-based Topcon solar cell according to claim 1, characterized in that: In the second n-type semiconductor layer, the atomic concentration of active phosphorus atoms is not less than 1E20 atoms / cm 3 , the atomic number ratio of germanium atoms to silicon atoms is not greater than 4%.

4. The silicon-based Topcon solar cell according to claim 1, characterized in that: A transitional n-type semiconductor layer is stacked between the first n-type semiconductor layer and the second n-type semiconductor layer. The transitional n-type semiconductor layer is a silicon layer doped with hydrogen, phosphorus, oxygen, carbon, antimony and germanium.

5. The silicon-based Topcon solar cell according to claim 1, characterized in that: In the first n-type semiconductor layer, the atomic concentration of active phosphorus atoms is greater than the atomic concentration of active antimony atoms.

6. The silicon-based Topcon solar cell according to claim 1, characterized in that: The total phosphorus atomic concentration in the tunneling oxide layer is greater than the total phosphorus atomic concentration in the first n-type semiconductor layer and the second n-type semiconductor layer; and / or, the total phosphorus atomic concentration in the tunneling oxide layer is greater than the total phosphorus atomic concentration in the first n-type semiconductor layer; And / or, the total phosphorus atomic concentration in the tunneling oxide layer is greater than the total phosphorus atomic concentration in the second n-type semiconductor layer.

7. The silicon-based Topcon solar cell according to claim 1, characterized in that: The atomic concentration of active antimony atoms in the first n-type semiconductor layer gradually increases in a direction gradually approaching the tunnel oxide layer; And / or, the total atomic concentration of active phosphorus atoms and active antimony atoms in the first n-type semiconductor layer gradually increases in a direction gradually moving away from the tunnel oxide layer.

8. The silicon-based Topcon solar cell according to any one of claims 1 to 7, characterized in that: The thickness of the first n-type semiconductor layer is 30 to 200 nm; and / or, the thickness of the second n-type semiconductor layer is 20 to 180 nm; And / or, the thickness of the tunneling oxide layer is 1.5-2.0 nm.

9. A method for preparing a silicon-based Topcon solar cell, characterized in that: For preparing the silicon-based Topcon solar cell according to any one of claims 1 to 8, the preparation method comprises the following steps: Providing a silicon wafer; A tunneling oxide layer, a first n-type semiconductor layer and a second n-type semiconductor layer are prepared on the backlight surface of the silicon wafer.

10. The method for preparing a silicon-based Topcon solar cell according to claim 9, characterized in that: During the preparation of the first n-type semiconductor layer and the second n-type semiconductor layer, the activation temperature of phosphorus atoms in the first n-type semiconductor layer and the second n-type semiconductor layer is 820-940°C.

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