Power amplifier

Abstract

The amplifier (Trc, Trp) uses a GaN HEMT. A diode linearizer (LNZ) and a variable attenuator (VATT) are connected in series with the inputs of the amplifiers (Trc, Trp). A peak detector (DET) detects the peak value of the drain voltage of the amplifiers (Trc, Trp). When the peak value exceeds a threshold value, the control unit (CTL) causes the diode linearizer (LNZ) to function as a linearizer and reduces the amount of attenuation of the variable attenuator (VATT).

Description

Technical Field

[0001] The present disclosure relates to power amplifiers. Background Art

[0002] In power amplifiers used in mobile phone base stations such as the fourth generation (4G) and fifth generation (5G) mobile communication systems, high output and high linearity are required to transmit radio waves with less distortion, i.e. signals with a low bit error rate when received, to remote locations. In addition, high efficiency is strongly required to reduce the power consumption of the base station itself.

[0003] In order to meet this requirement, the power amplifier used in the current mobile phone base station adopts a Doherty amplifier that can achieve high-efficiency operation even at an average output power that is 7-9dB lower than the peak output power. Compared with the general single-chain amplifier, the Doherty amplifier can greatly improve the efficiency during the back-off operation. However, the linearity of the output signal relative to the input signal, that is, the relationship between the input and output of the amplitude and phase characteristics is linear and degrades. Therefore, by placing a digital pre-distorter (DPD: Digital Pre-distorter) in front of the amplifier and pre-inputting the reverse characteristics of the distorted components in the amplifier into the amplifier, the amplification operation is performed while compensating for the degradation of linearity. This compensation is performed while monitoring the output signal of the amplifier in sequence through a coupler (directional coupler). In order to make the reverse characteristic component to be input to the amplifier have an appropriate amplitude and phase, the DPD has an analog attenuator, an analog phase shifter or equivalent functions as needed in addition to the digital signal processing function and the digital / analog conversion function.

[0004] As transistors used in power amplifiers for base stations, Si-LDMOS has been the mainstream so far. However, with the actual use of GaN HEMT, GaN HEMTs that can operate at a power supply voltage of 40-50V, which is higher than 28V of LDMOS, and can operate more efficiently, have begun to be used. In particular, GaN HEMTs are mostly used in Doherty power amplifiers for 5G base stations in the 3-4GHz band with a frequency higher than the 2GHz band (for example, refer to Patent Document 1).

[0005] GaN Doherty power amplifiers have a problem that the memory effect caused by the notch in the GaN HEMT is strong, and the current amplification state varies depending on the past amplification state. For example, it is known that if a smaller power is amplified immediately after a larger power is amplified, the gain or phase will change.

[0006] In order to suppress signal distortion by taking this memory effect into account, distortion compensation is performed by taking the memory effect into account in the DPD used in the base station. However, in product development, there are often cases where distortion compensation does not work well even if this DPD is used. For example, the amplitude characteristics (AM-AM) and phase characteristics (AM-PM) between the input and output of the Doherty power amplifier change sharply or the amount of change is large within a certain output power range. Therefore, the circuit is designed so that the DPD compensation works well, the amount of change falls within the specified range, and the change becomes gentle.

[0007] The inventors have experienced the following disadvantage in the design and evaluation of a Doherty power amplifier: although the DPD functions as designed in most of a desired frequency band, the DPD does not function well near the end of the frequency band.

[0008] According to the results of various analyses, this is a memory effect caused by the instantaneous drain voltage of the GaN HEMT. As mentioned above, the case where DPD cannot perform distortion compensation well is the case where the change in the amplitude characteristic (AM-AM) and phase characteristic (AM-PM) between the input and output exceeds the compensation range. Among them, the limit on the compensation amount relative to the change in the phase characteristic is strict. Therefore, in the case of a large change in the phase characteristic, it is effective to install a phase change suppression function in the power amplifier to suppress the phase change and suppress it within the compensation range based on DPD (for example, refer to Patent Document 1).

[0009] The diode linearizer is suitable for inexpensively implementing such a function in a power amplifier. Since the diode linearizer can slowly change the amplitude and phase of the signal according to the input power, changes in the amplitude and phase can be suppressed.

[0010] Patent Document 1: Japanese Patent Application Publication No. 2001-103100

[0011] However, since the operation principle is different due to the loss when the diode linearizer functions and when it does not function, the operation gain of the power amplifier changes. Therefore, there is a problem that the difference in the operation gain of the power amplifier product becomes large. Summary of the invention

[0012] The present disclosure is made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a power amplifier capable of reducing gain variation.

[0013] The power amplifier disclosed in the present invention is characterized by comprising: an amplifier using a GaN HEMT; a diode linearizer and a variable attenuator connected in series to an input of the amplifier; a peak detector detecting a peak value of a drain voltage of the amplifier; and a control unit causing the diode linearizer to function as a linearizer and reducing an attenuation amount of the variable attenuator when the peak value exceeds a threshold value.

[0014] In the present disclosure, a diode linearizer and a variable attenuator are connected in series to the input of an amplifier, and when the peak value of the drain voltage of the amplifier exceeds a threshold value, the diode linearizer is made to function. Thus, even when the digital predistorter cannot perform distortion compensation well due to the memory effect caused by the instantaneous drain voltage of the amplifier, the linearizer can suppress the degradation of linearity. Therefore, through the distortion compensation of the digital predistorter, the distortion characteristics generally required by the base station can be satisfied. In addition, when the diode linearizer functions, the gain is reduced, so the attenuation of the variable attenuator is reduced. Thus, the gain variation of the power amplifier can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a circuit diagram showing a power amplifier according to the first embodiment.

[0016] Figure 2 is a circuit diagram representing a linearizer.

[0017] Figure 3 This is a diagram showing the AM-AM / AM-PM characteristics of a diode linearizer when it functions as a linearizer.

[0018] Figure 4 This is a diagram showing the AM-AM / AM-PM characteristics of a diode linearizer when it does not function as a linearizer.

[0019] Figure 5 is a circuit diagram showing a variable attenuator.

[0020] Figure 6 It is a diagram showing an example of RF characteristics of a variable attenuator.

[0021] Figure 7 is a circuit diagram showing a peak detector.

[0022] Figure 8 This is a circuit diagram showing a control unit.

[0023] Fig. 9 It is a diagram showing a characteristic example of a peak detector and a control unit.

[0024] Fig.10 It is a diagram showing a characteristic example of the control unit.

[0025] Fig.11 It is a diagram showing a characteristic example of the control unit.

[0026] Fig.12 2 is a diagram showing an output example of voltages Vo2a and Vo2b.

[0027] Fig.13 is a circuit diagram showing a power amplifier of a comparative example.

[0028] Fig.14 This is a diagram showing the signal space of 64QAM (64 Quadrature Modulation) used in 4G.

[0029] Fig.15 It is a diagram showing the signal space of 256QAM (256 Quadrature Modulation).

[0030] Fig.16 The diagram shows the time waveforms of 12 subcarriers with a frequency interval of 15 kHz, which is the basis of OFDM (Orthogonal Frequency Division Multiplexing) of 4G.

[0031] Fig.17 This is a diagram showing an example of a synthesized waveform of 12 subcarriers.

[0032] Fig.18 FIG. 2 is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier according to a comparative example when there is no problem.

[0033] Fig.19 FIG. 2 is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier according to a comparative example when there is no problem.

[0034] Fig. 20 FIG. 2 is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier according to a comparative example when a problem exists.

[0035] Fig.21 FIG. 2 is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier according to a comparative example when a problem exists.

[0036] Fig. 22 This is a diagram showing simulation results of the AM-AM transition amount with respect to the peak value of the drain voltage of a GaN HEMT alone.

[0037] Fig.23 This is a diagram showing simulation results of the AM-PM transition amount with respect to the peak value of the drain voltage of a GaN HEMT alone.

[0038] Fig.24 FIG. 1 is a diagram showing an example of a setup for measuring a transient response delay of a drain current after application of a stress voltage pulse.

[0039] Fig.25 FIG. 4 is a diagram showing a drain voltage waveform when a stress voltage pulse is applied.

[0040] Fig.26 It means Fig.25 Figure 2. The corresponding transient response waveform of the drain current.

[0041] Fig. 27 It is a diagram for explaining the influence of a pre-linearizer on AM-AM / AM-PM.

[0042] Fig.28 This is a diagram showing the gain when there is no variable attenuator.

[0043] Fig.29 It is a diagram showing the gain when a variable attenuator is provided.

[0044] Fig.30 This is a circuit diagram showing a power amplifier according to the second embodiment.

[0045] Fig.31 This is a circuit diagram showing a power amplifier according to a third embodiment.

[0046] Fig.32 This is a circuit diagram showing a power amplifier according to a fourth embodiment. DETAILED DESCRIPTION

[0047] The power amplifier according to the embodiment will be described with reference to the drawings. The same reference numerals are used for the same or corresponding components, and overlapping descriptions may be omitted.

[0048] Implementation method 1.

[0049] Figure 1 : This is a circuit diagram of a power amplifier according to Embodiment 1. The power amplifier module PAM is a GaN HEMT Doherty power amplifier module mainly used in mobile phone base stations. The output signal of the power amplifier module PAM is linearly distorted relative to the input signal. Therefore, a digital pre-distorter (Digital Pre-distorter) DPD that performs distortion compensation is connected to the input terminal PAIN of the power amplifier module PAM. The directional coupler CPL is connected to the output terminal PAOUT of the power amplifier module PAM. The digital pre-distorter DPD monitors the output signal of the power amplifier module PAM using the directional coupler CPL, and pre-inputs the reverse characteristics of the distorted component in the amplifier of the power amplifier module PAM into the power amplifier module PAM. Thus, the amplification operation is performed while compensating for linear degradation.

[0050] In the power amplifier module PAM, the carrier amplifier Trc and the peak amplifier Trp connected in parallel to each other constitute a Doherty amplifier. The driver amplifier Trd is connected to the input of the Doherty amplifier. GaN HEMTs are used as the carrier amplifier Trc, the peak amplifier Trp, and the driver amplifier Trd.

[0051] The input matching section INM is connected to the gate of the driving amplifier Trd. The power distribution section DIS divides the output signal of the driving amplifier Trd and inputs it to the gate of the carrier amplifier Trc and the gate of the peak amplifier Trp respectively. The power distribution section DIS also functions as an inter-stage matching section.

[0052] Line TRL1 is connected between the power distribution unit DIS and the gate of the peak amplifier Trp. Line TRL2 is connected between the drain of the carrier amplifier Trc and the drain of the peak amplifier Trp. Line TRL3 is connected between the drain of the peak amplifier Trp and the output terminal PAOUT. Line TRL4 is connected between the drain of the carrier amplifier Trc and the power supply terminal Vdd. Capacitor Co1 is shunt-connected to the connection point between line TRL4 and the power supply terminal Vdd. Line TRL5 is connected between the drain of the peak amplifier Trp and the power supply terminal Vdd. Capacitor Co2 is shunt-connected to the connection point between line TRL5 and the power supply terminal Vdd. Line TRL6 is connected between the drain of the drive amplifier Trd and the power supply terminal Vdd. Capacitor Co3 is shunt-connected to the connection point between line TRL6 and the power supply terminal Vdd. Lines TRL1 to TRL6 change the phase by 90° to convert the impedance. For example, line TRL3 converts the signal impedance obtained by power-combining the output signal of the carrier amplifier Trc and the output signal of the peak amplifier Trp into an output impedance of 50Ω.

[0053] Line TRL4 is a power supply line that applies a 90° phase rotation relative to the fundamental frequency fo. Capacitor Co is a bypass capacitor used to make the impedance of the power supply terminal Vdd sufficiently low near the fundamental frequency fo and to make it almost short-circuited. As a result, the impedance of the power supply line is estimated from the drain of the carrier amplifier Trc to become sufficiently high near the fundamental frequency fo. Therefore, the power supply line is not affected by the high frequency of the drain of the carrier amplifier Trc. The same is true for the power supply lines of the peak amplifier Trp and the drive amplifier Trd.

[0054] The drain voltages of the carrier amplifier Trc, the peak amplifier Trp, and the driver amplifier Trd pulsate at the fundamental frequency fo, and their average value is the power supply voltage. However, the instantaneous voltage is determined by the load impedance of the transistor, and varies greatly from a minimum value of about 0.5 to 2V to a maximum value of about 2 to 2.5 times the power supply voltage. The coupling capacitor Cc1 monitors the drain voltage of the carrier amplifier Trc. The peak detector DET detects the peak value of the drain voltage of the carrier amplifier Trc monitored by the coupling capacitor Cc1.

[0055] The diode linearizer LNZ and the variable attenuator VATT are connected in series between the input terminal PAIN and the input matching unit INM. The control unit CTL generates voltages Vo2a and Vo2b based on the output voltage Vo1 of the peak detector DET and supplies them to the diode linearizer LNZ and the variable attenuator VATT, respectively.

[0056] Figure 2 : is a circuit diagram showing a linearizer. The diode linearizer LNZ is a series-type diode linearizer in which a diode D1 is provided in series in an RF signal path. The capacitor C1 is connected to the anode of the diode D1, and the capacitor C2 is connected to the cathode. The capacitor C3 is connected in parallel with the diode D1. The anode of the diode D1 is connected to the terminal V1 via the inductor L1. The cathode of the diode D1 is grounded via the inductor L2. The voltage Vo2a is applied to the terminal V1 of the diode linearizer LNZ.

[0057] Figure 3 This is a diagram showing the AM-AM / AM-PM characteristics of the diode linearizer when it functions as a linearizer. When the current Idio flowing to the diode D1 is small (for example, 3 mA), as the input power Pin increases, the gain Gp decreases and the phase advances in the positive direction. Therefore, the gain and phase of the signal passing through the diode linearizer LNZ near the desired Pin change. Therefore, the diode linearizer LNZ functions as a linearizer near the desired Pin.

[0058] Figure 4 This is a diagram showing the AM-AM / AM-PM characteristics of the diode linearizer when it does not function as a linearizer. When the current Idio flowing through the diode D1 is large (e.g., 10 mA), the gain and phase of the signal passing through the diode linearizer LNZ near the desired pin do not change. Therefore, the diode linearizer LNZ does not function as a linearizer near the desired pin.

[0059] Therefore, if the voltage Vo2a is large and a large amount of current flows to the diode D1, the input power level at which the diode linearizer LNZ functions as a linearizer becomes high. Therefore, when the diode linearizer LNZ functions as a linearizer within the desired input power range, the voltage Vo2a is set to a low Vo2aL to allow an appropriate amount of current to flow to the diode D1. However, if the voltage does not exceed the Schottky barrier Vbi (0.7-0.8V) of the diode D1, the current Idio does not flow, so Vo2aL>Vbi is set. On the other hand, if the voltage Vo2a is a high Vo2aH, a large amount of current flows to the diode D1, and the diode linearizer LNZ does not function as a linearizer. In addition, when the diode linearizer LNZ functions as a linearizer, the gain Gp decreases, and when it does not function, the gain Gp increases. In addition, even when the diode linearizer LNZ does not function, it is affected by the insertion loss equivalent to the on-resistance of the diode D1, so the gain Gp of the amplifier is slightly lower than when there is no diode linearizer LNZ.

[0060] Figure 5 : is a circuit diagram showing a variable attenuator. The variable attenuator VATT is a π-type FET attenuator. The drain of the transistor FET1 is connected to the input terminal IN via the capacitor C3, and the source is connected to the output terminal OUT via the capacitor C4. The resistor R1 and the inductor L3 are connected in parallel to the source and drain of the transistor FET1. The gate of the transistor FET1 is grounded via the resistor R2. The drain of the transistor FET1 is connected to the drain of the transistor FET2 via the capacitor C5 and the resistor R3. The source of the transistor FET1 is connected to the drain of the transistor FET3 via the capacitor C6 and the resistor R4. The source of the transistor FET2 is grounded via the capacitor C7. The source of the transistor FET3 is grounded via the capacitor C8. The voltage Vo2b is applied to the terminal V2, and is divided by the variable resistor R5 and the resistor R6 to generate the voltage Vc. The voltage Vc is applied to the source of the transistor FET1 via the resistor R7, to the gate of the transistor FET2 via the resistor R8, and to the gate of the transistor FET3 via the resistor R9. The terminal V2 is connected to the source of the transistor FET2 via the resistor R10 , and is connected to the source of the transistor FET3 via the resistor R11 .

[0061] When the voltage Vo2b is 0V, the voltage Vc also becomes 0V. In this case, the gate-source voltage of FET1 also becomes 0V. If the threshold of FET1, FET2, and FET3 is -2V, FET1 is turned on. Therefore, most of the RF signal passes through FET1 instead of resistor R1, and the insertion loss becomes only the on-resistance between the drain and source of FET1, and the loss is small. In addition, the gate-source voltage of FET2 and FET3 becomes 0V, and FET2 and FET3 are completely turned on. Therefore, a π-type attenuator composed of resistors R1, R2, and R3 is equivalently formed.

[0062] On the other hand, the higher the voltage Vo2b is, the higher the voltage Vc becomes in the positive direction. In this case, since the source potential of FET1 becomes higher in the positive direction, the gate-source voltage becomes larger in the negative direction. Therefore, the channel resistance between the drain and source of FET1 becomes larger, so FET1 is close to being disconnected. In this case, most of the RF signal passes through the resistor R1, and the attenuation becomes larger. When the voltage Vo2b is a certain positive voltage, the attenuation amount becomes the maximum, for example, it becomes about 14dB.

[0063] When the voltage Vo2b is +6V, the voltage dividing ratio of the variable resistor R5 and the resistor R6 is set to 1:1, and the voltage Vc becomes +3V. Since the gate voltage of FET1 is fixed at 0V, the gate-source voltage of FET1 becomes -3V, and FET1 is turned off. The gate-source voltage of FET2 and FET3 becomes -3V, and FET2 and FET3 are turned off. Therefore, the power leaked to GND through the resistors R3 and R4 is also minimized.

[0064] As described above, the attenuation amount of the variable attenuator VATT is changed according to the magnitude of the voltage Vo2b. Specifically, the higher the voltage Vo2b is, the greater the attenuation amount of the RF signal passing through the variable attenuator VATT is.

[0065] Figure 6 This is a diagram showing an example of the RF characteristics of a variable attenuator. It can be seen that the variable attenuator VATT can normally keep the attenuation and phase change constant regardless of the increase in the input power Pin. In addition, even when the variable attenuator VATT is not activated, the signal is affected by the series resistance of the FET when passing through the series FET, resulting in an insertion loss of about 0.2-0.3dB.

[0066] Figure 7is a circuit diagram showing a peak detector. The peak detector DET is an RC circuit having a time constant appropriately set in combination with the time constant of the modulation wave. A drain voltage Vin is input to the + terminal of the operational amplifier OP1. An output voltage Vo1 is output from the operational amplifier OP1 via a diode D2. The output voltage is also input to the - terminal of the operational amplifier OP1. Capacitor C9 and resistor R12 are shunt-connected to the output of the operational amplifier OP1. With this structure, the peak detector DET maintains the peak value of the drain voltage. In addition, a source follower can also be used for the operational amplifier OP1. In particular, a source follower is preferred at high frequencies.

[0067] Figure 8 : is a circuit diagram showing a control unit. In the control unit CTL, the operational amplifier OP2 compares the output voltage Vo1 of the peak detector DET with the predetermined threshold value Va to generate an output voltage Vo2. The inverter INV1 inverts the output voltage Vo2 to generate a voltage Vo2a and supplies it to the diode linearizer LNZ. The inverter INV2 inverts the voltage Vo2 to generate a voltage Vo2b and supplies it to the variable attenuator VATT. Since the desired voltage levels of the diode linearizer LNZ and the variable attenuator VATT are often different, the inverter INV1 and the inverter INV2 shift the voltage Vo2 level to an appropriate voltage level to generate voltages Vo2a and Vo2b. The voltages Vo2a and Vo2b are binary values ​​of high level or low level.

[0068] Fig. 9 : is a diagram showing a characteristic example of a peak detector and a control unit. When the voltage Vo1 (drain voltage Vin) is greater than the threshold value Va, the voltage Vo2a obtained by inverting the voltage Vo2 becomes a low level Vo2aL. When the voltage Vo1 (drain voltage Vin) is less than the threshold value Va, the voltage Vo2a becomes a high level Vo2aH. Therefore, by setting the threshold value Va to an appropriate value, it is possible to detect a situation where the peak value of the drain voltage is too high.

[0069] Fig.10 and Fig.11 It is a diagram showing a characteristic example of the control unit. Fig.10 This is the case where the output voltage Vo2 suddenly switches between a high level (High) and a low level (Low) when Vo1 changes relative to the threshold value Va. Fig.11 This is the case where the output voltage Vo2 changes slowly. As described later, since the modulation signal increases and decreases quite sharply from several MHz to 100 MHz, in order to avoid the sharp action of the variable attenuator VATT and the diode linearizer LNZ and maintain the continuity of the signal response, a relatively slow response of Vo2 is more suitable.

[0070] Fig.121 is a diagram showing an output example of voltages Vo2a and Vo2b. When voltage Vo1 is lower than threshold value Va, voltages Vo2a and Vo2b become high level Vo2aH and Vo2bH. When voltage Vo1 is higher than threshold value Va, voltages Vo2a and Vo2b become low level Vo2aL and Vo2bL.

[0071] When the voltage Vo2a is at a low level, the insertion loss of the diode linearizer LNZ increases, but since the voltage Vo2b is at a low level, the attenuation of the variable attenuator VATT decreases. On the other hand, when the voltage Vo2a is at a high level, the insertion loss of the diode linearizer LNZ decreases, but since the voltage Vo2b is at a high level, the attenuation of the variable attenuator VATT increases. That is, when the peak value of the drain voltage of the carrier amplifier Trc exceeds the threshold value Va, the control unit CTL causes the diode linearizer LNZ to function as a linearizer and reduces the attenuation of the variable attenuator VATT. On the other hand, when the peak value of the drain voltage of the carrier amplifier Trc is less than the threshold value Va, the control unit CTL causes the diode linearizer LNZ not to function as a linearizer and increases the attenuation of the variable attenuator VATT.

[0072] When the insertion loss of the diode linearizer LNZ at the desired pin when it functions as a linearizer is set to A (dB), and the insertion loss when it does not function as a linearizer is set to A0 (dB), and for the sake of simplicity, the minimum attenuation of the variable attenuator VATT is set to 0 dB, then when the diode linearizer LNZ does not function as a linearizer, the attenuation of the variable attenuator VATT can be set to |A-A0| (dB). In addition, A and A0 are negative values ​​when converted to dB.

[0073] As described above, the control unit CTL controls the diode linearizer LNZ so that the gain and phase of the signal passing through the diode linearizer LNZ are changed when the peak value of the drain voltage exceeds the threshold value, and the gain and phase of the signal passing through the diode linearizer LNZ are not changed when the peak value of the drain voltage does not exceed the threshold value. In addition, the control unit CTL controls the variable attenuator VATT so that the attenuation amount of the signal passing through the variable attenuator VATT when the peak value of the drain voltage exceeds the threshold value is smaller than the attenuation amount of the signal passing through the variable attenuator VATT when the peak value of the drain voltage does not exceed the threshold value.

[0074] Next, the effects of the present embodiment will be described in comparison with the comparative example. Fig.132 is a circuit diagram showing a power amplifier of a comparative example. Compared with the first embodiment, the comparative example does not include a coupling capacitor Cc1, a peak detector DET, a control unit CTL, a diode linearizer LNZ, and a variable attenuator VATT.

[0075] Here, in 4G and 5G, in the case of a modulation bandwidth of 20MHz, the number of subcarriers is 12×100=1200. Since the value of 64 is 2 to the sixth power, 6 bits can be sent at a time using one subcarrier. Therefore, 1200×6 bits=7.2k bits. Since one subcarrier sends 14000 symbols per second, 7.2k×14000=about 100Mbit / sec can be sent in a 20MHz band. Fig.14 This is a diagram showing the signal space of 64QAM (64-value quadrature modulation) used in 4G. Fig.15 This is a diagram showing the signal space of 256QAM (256-value quadrature modulation). The amplitude and phase of the carrier are changed simultaneously so that the amplitude and phase of the carrier are at the positions of the points of the diagram, and the information is carried.

[0076] In 64QAM, the amplitude changes from the center O to the I-ch direction to ±1, ±3, ±5, ±7, and changes similarly in the Q-ch direction. For example, the value A represents an amplitude of sqrt(7^2+7^2)=sqrt(49*2)=sqrt(2)·7 and a modulation value of a phase of 45°. The value B represents an amplitude of sqrt(3^2+1^2)=sqrt(10) and a modulation value of a phase of approximately 18°. In addition, since I-ch and Q-ch correspond to the relationship between cos and sin, in order to obtain the value of A, the amplitude of the cos carrier is set to +7, and the amplitude of the sin carrier is set to +7 (+7·cos(ωt)-(+7)·sin(ωt)). Similarly, to obtain the value of B, the amplitude of the cosine carrier wave is set to 3, and the amplitude of the sinine carrier wave is set to 1 (+3·cos(ωt)-(+1)·sin(ωt)). Such modulation is performed on each of the 12 subcarriers.

[0077] Fig.16 The diagram shows the time waveforms of 12 subcarriers with a frequency interval of 15 kHz, which is the basis of OFDM (Orthogonal Frequency Division Multiplexing) of 4G. Fig.17 This is a diagram showing an example of a synthesized waveform of 12 subcarriers. Fig.14 and Fig.15 The modulation shown is applied to Fig.16 The number of subcarriers actually used is 1024 in the 20MHz modulation bandwidth of 4G. Fig.17The difference between the peak value and the average value of the signal waveform shown becomes very large, usually a large difference of 8-10 dB. The dynamic range, which is the difference between the maximum value and the minimum value included in the signal, is close to 30 dB.

[0078] Thus, in order to accurately demodulate 1024 subcarriers modulated by 64QAM or 256QAM, it is necessary to accurately transmit the wireless Fig.14 and Fig.15 Therefore, the amplifier is required to have extremely high linearity, that is, linear amplification over a wide range of input amplitude and phase.

[0079] An example of AM-AM / AM-PM characteristics when such a modulated signal is input to a power amplifier of a comparative example will be described. Fig.18 and Fig.19 : is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier of a comparative example without any problem. Fig.18 No distortion compensation based on digital predistorter DPD is performed in Fig.19 It is known that if distortion compensation by the digital predistorter DPD is appropriately performed, the AM-AM / AM-PM characteristics become a flat linear operation in a wide dynamic range.

[0080] Next, the inconveniences encountered by the inventors are described. Fig. 20 and Fig.21 : is a diagram showing an example of AM-AM / AM-PM characteristics of a power amplifier of a comparative example in the case where a problem exists. Fig. 20 No distortion compensation based on digital predistorter DPD is performed in Fig.21 Distortion compensation is performed in Fig. 20 In the figure, AM-AM becomes a rather steep upward-right characteristic, and the change in AM-PM is Fig.18 Therefore, even after distortion compensation, it is not Fig.19 The straight line system shown is Fig.21 The AM-AM / AM-PM characteristics shown have a certain degree of width. Therefore, it can be seen that the distortion compensation by the digital predistorter DPD is not properly implemented.

[0081] In the case of steep and large gain changes, or phase changes such as Fig. 20 However, in most of the desired frequency band, such Fig.19 Distortion compensation is performed appropriately as shown in FIG. 1 , whereas only near the end of the frequency band, as shown in FIG. Fig. 20 and Fig.21 An undesirable situation occurs as shown.

[0082] Therefore, we suspected factors other than circuit design and investigated the factors. As a result, we experimentally confirmed that when a modulated wave is input to a GaN HEMT single body with the power supply impedance and load impedance set to be the same as those in the amplifier module, a larger amplitude shift and phase shift will occur as the input power level increases.

[0083] Fig. 22 This is a diagram showing simulation results of the AM-AM transition amount with respect to the peak value of the drain voltage of a GaN HEMT alone. Fig.23 This is a diagram showing the simulation results of the AM-PM shift amount relative to the peak value of the drain voltage of a GaN HEMT single body. Through simulation analysis, it was confirmed that these shift amounts strongly depend on the peak value of the drain voltage. From this, the inventors speculate that the transient response delay of the drain current after the stress voltage pulse application, which is a phenomenon often observed in GaN HEMTs at the frequencies at the end of the band, occurs significantly.

[0084] An example of the transient response delay of the drain current will be described below. Fig.24 This is a diagram showing an example of a setting for measuring the transient response delay of the drain current after the stress voltage pulse is applied. The gate voltage Vg is set so that a certain drain current Id flows. The drain voltage Vd is temporarily pulse-raised from a certain level, such as the power supply voltage of the amplifier Tr, to a higher voltage, and then returns to the original voltage. Fig.25 FIG. 4 is a diagram showing a drain voltage waveform when a stress voltage pulse is applied. Fig.26 It means Fig.25 The corresponding transient response waveform of the drain current is shown in Figure 1. Fig.25 and Fig.26 As shown, it can be seen that the drain current rises faster shortly after the low drain voltage stress, but the drain current rises slower shortly after the high drain voltage stress.

[0085] When amplifying multiple subcarriers after multi-level modulation at the same time, the drain voltage of the GaN HEMT occasionally produces a very high peak output as described above. At this time, it is presumed that if the transient response of the drain current becomes slow, the drain current will not rise, such as Fig. 20 and Fig.21 As shown in FIG. 1 , at low input power, the gain becomes low and the phase change in the dynamic range becomes large. In other words, it is presumed that since the peak output voltage is too high, an AM-AM or AM-PM offset cannot be compensated by the digital predistorter DPD. Therefore, it is presumed that the factor that hinders the distortion compensation by the digital predistorter DPD is the memory effect caused by the transient response of the drain current.

[0086] The problem is to suppress the change of AM-AM / AM-PM to the extent that the distortion compensation based on the digital predistorter DPD can function properly. Therefore, it is possible to consider using a circuit that can compensate AM-AM / AM-PM with a simple circuit structure. Figure 2 The diode linearizer shown is placed before the power amplifier module. The inventors experimentally confirmed that the suppression of AM-PM deviations in particular is important for properly implementing distortion compensation based on a digital predistorter DPD.

[0087] Fig. 27 This is a diagram for explaining the influence of the pre-linearizer on AM-AM / AM-PM. It can be seen that the change of AM-AM / AM-PM is suppressed by the compensation of the linearizer. Therefore, in the power amplifier with the diode linearizer LNZ in front, the distortion compensation based on the digital predistorter DPD works properly, and it can be expected that the desired frequency band can be achieved. Fig.19 Implementation of the features shown.

[0088] However, when observing Fig. 27 When studying the characteristics of PAM with linearizer, it was noted that the amplifier gain (linear gain) decreases when the output power Pout is low. This becomes a problem when the power amplifier is considered as a product because the gain of the product changes depending on whether the diode linearizer LNZ is activated. The gain difference varies depending on the compensation amount of AM-AM / AM-PM based on the diode linearizer LNZ, but it produces a gain difference of about 2-3dB.

[0089] In this embodiment, in order to suppress this gain difference, a variable attenuator VATT is installed in the power amplifier. Fig.28 This is a diagram showing the gain when there is no variable attenuator. When there is no variable attenuator VATT, a large gain deviation occurs depending on whether the diode linearizer LNZ is activated or not. Fig.29 This is a diagram showing the gain when a variable attenuator is provided. When the diode linearizer LNZ is not activated, the gain becomes higher than when the diode linearizer LNZ is activated. Therefore, when the diode linearizer LNZ is not activated, the attenuation amount of the variable attenuator VATT is increased. Thus, the gain can be made constant regardless of whether the diode linearizer LNZ is activated or not.

[0090] As described above, in this embodiment, the diode linearizer and the variable attenuator are connected in series to the input of the amplifier, and when the peak value of the drain voltage of the amplifier exceeds the threshold value, the diode linearizer is made to function. Thus, even when the digital predistorter cannot perform distortion compensation well due to the memory effect caused by the instantaneous drain voltage of the amplifier, the linearizer can suppress the degradation of linearity. Therefore, through the distortion compensation of the digital predistorter, the distortion characteristics generally required by the base station can be satisfied. In addition, when the diode linearizer functions, the gain is reduced, so the attenuation amount of the variable attenuator is reduced. Thus, the gain variation of the power amplifier can be reduced.

[0091] In addition, since the diode linearizer LNZ and the variable attenuator VATT are very simple analog circuits, they can be implemented not only by GaN HEMT but also by GaAs FET / HEMT, which is suitable for miniaturization and low cost. In addition, since the same structure can be realized using IV group Si series semiconductors, the power amplifier of this embodiment is not limited to the III-V group system.

[0092] In Patent Document 1, the drain voltage of the FET of the power amplifier is also monitored, and the phase shifter compensates for AM-PM accordingly. However, if the analog circuit is used as a premise, AM-AM also changes while AM-PM is compensated. Therefore, the compensation effect of this embodiment that compensates for both is greater. In addition, the gain deviation caused by the activation or non-activation of the diode linearizer LNZ can also be suppressed.

[0093] In addition, as an actual power amplifier for base stations, the Doherty amplifier is the mainstream, but the same phenomenon occurs due to the notch effect of the transistor itself, and even in amplifiers other than the Doherty amplifier, the digital predistorter cannot perform distortion compensation. Therefore, this embodiment is also effective when the amplifier is not a Doherty amplifier.

[0094] Implementation method 2.

[0095] Fig.30 : is a circuit diagram of a power amplifier according to Embodiment 2. In Embodiment 1, the peak value of the drain voltage of the carrier amplifier Trc of the Doherty amplifier is detected, but in this embodiment, the peak value of the drain voltage of the peak amplifier Trp is detected. The other structures are the same as those in Embodiment 1. In this case, the same effect as in Embodiment 1 can also be obtained.

[0096] Implementation method 3.

[0097] Fig.31: is a circuit diagram showing a power amplifier according to Embodiment 3. In Embodiment 1, the peak value of the drain voltage of the carrier amplifier Trc of the Doherty amplifier is detected, but in this embodiment, the peak value of the drain voltage of the drive amplifier Trd is detected. The other structures are the same as those in Embodiment 1.

[0098] Normally, the peak value of the drain voltage of the final-stage carrier amplifier Trc is higher than the peak value of the drain voltage of the driver amplifier Trd. However, depending on the circuit design, the peak value of the drain voltage of the GaN HEMT of the driver amplifier Trd becomes too high, which becomes a major factor in delaying the transient response characteristics of the drain current. In this case, this embodiment is effective and can obtain the same effect as that of the first embodiment.

[0099] In addition, Fig.31 Although there is only one driver amplifier Trd, one driver amplifier Trd may be provided for the carrier amplifier Trc and one driver amplifier Trd may be provided for the peak amplifier Trp. In this case, the same effect as that of the first embodiment can be obtained by monitoring the drain voltage of the driver amplifier Trd on the carrier amplifier Trc side.

[0100] Implementation method 4.

[0101] Fig.32 : is a circuit diagram showing a power amplifier of Embodiment 4. In this embodiment, the peak detector DET1 detects the peak value of the drain voltage of the carrier amplifier Trc of the Doherty amplifier, and the peak detector DET2 detects the peak value of the drain voltage of the driver amplifier Trd. Then, the comparator COM selects the higher voltage and supplies it to the control unit CTL. The control unit CTL applies a control voltage to the diode linearizer LNZ and the variable attenuator VATT according to the output signal of the comparator COM. The other structures are the same as those of Embodiment 1, and the same effects as those of Embodiment 1 can be obtained.

[0102] Description of Reference Numerals

[0103] CTL…control unit; CPL…directional coupler; DET, DET1, DET2…peak detector; DPD…digital predistorter; LNZ…diode linearizer; Trc…carrier amplifier; Trd…driver amplifier; Trp…peak amplifier; VATT…variable attenuator.

Claims

1. A power amplifier, characterized in that: have: amplifiers, which use GaN HEMTs; a diode linearizer and a variable attenuator connected in series with the input of the amplifier; a peak detector that detects a peak value of a drain voltage of the amplifier; as well as The control unit causes the diode linearizer to function as a linearizer and reduces the attenuation amount of the variable attenuator when the peak value exceeds a threshold value.

2. The power amplifier according to claim 1, characterized in that: The control unit controls the diode linearizer in such a manner that, when the peak value exceeds a threshold value, the gain and phase of the signal passing through the diode linearizer are changed, and when the peak value does not exceed the threshold value, the gain and phase of the signal passing through the diode linearizer are not changed. The control unit controls the variable attenuator so that the attenuation amount of the signal passing through the variable attenuator when the peak value exceeds a threshold value is smaller than the attenuation amount of the signal passing through the variable attenuator when the peak value does not exceed the threshold value.

3. The power amplifier according to claim 1 or 2, characterized in that: have: a directional coupler connected to the output of the amplifier; and A digital predistorter monitors the output signal of the amplifier by means of the directional coupler and inputs the inverse characteristic of the component distorted in the amplifier into the amplifier in advance.

4. The power amplifier according to any one of claims 1 to 3, characterized in that: The amplifier has a Doherty amplifier.

5. The power amplifier according to claim 4, characterized in that: The Doherty amplifier comprises: a carrier amplifier and a peak amplifier connected in parallel to each other, The peak detector detects a peak value of a drain voltage of the carrier amplifier.

6. The power amplifier according to claim 4, characterized in that: The Doherty amplifier comprises: a carrier amplifier and a peak amplifier connected in parallel to each other, The peak detector detects a peak value of a drain voltage of the peak amplifier.

7. The power amplifier according to claim 4, characterized in that: The amplifier has a driver amplifier connected to an input of the Doherty amplifier, The peak detector detects a peak value of a drain voltage of the driver amplifier.

8. The power amplifier according to claim 4, characterized in that: The Doherty amplifier comprises: a carrier amplifier and a peak amplifier connected in parallel to each other, The amplifier has a driver amplifier connected to an input of the Doherty amplifier, The peak detector detects a peak value of the drain voltage of the carrier amplifier and a peak value of the drain voltage of the driver amplifier, and selects a higher voltage to provide to the control unit.

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