Real-time debugging method and device for monitoring internal signals of FPGA (Field Programmable Gate Array)

Abstract

The invention provides a real-time debugging method for monitoring internal signals of a field programmable gate array (FPGA), which comprises the following steps of: creating a VIO kernel and embedding the VIO kernel into a user circuit; the upper computer inputs an instruction to the user circuit through the JTAG interface, the JTAG control module of the VIO kernel receives the instruction, stores and analyzes the instruction, and inputs the instruction to the instruction analysis module according to an instruction analysis result to carry out instruction splitting and latching operation; an instruction splitting result is sent to a control information processing module for execution, and parameters of an enable signal, a VIO kernel instruction and an output instruction are sent to an execution module for execution according to an instruction execution result; after the execution module completes corresponding work, the state of the JTAG interface continues to jump backwards, all the modules do not act in the transmission process, and when the JTAG enters a signal sending state, the output arbitration module sends a sampling result to the JTAG interface to be output. The invention further provides a real-time debugging device for monitoring the internal signals of the FPGA.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a real-time debugging method and device for monitoring internal signals of FPGA. Background Art

[0002] Field Programmable Gate Array (FPGA) is a large-scale programmable device that solves the problem of customized circuits. Users can describe the required functions through hardware description language, and then compile the description language into a bit stream file through software to finally configure the FPGA. Field Programmable Gate Array (FPGA) has the advantages of being programmable, reconfigurable, and easy to use, and is widely used in various fields.

[0003] The complete design process of FPGA (field programmable gate array) includes major steps such as circuit design and input, functional simulation, synthesis, implementation, layout and routing, board-level verification and debugging.

[0004] In the existing technology, when designing FPGA, users need to add or modify stimulus signals during board-level verification and debugging, or even add board-level IO interfaces. After the modification, the project needs to be re-performed with logic synthesis, wiring, layout, timing analysis, and bitstream generation. As the scale of FPGA continues to expand and internal resources continue to increase, the circuit modules developed by engineers are also gradually becoming larger. The above process will increase the complexity of debugging and bring great time costs.

[0005] Therefore, it is necessary to develop a new real-time debugging method and device that can monitor the internal signals of FPGA, which can drive and monitor the internal signals of FPGA in real time without recompiling the code and reconfiguring the FPGA, so as to improve the debugging efficiency. Summary of the invention

[0006] The present invention provides a real-time debugging method and device for monitoring FPGA internal signals, which can embed a virtual input and output interface in a user circuit, allowing the user to drive and monitor the FPGA internal signals in real time through a user interface without recompiling codes and reconfiguring the FPGA, thereby improving the user's design capability and debugging efficiency.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above purposes or other purposes, a real-time debugging method for monitoring FPGA internal signals provided by a technical solution of the present invention includes creating a VIO kernel and embedding it into a user circuit; the host computer inputs instructions to the user circuit through a JTAG interface, the JTAG control module of the VIO kernel receives the instructions, stores and analyzes the instructions, and inputs the instructions to the instruction parsing module for instruction splitting and latching operations according to the instruction analysis results; the instruction splitting results are sent to the control information processing module for execution, and the enable signal, VIO kernel instructions, and output instruction parameters are sent to the execution module for execution according to the instruction execution results; after the execution module completes the corresponding work, the JTAG interface state continues to jump backward, and the modules do not act during the transmission process. When JTAG enters the signal sending state, the output arbitration module sends the sampling results to the JTAG interface for output. Compared with the prior art, the present invention embeds a virtual input and output interface in the user circuit, and the bit width and number of the interface are customized by the user, allowing the user to drive and monitor the internal signals of the FPGA in real time through the user interface, without recompiling the code and reconfiguring the FPGA, thereby improving the user's design ability and debugging efficiency. The generated VIO core is integrated with the user circuit, and layout and routing are performed to generate a user circuit with a VIO function, and the generated bit stream file is configured into the FPGA.

[0009] A VIO kernel is created in the user interface and embedded into the user circuit. After the VIO kernel is created, the corresponding register transfer level code is generated.

[0010] After the VIO core receives the instruction, when it is determined that the latch value of the instruction is the corresponding synchronization header, the VIO core enable signal is pulled high and distributed to the input instruction parsing module and the execution module.

[0011] The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instructions; the VIO signal output monitoring module is used for executing output signal refresh instructions, output signal sending instructions and output signal reset instructions.

[0012] When multiple VIO cores embedded in the user circuit are instantiated at the same time, the output arbitration module arbitrates the output order, polls the VIO windows of the JTAG interface that need to upload data, and uploads the data of the next VIO window after the data upload of the next VIO window is completed; if there is no uploaded data, it is skipped until all VIO windows have been polled.

[0013] According to the debugging requirements of the user, any of the VIO cores can be instantiated multiple times, and each instantiation will generate a new window on the host computer. All window output data of the host computer are polled and output by the output arbitration module.

[0014] Another technical solution of the present invention provides a real-time debugging device for monitoring internal signals of FPGA, including: a VIO core embedded in a user circuit, the VIO core is provided with a JTAG status module and a JTAG control module, the JTAG status module and the JTAG control module receive signals input through the JTAG interface, and input the processing results to an input instruction parsing module; the input instruction parsing module is used for splitting and latching input instructions; a VIO function control module, including a control information processing module that receives the splitting results output by the input instruction parsing module and an execution module responsible for instruction execution; an output arbitration module, the VIO core communicates with the JTAG output interface through the output arbitration polling module, and when JTAG enters the signal sending state, the output of the execution module is sent to the JTAG interface.

[0015] The control information processing module determines the specific execution instructions of the VIO kernel, and sends the relevant enable signals, VIO instructions and output instruction parameters to the execution module; the execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instructions; the VIO signal output monitoring module is used for executing output signal refresh instructions, output signal sending instructions and output signal reset instructions.

[0016] When the VIO signal input monitoring module receives an input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module, and processes and sends the sampling result to the output arbitration module.

[0017] When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, and sends the sampling result to the output arbitration module after processing; when the VIO signal output monitoring module receives an output signal sending instruction, it sends the output parameters set by the user interface to the user circuit, and drives the target circuit connected to the user circuit; when the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value generated by the VIO core to the user circuit.

[0018] When the multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output sequence of the multiple VIO cores.

[0019] The number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The VIO core of the present invention can be used for debugging and fault reproduction, and is efficient and flexible when used. At the same time, it can drive and monitor the user circuit in real time, and the parameters can be configured, which is easy to use. There is no need to perform logic synthesis and layout wiring multiple times, which can greatly reduce the time cost and improve the efficiency of debugging and fault reproduction.

[0021] 2. The user circuit embedded in the VIO core of the present invention can set the number of channels and signal bit width, and can operate on multi-bit signals simultaneously during use. Different VIO cores can be instantiated and used at the same time, and the same VIO core also supports multiple instantiations.

[0022] 3. The VIO core circuit structure in the present invention is flexible. During use, the JTAG interface can be reused with other functional circuits, and the JTAG interface can be polled to communicate with the host computer.

[0023] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a design diagram of the real-time debugging device for monitoring internal signals of FPGA according to the present invention. DETAILED DESCRIPTION

[0026] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0027] Example 1 Embodiment 1 provides a real-time debugging method for monitoring internal signals of FPGA, including creating a VIO kernel (the VIO (Virtual Input Output, VIO) kernel here is a virtual input and output kernel, which is mainly used to monitor and drive internal FPGA signals in real time), and embedding it into a user circuit, a host computer inputs instructions to the user circuit through a JTAG interface, a JTAG control module of the VIO kernel receives instructions, stores and analyzes the instructions, and inputs the instructions to an instruction parsing module for instruction splitting and latching operations according to the instruction analysis results; the instruction splitting results are sent to a control information processing module for execution, and the enable signal, the VIO kernel instruction, and the parameters of the output instruction are sent to an execution module for execution according to the instruction execution results; after the execution module completes the corresponding work, the JTAG interface state continues to jump backward, and the modules do not act during the transmission process. When JTAG enters the signal sending state, the output arbitration module sends the sampling results to the JTAG interface for output.

[0028] The technical solution of the present invention is specifically explained below: The created VIO kernel is embedded into the user circuit. For specific embedding strategies, please refer to Figure 1 The design diagram of the real-time debugging device for monitoring the internal signals of the FPGA; multiple VIO cores can be set and can be embedded in the user circuit together with other functional circuits. The VIO cores and the VIO cores and other functional circuits use the JTAG interface to input and output data. In order to facilitate user operation, the user can operate the user interface to create a VIO core. When the VIO core is created, the corresponding register transfer level code for the VIO core will be generated. After the VIO core is created, the generated VIO core and the user circuit are integrated, laid out and wired, and a user circuit with VIO function is generated, and the generated bitstream file is configured in the FPGA.

[0029] The user directly operates the user interface, and the host computer sends the corresponding instructions to the user circuit through JTAG. After the VIO core in the user circuit receives the instructions, it stores the instructions. When the latch value of the instruction is judged to be the corresponding synchronization header, the VIO core enable signal is pulled high and distributed to the input instruction parsing module and the execution module.

[0030] The input instruction parsing module will split and latch the JTAG input instructions, and send the split results to the control information processing module. The control information processing module determines the specific execution instructions of the VIO core and sends the relevant enable signals, VIO instructions, and output instruction specific parameters to the subsequent execution modules.

[0031] The execution module includes a VIO signal output monitoring module and a VIO signal output monitoring module; the VIO signal input monitoring module is used for input signal refresh instructions. When the VIO signal input monitoring module receives the input signal refresh instruction, it will sample the target circuit connected to the VIO signal input monitoring module and process the sampling results and send them to the output arbitration module for output selection; The VIO signal output monitoring module is used to execute output signal refresh instructions, output signal sending instructions and output signal reset instructions. When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, and sends the sampling result to the output arbitration module after processing; when the VIO signal output monitoring module receives an output signal sending instruction, it sends the output parameters set by the user interface to the user circuit to drive the target circuit connected to the user circuit; when the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value generated by the VIO kernel to the user circuit.

[0032] When the execution module completes the corresponding work, the JTAG interface state will continue to jump backwards. During the signal transmission process, each module will not act. When JTAG enters the signal sending state, the output arbitration module will send the sampling result to the JTAG interface.

[0033] As an implementation method, when multiple VIO cores are embedded in the user circuit in this embodiment 1 and are instantiated (configured) at the same time, the output arbitration module arbitrates the output order, polls the VIO windows of the JTAG interface that need to upload data, and uploads the data of the next VIO window after the data upload of the next VIO window is completed; if there is no uploaded data, it is skipped and the above operation steps are repeated until all VIO windows have been polled.

[0034] As an implementation method, any VIO core in this embodiment 1 can be instantiated multiple times. According to the user's debugging requirements, any VIO core can be instantiated (configured) multiple times. Each instantiation will generate a new window in the host computer, and all window output data of the host computer are polled and output by the output arbitration module.

[0035] Through the method in Example 1, the real-time monitoring / driving of the target circuit is achieved by adding a VIO core (virtual input / output circuit). At the same time, the technical solution of this embodiment supports the simultaneous use of multiple windows, supports the characteristics of multi-channel and multi-bit signal operation of user circuits, supports compatibility with other functional circuits, and can reproduce faults in multi-parameter circuits, saving logic synthesis and layout and routing time.

[0036] Example 2 Embodiment 2 provides a real-time debugging device for monitoring internal signals of FPGA, including: a VIO core embedded in a user circuit, the VIO core is provided with a JTAG status module and a JTAG control module, the JTAG status module and the JTAG control module receive signals input through the JTAG interface, and input the processing results to the input instruction parsing module; the input instruction parsing module is used for splitting and latching the input instructions; there is also a VIO function control module, including a control information processing module that receives the splitting results output by the input instruction parsing module and an execution module responsible for instruction execution; and an output arbitration module, the VIO core communicates with the JTAG output interface through the output arbitration polling module, and when JTAG enters the signal sending state, the output of the execution module is sent to the JTAG interface.

[0037] The following is combined with Figure 1 The real-time debugging device for monitoring the internal signal of FPGA in this embodiment 2 is specifically described as follows: See also Figure 1 The real-time debugging device for monitoring the internal signal of FPGA of the present invention includes creating a VIO kernel embedded in the user circuit, and the VIO kernel includes a JTAG status module and a JTAG control module. The JTAG status module and the JTAG control module receive signals input through the JTAG interface, and the input signals include a user monitoring signal and a user clock signal, and input the processing results to the input instruction parsing module.

[0038] The input instruction parsing module is used for splitting and latching input instructions. The input instruction parsing module generates control information containing the splitting results by splitting the instructions. The control information is sent to the VIO function control module. The specific VIO function control module includes a control information processing module that directly receives the control information and an execution module responsible for instruction execution.

[0039] The control information processing module determines the specific execution instructions of the VIO kernel and sends the relevant enable signals, VIO instructions and output instruction parameters to the execution module.

[0040] The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module. The VIO signal input monitoring module is used to input a signal refresh instruction. After receiving the input signal refresh instruction, the VIO signal input monitoring module will sample the target circuit connected to the VIO signal input monitoring module and process the sampling result (that is, Figure 1 The refresh input value Refresh_input value generated in is sent to the output arbitration module; The VIO signal output monitoring module is used to execute output signal refresh instructions, output signal sending instructions and output signal reset instructions. When the VIO signal output monitoring module receives the output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module and processes the sampling results (that is, Figure 1 The refresh output value Refresh_ontput value output to the JTAG interface is sent to the output arbitration module; When the VIO signal output monitoring module receives the output signal sending instruction, it sends the output signal value commit_output_valuse set by the user interface to the user circuit to drive the connected target circuit; When the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value reset_output_en generated by the set VIO core to the user circuit.

[0041] As well as the output arbitration module, the VIO core communicates with the JTAG output interface through the output arbitration polling module, and when JTAG enters the signal sending state, the output of the execution module is sent to the JTAG interface.

[0042] Since the VIO module communicates with the JTAG interface through polling of the output arbitration module, it can be used in conjunction with other functional circuits that use the JTAG interface, leaving room for the subsequent addition of new IP cores.

[0043] As an implementation manner, when multiple VIO cores are embedded in a user circuit, the output arbitration module arbitrates the output sequence of the multiple VIO cores.

[0044] As an implementation manner, the number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

[0045] The above is a detailed introduction to a multi-threaded microcode control circuit for a chip provided by the present invention. The structure and working principle of the present invention are described in detail using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, the present invention can also be improved and modified without departing from the principle of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A real-time debugging method for monitoring internal signals of FPGA, characterized in that: This includes creating a VIO kernel and embedding it into the user circuit; The host computer inputs instructions to the user circuit through the JTAG interface, and the JTAG control module of the VIO core receives the instructions, stores and analyzes the instructions, and inputs the instructions to the instruction parsing module for instruction splitting and latching operations according to the instruction analysis results; The instruction splitting result is sent to the control information processing module for execution, and according to the instruction execution result, the enable signal, VIO kernel instruction, and output instruction parameters are sent to the execution module for execution; After the execution module completes the corresponding work, the JTAG interface state continues to jump backwards. During the transmission process, each module does not act. When JTAG enters the signal sending state, the output arbitration module sends the sampling result to the JTAG interface for output.

2. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: The generated VIO core is integrated with the user circuit, and layout and routing are performed to generate a user circuit with a VIO function, and the generated bit stream file is configured into the FPGA.

3. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: A VIO kernel is created in the user interface and embedded into the user circuit. After the VIO kernel is created, the corresponding register transfer level code is generated.

4. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: After the VIO core receives the instruction, when it is determined that the latch value of the instruction is the corresponding synchronization header, the VIO core enable signal is pulled high and distributed to the input instruction parsing module and the execution module.

5. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; The VIO signal input monitoring module is used for inputting signal refresh instructions; The VIO signal output monitoring module is used to execute output signal refresh instructions, output signal sending instructions and output signal reset instructions.

6. A real-time debugging method for monitoring FPGA internal signals according to claim 1, characterized in that: When multiple VIO cores embedded in the user circuit are instantiated at the same time, the output arbitration module arbitrates the output order, polls the VIO windows of the JTAG interface that need to upload data, and uploads the data of the next VIO window after the data upload of the next VIO window is completed; If there is no upload data, skip it until all VIO windows have been polled.

7. A real-time debugging method for monitoring FPGA internal signals according to claim 6, characterized in that: According to the debugging requirements of the user, any of the VIO cores can be instantiated multiple times, and each instantiation will generate a new window on the host computer. All window output data of the host computer are polled and output by the output arbitration module.

8. A real-time debugging device for monitoring internal signals of FPGA, characterized in that: include: A VIO core embedded in the user circuit, wherein the VIO core is provided with a JTAG status module and a JTAG control module, wherein the JTAG status module and the JTAG control module receive signals input through the JTAG interface and input processing results to the input instruction parsing module; The input instruction parsing module is used for splitting and latching the input instructions; A VIO function control module, including a control information processing module for receiving the splitting result output by the input instruction parsing module and an execution module responsible for instruction execution; Output arbitration module, the VIO core communicates with the JTAG output interface through the output arbitration polling module, and when JTAG enters the signal sending state, the output of the execution module is sent to the JTAG interface.

9. A real-time debugging device for monitoring internal signals of FPGA according to claim 8, characterized in that: The control information processing module determines the specific execution instruction of the VIO kernel, and sends the relevant enable signal, VIO instruction and output instruction parameters to the execution module; The execution module includes a VIO signal input monitoring module and a VIO signal output monitoring module; The VIO signal input monitoring module is used for inputting signal refresh instructions; The VIO signal output monitoring module is used to execute output signal refresh instructions, output signal sending instructions and output signal reset instructions.

10. A real-time debugging device for monitoring internal signals of FPGA according to claim 9, characterized in that: When the VIO signal input monitoring module receives an input signal refresh instruction, it samples the target circuit connected to the VIO signal input monitoring module, and processes and sends the sampling result to the output arbitration module.

11. A real-time debugging device for monitoring internal signals of FPGA according to claim 9, characterized in that: When the VIO signal output monitoring module receives an output signal refresh, it samples the target circuit connected to the VIO signal output monitoring module, and processes the sampling result and sends it to the output arbitration module; When the VIO signal output monitoring module receives the output signal sending instruction, it sends the output parameters set by the user interface to the user circuit and drives the target circuit connected to the user circuit; When the VIO signal output monitoring module receives an output reset instruction, the VIO signal output monitoring module will send the default value generated by the VIO core to the user circuit.

12. A real-time debugging device for monitoring internal signals of FPGA according to claim 8, characterized in that: When the multiple VIO cores are embedded in the user circuit, the output arbitration module arbitrates the output sequence of the multiple VIO cores.

13. A real-time debugging device for monitoring internal signals of FPGA according to claim 9, characterized in that: The number of input signal ports of the VIO signal input monitoring module and the number of output signal ports of the VIO signal output monitoring module support multiple groups, and the bit width range of each group of signals is 1-32 bits.

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