Semiconductor packaging structure and forming method thereof

Abstract

The invention relates to the field of semiconductor packaging, and provides a semiconductor packaging structure and a forming method thereof, and the method comprises the steps: providing a glass substrate which is provided with a plurality of discrete glass through hole interconnection structures; an inorganic dielectric layer and a first interconnection structure located in the inorganic dielectric layer are formed on the upper surface of a glass substrate through the BEOL technology in the front-end manufacturing process of a semiconductor, and the density of the formed first interconnection structure is larger than that of a second interconnection structure formed on the lower surface of the glass substrate subsequently. The feature size of the first interconnection structure is smaller than that of a subsequently formed second interconnection structure; forming an organic passivation layer and a second interconnection structure located in the organic passivation layer on the lower surface of the glass substrate by adopting an RDL process in a semiconductor back-end process; and mounting at least one first semiconductor chip on the upper surface of the inorganic dielectric layer. The method improves the wiring density of the first interconnection structure on the upper surface of the glass substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] The most common packaging substrate is an organic material substrate. Organic material substrates are easy to process and can transmit signals at high speed. They have always been regarded as leaders in the chip field. However, organic material substrates also have some disadvantages. For example, the thermal expansion coefficient of organic material substrates and chips is too different. At high temperatures, the connection point between the chip and the organic material substrate is easy to disconnect, making the chip easy to burn. In addition, the size of the organic substrate is greatly limited, and it cannot accommodate too many chips within the limited size.

[0003] In this context, glass substrates came into being. Glass substrates have ultra-low flatness (extremely flat), better thermal stability and mechanical stability. Because the glass material is very flat, it can improve the focus depth of lithography. Under the same area, the number of openings is much more than that on the organic material substrate, so that the spacing between the formed through-glass vias (Through Glass Via) can be less than 100 microns, which can directly increase the interconnection density between chips by 10 times. In addition, the thermal expansion coefficient of the glass substrate is closer to that of the chip, and the higher temperature tolerance can reduce deformation by 50%, which can reduce the risk of fracture at the connection point and increase the reliability of the chip. In addition, compared with traditional organic material substrates, glass substrates not only have lower power consumption, but also faster signal transmission speed, and the thickness of the glass substrate can be reduced by about half. These advantages make glass substrates an ideal choice for the next generation of high-density packaging, capable of building higher-performance multi-chip packaging structures.

[0004] When glass substrates are currently used for packaging, resin materials (such as ABF resin) are usually used to cover metal wires for wiring. This wiring method reduces the density of metal wires used for interconnection, thereby limiting the number of external ports of chips that are suitable for electrical connection with the metal wires, which is not conducive to improving the performance of the packaging structure. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a semiconductor packaging structure and a method for forming the same, so as to improve the wiring density in the packaging process based on the glass substrate and improve the performance of the packaging structure based on the glass substrate.

[0006] To this end, the present application first provides a method for forming a semiconductor packaging structure, comprising: Providing a glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively; An inorganic dielectric layer and a first interconnect structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate, the first interconnect structure is electrically connected to the upper end surface of the through-glass via interconnect structure, and the inorganic dielectric layer and the first interconnect structure are manufactured by a BEOL process in a semiconductor front-end process, the density of the formed first interconnect structure is greater than the density of a second interconnect structure subsequently formed on the lower surface of the glass substrate, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the second interconnect structure subsequently formed; An organic passivation layer and a second interconnection structure located in the organic passivation layer are formed on the lower surface of the glass substrate, the second interconnection structure is electrically connected to the lower end surface of the through-glass hole interconnection structure, and the organic passivation layer and the second interconnection structure are manufactured by using an RDL process in a semiconductor back-end process; At least one first semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the first semiconductor chip is electrically connected to the first interconnection structure.

[0007] In an optional embodiment, the present invention further includes: forming a plurality of discrete first welding protrusions on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the second interconnect structure.

[0008] In an optional embodiment, the glass substrate serves as a transfer plate; the forming method further includes: providing a packaging substrate, welding the first welding protrusion to the upper surface of the packaging substrate; and forming a plurality of discrete second welding protrusions on the lower surface of the packaging substrate.

[0009] In an optional embodiment, the first interconnect structure includes one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the second interconnect structure is a rewiring layer.

[0010] In an optional embodiment, the inorganic dielectric layer is a single-layer or multi-layer stacked structure, and the first interconnect structure is correspondingly a single-layer or multi-layer stacked structure.

[0011] In an optional embodiment, the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnect structure and the second interconnect structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0012] In an optional embodiment, the characteristic size of the first interconnect structure is 0.2-0.8 microns, and the characteristic size of the second interconnect structure is 1.5-2.5 microns.

[0013] In an optional embodiment, a bridge chip is provided, wherein the bridge chip has a wiring layer, and the density of the wiring layer is greater than the density of the first interconnect structure; the formation method further includes: burying the bridge chip in the inorganic dielectric layer, and the wiring layer on the bridge chip is electrically connected to a portion of the first interconnect structure.

[0014] In an optional embodiment, the inorganic dielectric layer includes a first inorganic dielectric layer located on the upper surface of a glass substrate and a second inorganic dielectric layer located on the upper surface of the first inorganic dielectric layer, and the first interconnection structure includes a first sub-interconnection structure and a second sub-interconnection structure electrically connected to the first sub-interconnection structure; the process of forming the inorganic dielectric layer and the first interconnection structure includes: forming a first inorganic dielectric layer on the upper surface of the glass substrate; forming a first sub-interconnection structure in the first inorganic dielectric layer; forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; and forming a second sub-interconnection structure in the second inorganic dielectric layer.

[0015] In an optional embodiment, the formation method further includes: providing a semiconductor chip without internal wiring, the semiconductor chip without internal wiring comprising a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, the device layer having semiconductor devices; burying the semiconductor chip without internal wiring before or after forming the first sub-interconnect structure in the first inorganic dielectric layer; after burying the semiconductor chip without internal wiring, forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; while forming the second sub-interconnect structure in the second inorganic dielectric layer, forming a third interconnect structure in the second inorganic dielectric layer, the density of the third interconnect structure is greater than or equal to the density of the first interconnect structure, the third interconnect structure is electrically connected to the semiconductor devices in the device layer of the semiconductor chip without internal wiring, and part of the third interconnect structure is also electrically connected to part of the first interconnect structure, the semiconductor chip without internal wiring, the third interconnect structure and part of the second inorganic dielectric layer constitute a second semiconductor chip.

[0016] In an optional embodiment, the device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, and the conductive connection structure is electrically connected to the third interconnection structure.

[0017] In an optional embodiment, the semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

[0018] In an optional embodiment, the semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

[0019] The present application also provides a semiconductor packaging structure, comprising: A glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively; an inorganic dielectric layer located on the upper surface of the glass substrate and a first interconnect structure located in the inorganic dielectric layer, wherein the first interconnect structure is electrically connected to the upper end surface of the through-glass via interconnect structure; an organic passivation layer located on the lower surface of the glass substrate and a second interconnect structure located in the organic passivation layer, wherein the density of the first interconnect structure is greater than the density of the second interconnect structure, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the second interconnect structure; At least one first semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the first semiconductor chip is electrically connected to the first interconnection structure.

[0020] In an optional embodiment, it further includes: a plurality of discrete first welding protrusions located on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the second interconnect structure.

[0021] In an optional embodiment, the glass substrate serves as a transfer plate; the packaging structure further includes: a packaging substrate, wherein the first welding protrusion is welded to the upper surface of the packaging substrate; and a plurality of discrete second welding protrusions are formed on the lower surface of the packaging substrate.

[0022] In an optional embodiment, the first interconnect structure includes one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the second interconnect structure is a rewiring layer.

[0023] In an optional embodiment, the inorganic dielectric layer is a single-layer or multi-layer stacked structure, and the first interconnect structure is correspondingly a single-layer or multi-layer stacked structure; the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnect structure and the second interconnect structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0024] In an optional embodiment, the characteristic size of the first interconnect structure is 0.2-0.8 microns, the characteristic size of the second interconnect structure is 1.5-2.5 microns, and the inorganic dielectric layer and the first interconnect structure are formed by the BEOL process in the semiconductor front-end process, and the organic passivation layer and the second interconnect structure are formed by the RDL process in the semiconductor back-end process.

[0025] In an optional embodiment, the packaging structure also includes: a bridge chip, the bridge chip having a wiring layer, the density of the wiring layer is greater than the density of the first interconnect structure, the bridge chip is buried in the inorganic dielectric layer, and the wiring layer on the bridge chip is electrically connected to a portion of the first interconnect structure.

[0026] In an optional embodiment, the inorganic dielectric layer includes a first inorganic dielectric layer located on the upper surface of the glass substrate and a second inorganic dielectric layer located on the upper surface of the first inorganic dielectric layer, and the first interconnection structure includes a first sub-interconnection structure located in the first inorganic dielectric layer and a second sub-interconnection structure located in the second inorganic dielectric layer and electrically connected to the first sub-interconnection structure.

[0027] In an optional embodiment, the packaging structure also includes: a semiconductor chip without internal wiring, the semiconductor chip without internal wiring includes a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, the device layer has a semiconductor device; the semiconductor chip without internal wiring is buried in the first inorganic dielectric layer, and a third interconnect structure is located in the second inorganic dielectric layer, the density of the third interconnect structure is greater than or equal to the density of the first interconnect structure, the third interconnect structure is electrically connected to the semiconductor device in the device layer of the semiconductor chip without internal wiring, and part of the third interconnect structure is also electrically connected to part of the first interconnect structure, the semiconductor chip without internal wiring, the third interconnect structure and part of the second inorganic dielectric layer constitute a second semiconductor chip.

[0028] In an optional embodiment, the device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, and the conductive connection structure is electrically connected to the third interconnection structure.

[0029] In an optional embodiment, the semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

[0030] In an optional embodiment, the semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

[0031] Compared with the prior art, the advantages of the technical solution of this application are: In the aforementioned embodiments of the present application, the semiconductor packaging structure and the method for forming the same, in one embodiment, the method for forming the semiconductor packaging structure comprises providing a glass substrate, wherein the glass substrate has a plurality of discrete through-glass via interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass via interconnect structures respectively; forming an inorganic dielectric layer and a first interconnect structure located in the inorganic dielectric layer on the upper surface of the glass substrate, wherein the first interconnect structure is electrically connected to the upper end surface of the through-glass via interconnect structure, and wherein the inorganic dielectric layer and the first interconnect structure are manufactured by a BEOL process in a semiconductor front-end process, wherein the density of the formed first interconnect structure is greater than the density of a second interconnect structure subsequently formed on the lower surface of the glass substrate, and wherein the characteristic size of the first interconnect structure is smaller than the characteristic size of the second interconnect structure subsequently formed; forming an organic passivation layer and a second interconnect structure located in the organic passivation layer on the lower surface of the glass substrate, wherein the second interconnect structure is electrically connected to the lower end surface of the through-glass via interconnect structure, and wherein the organic passivation layer and the second interconnect structure are manufactured by an RDL process in a semiconductor back-end process; and mounting at least one first semiconductor chip on the upper surface of the inorganic dielectric layer, wherein the first semiconductor chip is electrically connected to the first interconnect structure. The BEOL process in the semiconductor front-end process is unconventionally used for the production of part of the rewiring layer (the inorganic dielectric layer and the first interconnection structure) in the back-end process. Since the BEOL process in the semiconductor front-end process is relatively advanced, the density of the formed first interconnection structure is greater than the density of the second interconnection structure formed on the lower surface of the glass substrate, and the characteristic size of the first interconnection structure is smaller than the characteristic size of the formed second interconnection structure. That is, in the present application, the density of the rewiring layer (first interconnection structure) formed on the upper surface of the glass substrate can be greater and the characteristic size can be smaller (more first interconnection structures can be arranged and more connection ports can be reserved under the same area), so that when the first semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, the first semiconductor chip can reserve more external ports to be electrically connected to the corresponding connection ports in the first interconnection structure, thereby improving the performance of the packaging structure.

[0032] Further, in one embodiment, the inorganic dielectric layer includes a first inorganic dielectric layer located on the upper surface of the glass substrate and a second inorganic dielectric layer located on the upper surface of the first inorganic dielectric layer, the second inorganic dielectric layer is a single-layer or multi-layer stacking structure, the first interconnection structure includes a first sub-interconnection structure and a second sub-interconnection structure electrically connected to the first sub-interconnection structure, the second inorganic dielectric layer can also be a single-layer or multi-layer stacking structure, and the number of layers of the second inorganic dielectric layer corresponds to the number of layers of the second inorganic dielectric layer; the process of forming the inorganic dielectric layer and the first interconnection structure includes: a first inorganic dielectric layer on the upper surface of the glass substrate; forming a first sub-interconnection structure in the first inorganic dielectric layer; forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; forming a second sub-interconnection structure in the second inorganic dielectric layer. The formation method also includes: providing a semiconductor chip without internal wiring, wherein the semiconductor chip without internal wiring includes a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has semiconductor devices; burying the semiconductor chip without internal wiring before or after forming the first sub-interconnection structure in the first inorganic dielectric layer; after burying the semiconductor chip without internal wiring, forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; while forming the second sub-interconnection structure in the second inorganic dielectric layer, forming a third interconnection structure in the second inorganic dielectric layer, wherein the density of the third interconnection structure is greater than or equal to the density of the first interconnection structure, the third interconnection structure is electrically connected to the semiconductor devices in the device layer of the semiconductor chip without internal wiring, and part of the third interconnection structure is also electrically connected to part of the first interconnection structure, and the semiconductor chip without internal wiring, the third interconnection structure and part of the second inorganic dielectric layer constitute a second semiconductor chip. That is, when the semiconductor chip without internal wiring is manufactured, only the front-end process (FEOL, Front End Of Line) of the semiconductor front-end process is performed to form a semiconductor device, and the back-end process (BEOL, Back End Of Line) of the semiconductor front-end process is not performed, that is, the internal wiring for interconnecting the semiconductor devices is not formed. After the semiconductor chip without internal wiring is buried in the first inorganic dielectric layer, the internal wiring (third interconnection structure) for interconnecting the semiconductor devices is formed simultaneously or compatible with the step of forming the first interconnection structure on the upper surface of the glass substrate. The semiconductor chip without internal wiring, the third interconnection structure and part of the second inorganic dielectric layer constitute a second semiconductor chip. The second semiconductor chip can have corresponding functions (such as logic control and / or data storage, etc.). The second semiconductor chip can be interconnected with the first semiconductor chip through part of the first interconnection structure, thereby increasing the function of the packaging structure and improving the function of the packaging structure.Moreover, since the semiconductor chip without internal wiring is only made to the device layer without internal wiring, the manufacturing process of the semiconductor chip without internal wiring is greatly simplified. The internal wiring (third interconnection structure) is carried out simultaneously or is compatible with the step of forming the first interconnection structure on the upper surface of the glass substrate, and the structure and function of the second semiconductor chip can be fully realized. Moreover, the semiconductor chip without internal wiring is buried in part of the inorganic dielectric layer, which will not increase the thickness of the packaging structure. Moreover, semiconductor devices (thin film transistor packages) may not be made on the surface of the glass substrate, and the semiconductor devices are all integrated and manufactured on the semiconductor chip without internal wiring. On the one hand, it simplifies the process and reduces thermal effects, and on the other hand, it optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a glass substrate provided in the process of forming a semiconductor packaging structure in one embodiment of the present application; Figure 2 It is a schematic structural diagram of forming an inorganic dielectric layer and a first interconnection structure in the inorganic dielectric layer on the upper surface of a glass substrate during the formation of a semiconductor packaging structure in one embodiment of the present application; Figure 3 It is a schematic structural diagram of an organic passivation layer formed on the lower surface of a glass substrate and a second interconnection structure located in the organic passivation layer during the formation of a semiconductor package structure in one embodiment of the present application; Figure 4 This is a structural schematic diagram of mounting at least one first semiconductor chip on the upper surface of the inorganic dielectric layer during the formation of the semiconductor packaging structure in one embodiment of the present application; Figure 5 It is a schematic structural diagram of forming a plurality of discrete first welding protrusions on the lower surface of the organic passivation layer during the formation of the semiconductor packaging structure in one embodiment of the present application; Figure 6 A structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present application; Figure 7 A structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present application; Figure 8 A structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present application; Fig. 9 for Figure 8 Schematic diagram of the enlarged structure of a semiconductor chip without internal wiring. DETAILED DESCRIPTION

[0034] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0035] Some embodiments of the present application first provide a method for forming a semiconductor packaging structure. The formation process of the semiconductor packaging structure is described in detail below with reference to the accompanying drawings.

[0036] refer to Figure 1 A glass substrate 100 is provided, wherein the glass substrate 100 has a plurality of discrete through-glass interconnect structures 103, and the upper surface and the lower surface of the glass substrate 100 respectively expose the upper end surface and the lower end surface of the through-glass interconnect structures 103.

[0037] The glass substrate 100 serves as a support carrier and a wiring carrier of the packaging structure. Compared with an organic material substrate, the glass substrate 100 has ultra-low flatness (extremely flat), better thermal stability and mechanical stability. In one embodiment, the material of the glass substrate 100 is glass, crystal and the like, and the thermal expansion coefficient of the glass substrate 100 is less than or equal to 9 ppm / °C, specifically 3 ppm / °C-4 ppm / °C, 6 ppm / °C-9 ppm / °C.

[0038] The glass substrate 100 may have a thinner thickness and a larger size. In one embodiment, the thickness of the glass substrate 100 is less than 800 microns. In a specific embodiment, the thickness of the glass substrate 100 may be 300 microns-500 microns. In another specific embodiment, the thickness of the glass substrate 100 may be 30 microns-200 microns. In one embodiment, the shape of the glass substrate 100 is a cuboid, and the size of the glass substrate 100 is greater than 100mmX100mm. Specifically, the size of the glass substrate 100 may be 110mmX110mm, 300mmx300mm, 515mmx510mm, 600mmx600mm, 620mmx750mm.

[0039] A plurality of discrete through-glass interconnect structures 103 are formed in the glass substrate 100. In one embodiment, the material of the through-glass interconnect structure 103 is one material selected from copper, tungsten, aluminum, nickel, gold, gallium, silver, and titanium, or a combination of two or more thereof. In one embodiment, the formation process of the through-glass interconnect structure 103 includes: forming a through-glass via (TGV) in the glass substrate 100, wherein the through-glass via may be formed by a photosensitive glass method, a focused power generation method, a plasma etching method, a laser ablation method, an electrochemical discharge machining method, or a laser induced etching method; filling a metal conductive material in the through-glass via and planarizing the metal conductive material to form the through-glass interconnect structure 103, wherein the filling of the metal conductive material may be performed by electroplating or physical vapor deposition (such as sputtering), and the planarization of the metal conductive material may be performed by a chemical mechanical polishing process.

[0040] refer to Figure 2 An inorganic dielectric layer 104 and a first interconnect structure 101 located in the inorganic dielectric layer 104 are formed on the upper surface of the glass substrate 100, the first interconnect structure 101 is electrically connected to the upper end surface of the through-glass hole interconnect structure 103, and the inorganic dielectric layer 104 and the first interconnect structure 101 are manufactured using a BEOL process in a semiconductor front-end process, and the density of the formed first interconnect structure 101 is greater than that of a second interconnect structure 102 (reference Figure 4 ), the characteristic size of the first interconnect structure 101 is smaller than the characteristic size of the second interconnect structure 102 formed subsequently.

[0041] The inorganic dielectric layer 104 is used to isolate adjacent first interconnect structures 101. The first interconnect structure 101 is used to interconnect different devices. In one embodiment, part of the first interconnect structure 101 can be used to interconnect a first semiconductor chip 201 (refer to FIG. 5 ) subsequently mounted on the surface of the inorganic dielectric layer 104 with the glass through hole interconnect structure 103 in the glass substrate 100. In another embodiment, part of the first interconnect structure 101 can also be used to interconnect a plurality of first semiconductor chips 201 subsequently mounted. In another embodiment, part of the first interconnect structure 101 can also be used to interconnect a bridge chip 301 (refer to FIG. 5 ) subsequently buried in part of the inorganic dielectric layer 104. Figure 6 or Figure 7 ) and the first semiconductor chip 201. In another embodiment, part of the first interconnect structure 101 can also be used for the second semiconductor chip 310 (refer to Figure 8) with the first semiconductor chip 201 and / or a portion of the through glass via interconnection structure 103 in the glass substrate 100.

[0042] The inorganic dielectric layer 104 is a single-layer or multi-layer (multi-layer means ≥ two layers) stacked structure, and the first interconnection structure 101 is a single-layer or multi-layer stacked structure accordingly. In one embodiment, when the inorganic dielectric layer 104 is a multi-layer stacked structure, the corresponding first interconnection structure 101 is also a multi-layer stacked structure, that is, each layer of the inorganic dielectric layer 104 has a first interconnection structure 101. It should be noted that Figure 3 In the example, the inorganic dielectric layer 104 has three layers, and the corresponding first interconnect structure 101 also has three layers, which should not limit the protection scope of the present application. Figure 3 The specific structure of the inorganic dielectric layer 104 and the first interconnect structure 101 is only used as an illustration, and it should not limit the protection scope of the present application. In other embodiments, the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 can be other numbers of layers, and the inorganic dielectric layer 104 and the corresponding first interconnect structure 101 can be other specific structures.

[0043] In one embodiment, the first interconnect structure 101 may include one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; the material of the inorganic dielectric layer 104 is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material; the material of the first interconnect structure is one or a combination of two or more (greater than or equal to two) of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0044] As we all know, the current semiconductor manufacturing process includes semiconductor front-end process and semiconductor back-end process. The semiconductor front-end process will make transistors, resistors, capacitors and other devices on the wafer, as well as the internal wiring that connects these devices to each other. The semiconductor front-end process is also subdivided into front-end process (FEOL, Front End Of Line) and back-end process (BEOL, Back End Of Line). The front-end process (FEOL, Front End Of Line) is used to make transistors, resistors, capacitors and other devices, and the back-end process (BEOL, Back End Of Line) is used to make internal wiring that connects transistors, resistors, capacitors and other devices to each other. The semiconductor back-end process generally includes wafer testing, thinning, mounting, redistribution layer (RDL), packaging and other processes. When semiconductor chips are currently packaged, the redistribution layer is usually produced using the redistribution layer (RDL) process in the semiconductor back-end process, such as forming a resin material layer (such as an ABF resin layer) on the surface of a substrate (such as an inorganic material substrate, a PCB substrate, or a glass substrate); exposing and developing the resin material layer to form a groove; forming a redistribution layer in the groove and on the upper surface of the resin material. The density of the redistribution layer formed in this way is relatively low. Based on the different requirements of the process and various considerations such as yield, in the current semiconductor manufacturing process, the back-end process (BEOL) in the semiconductor front-end process will not be applied to the back-end process.

[0045] The glass substrate has ultra-low flatness (extremely flat), better thermal stability and mechanical stability, which are similar to the characteristics of silicon wafers, and even some characteristics are better than those of silicon wafers. This makes it very suitable for the BEOL process in the semiconductor front-end process when wiring is performed on the glass substrate. Therefore, in this application, the BEOL process in the semiconductor front-end process is unconventionally used for the preparation of part of the rewiring layer (the inorganic dielectric layer 104 and the first interconnect structure 101) in the back-end process. Since the BEOL process in the semiconductor front-end process is relatively advanced, the density of the formed first interconnect structure 101 is greater than the second interconnect structure 102 (reference) formed subsequently on the lower surface of the glass substrate 100. Figure 4), the characteristic size of the first interconnect structure 101 is smaller than the characteristic size of the second interconnect structure 102 formed subsequently, that is, in the present application, the density of the redistribution layer (first interconnect structure 101) formed on the upper surface of the glass substrate 100 can be higher and the characteristic size can be smaller (more first interconnect structures 101 can be arranged and more connection ports can be reserved under the same area), so that when the first semiconductor chip is subsequently mounted on the upper surface of the inorganic dielectric layer 104, the first semiconductor chip can reserve more external ports to be electrically connected to the corresponding connection ports in the first interconnect structure 101, thereby improving the performance of the packaging structure.

[0046] In one embodiment, the first interconnect structure 101 formed has a characteristic size of 0.2-0.8 micrometers, and the second interconnect structure 102 formed subsequently has a characteristic size of 1.5-2.5 micrometers.

[0047] In one embodiment, before forming the inorganic dielectric layer 104 and the first interconnect structure 101 , an upper pad is formed on the upper surface of the glass substrate 100 , and the upper pad is electrically connected to the upper end surface of the through-glass via interconnect structure 103 , and the upper pad is also used as a part of the first interconnect structure 101 .

[0048] refer to Figure 3 An organic passivation layer 105 and a second interconnect structure 102 located in the organic passivation layer 105 are formed on the lower surface of the glass substrate 100, and the second interconnect structure 102 is electrically connected to the lower end surface of the through-glass hole interconnect structure 103, and the organic passivation layer 105 and the second interconnect structure 102 are manufactured using the RDL process in the semiconductor back-end process.

[0049] In one embodiment, the second interconnect structure 102 is a redistribution layer (RDL). The organic passivation layer 105 is a single-layer or multi-layer stacked structure, and the second interconnect structure 102 is a single-layer or multi-layer stacked structure accordingly. The material of the organic passivation layer 105 is a resin material, such as ABF resin or other resins, and the material of the second interconnect structure 102 is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0050] In one embodiment, before forming the organic passivation layer 105 and the second interconnect structure 102 , a lower pad is formed on the lower surface of the glass substrate 100 , and the lower pad is electrically connected to the lower end surface of the through glass via interconnect structure 103 , and the lower pad is also used as a part of the second interconnect structure 102 .

[0051] In one embodiment, the process of manufacturing the organic passivation layer 105 and the second interconnect structure 102 by the RDL process in the semiconductor back-end process includes: forming the organic passivation layer 105 on the lower surface of the glass substrate 100, and the formation process of the organic passivation layer 105 includes spin coating; exposing and developing the organic passivation layer 105 to form a groove, and the groove exposes the lower end surface of the through glass via interconnect structure 103 or the upper pad formed on the lower end surface of the through glass via interconnect structure 103; forming the second interconnect structure 102 in the groove and on a portion of the upper surface of the organic passivation layer 105, and the formation of the second interconnect structure 102 includes electroplating.

[0052] In one embodiment, the density of the formed second interconnect structure 102 is smaller than that of the first interconnect structure 101, the characteristic size of the second interconnect structure 102 is larger than the characteristic size of the first interconnect structure 101, and the organic passivation layer 105 and the second interconnect structure 102 are formed after the inorganic dielectric layer 104 and the first interconnect structure 101 are formed, so that when the inorganic dielectric layer 104 and the first interconnect structure 101 are formed on the upper surface of the glass substrate 100, the lower surface of the glass substrate 100 can maintain a relatively high flatness, which is conducive to performing a more advanced BEOL process in a semiconductor front-end process on the upper surface of the glass substrate 100 to manufacture a first interconnect structure with a higher density and a smaller characteristic size.

[0053] refer to Figure 4 At least one first semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104 , and the first semiconductor chip 201 is electrically connected to the first interconnect structure 101 .

[0054] The first semiconductor chip 201 includes a relative back surface and an active surface, an integrated circuit (with specific functions) (not shown in the figure) is formed in the first semiconductor chip, and the active surface has a plurality of external protrusions 202 (the plurality of external protrusions 202 correspond to a plurality of external ports of the first semiconductor chip), and the plurality of external protrusions 202 are electrically connected to the integrated circuit. The external protrusions 202 are microbumps, and the material of the external protrusions 202 is one or a combination of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0055] In one embodiment, the first semiconductor chip 201 is mounted by flip-chip mounting. Specifically, the active surface of the first semiconductor chip 201 is mounted downward on the upper surface of the inorganic dielectric layer 104 , and the external protrusions 202 on the active surface of the first semiconductor chip 201 are welded together with the corresponding first interconnect structure 101 .

[0056] The number of the mounted first semiconductor chips 201 is one or more (greater than or equal to 2). Figure 4 The mounting of two first semiconductor chips 201 is taken as an example for description.

[0057] In one embodiment, when there are multiple first semiconductor chips 201 mounted, the multiple first semiconductor chips 201 may be semiconductor chips with the same function or different functions.

[0058] In one embodiment, the plurality of first semiconductor chips 201 may include logic chips and / or memory chips. In some embodiments, the logic chip may include but is not limited to a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip or a complementary metal oxide semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase change memory (PRAM), a resistive random access memory (RRAM) or a non-volatile memory chip (such as a flash memory).

[0059] In one embodiment, reference Figure 5 , further comprising: forming a plurality of discrete first welding protrusions 106 on the lower surface of the organic passivation layer 105 , wherein the first welding protrusions 106 are electrically connected to the second interconnect structure 102 .

[0060] The first welding protrusion 106 is used as a port for connecting the packaging structure to other substrates, other packaging structures and devices. In one embodiment, the material of the first welding protrusion 106 is one or a combination of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.

[0061] In one embodiment, before forming the first welding protrusion 106 , a second inorganic passivation layer (not shown) may be formed on the lower surface of the organic passivation layer 105 , and the second inorganic passivation layer partially exposes the lower surface of the second interconnect structure 102 .

[0062] Another embodiment of the present application further provides a method for forming a semiconductor packaging structure, referring to Figure 6 The main difference between this embodiment and the previous embodiment is that: a bridge chip 301 is provided, and the bridge chip 301 has a wiring layer (not shown in the figure), and the density of the wiring layer is greater than the density of the first interconnect structure 101; the formation method also includes: burying the bridge chip 301 in the inorganic dielectric layer 104, the wiring layer on the bridge chip 301 is electrically connected to a part of the first interconnect structure 101, and is electrically connected to the first semiconductor chip 201 through a part of the external protrusion 202, so that the wiring density on the upper surface of the glass substrate 100 can be further improved through the bridge chip 301, and the interconnection between the adjacent multiple first semiconductor chips 201 is realized, and the performance of the packaging structure is improved.

[0063] In one embodiment, the bridge chip 301 is buried in the topmost inorganic dielectric layer 104 to reduce the impact of the buried bridge chip 301 on the formation process of the first interconnect structure 101, while reducing the distance between the bridge chip 301 and the first semiconductor chip 201 to improve the signal transmission rate.

[0064] Another embodiment of the present application further provides a method for forming a semiconductor packaging structure, referring to Figure 7 The main difference between this embodiment and the previous embodiment is that: the glass substrate 100 is used as an interposer; the formation method also includes: providing a packaging substrate 120, welding the first welding protrusion 106 to the upper surface of the packaging substrate 120; forming a plurality of discrete second welding protrusions 122 on the lower surface of the packaging substrate 120, the size of the second welding protrusion 122 is larger than the size of the first welding protrusion 106, and the size of the first welding protrusion 106 is larger than the size of the external protrusion 202.

[0065] In one embodiment, the packaging substrate 120 is an organic material substrate or a printed circuit board (PCB). The packaging substrate 120 has a connection wiring 121 therein. The connection wiring 121 electrically connects the corresponding first welding protrusions 106 and the second welding protrusions 122 .

[0066] In one embodiment, a third semiconductor chip (not shown) may be mounted on the upper surface of the package substrate 120, and the third semiconductor chip is electrically connected to the connection wiring 121. In one embodiment, the third semiconductor chip may be electrically connected to the first semiconductor chip 201 on the glass substrate 100 through part of the connection wiring 121 and the first soldering protrusion 106. The number of the third semiconductor chip may be one or more, and the third semiconductor chip may be a logic chip and / or a memory chip.

[0067] Another embodiment of the present application further provides a method for forming a semiconductor packaging structure, referring to Figure 8 and Fig. 9 , Fig. 9 for Figure 8Schematic diagram of the enlarged structure of the semiconductor chip 300 without internal wiring in the embodiment, the main difference between this embodiment and the previous embodiment is that: the inorganic dielectric layer 104 includes a first inorganic dielectric layer 104a located on the upper surface of the glass substrate 100 and a second inorganic dielectric layer 104b located on the upper surface of the first inorganic dielectric layer 104a, the second inorganic dielectric layer 104b is a single-layer or multi-layer stacked structure, the first interconnection structure 101 includes a first sub-interconnection structure 101a and a second sub-interconnection structure 101b electrically connected to the first sub-interconnection structure 101a, and the second inorganic dielectric layer 104b is a single-layer or multi-layer stacked structure. Layer 104b may also be a single-layer or multi-layer stacked structure, and the number of layers of the second inorganic dielectric layer 104b corresponds to the number of layers of the second inorganic dielectric layer 104b; the process of forming the inorganic dielectric layer 104 and the first interconnect structure 101 includes: forming a first inorganic dielectric layer 104a on the upper surface of the glass substrate 100; forming a first sub-interconnect structure 101a in the first inorganic dielectric layer 104a; forming a second inorganic dielectric layer 104b on the upper surface of the first inorganic dielectric layer 104a; and forming a second sub-interconnect structure 101b in the second inorganic dielectric layer 104b. The formation method further includes: providing a semiconductor chip 300 without internal wiring, wherein the semiconductor chip 300 without internal wiring includes a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302, wherein the device layer has a semiconductor device 304; burying the semiconductor chip 300 without internal wiring before or after forming the first sub-interconnect structure in the first inorganic dielectric layer 104a; after burying the semiconductor chip 300 without internal wiring, forming a second inorganic dielectric layer 104b on the upper surface of the first inorganic dielectric layer 104a; forming a second inorganic dielectric layer 104b in the second inorganic dielectric layer 104b; While forming the second sub-interconnect structure 101b, a third interconnect structure 305 is formed in the second inorganic dielectric layer 104b, the density of the third interconnect structure 305 is greater than or equal to the density of the first interconnect structure 101, the third interconnect structure 305 is electrically connected to the semiconductor device 304 in the device layer of the semiconductor chip 300 without internal wiring, and part of the third interconnect structure 305 is also electrically connected to part of the first interconnect structure 101, the semiconductor chip 300 without internal wiring, the third interconnect structure 305 and part of the second inorganic dielectric layer 104b constitute a second semiconductor chip 310.

[0068] In this embodiment, when the semiconductor chip 300 without internal wiring is manufactured, only the front-end process (FEOL) of the semiconductor front-end process is performed to form the semiconductor device 304, and the back-end process (BEOL) of the semiconductor front-end process is not performed, that is, the internal wiring for interconnecting the semiconductor device 304 is not formed. After the semiconductor chip 300 without internal wiring is buried in the first inorganic dielectric layer 104a, the internal wiring (third interconnection structure) for interconnecting the semiconductor device 304 is formed simultaneously or compatible with the step of forming the first interconnection structure 101 on the upper surface of the glass substrate 100. The semiconductor chip 300 without internal wiring, the third interconnection structure 305 and part of the second inorganic dielectric layer 104b constitute the second semiconductor chip 310. The second semiconductor chip 310 can have corresponding functions (such as logic control and / or data storage, etc.). The second semiconductor chip 310 can be interconnected with the first semiconductor chip 201 through part of the first interconnection structure 101, thereby increasing the function of the packaging structure and improving the function of the packaging structure. Furthermore, since the semiconductor chip 300 without internal wiring is only made to the device layer without internal wiring, the manufacturing process of the semiconductor chip 300 without internal wiring is greatly simplified. The internal wiring (third interconnection structure) is performed synchronously or compatible with the step of forming the first interconnection structure 101 on the upper surface of the glass substrate 100, and the structure and function of the second semiconductor chip 310 can be fully realized. Moreover, the semiconductor chip 300 without internal wiring is buried in part of the inorganic dielectric layer 104, and the thickness of the packaging structure will not be increased. Moreover, the surface of the glass substrate 100 does not need to manufacture semiconductor devices (thin film transistor package), and the semiconductor devices are integrated and manufactured on the semiconductor chip 300 without internal wiring. On the one hand, it simplifies the process and reduces the thermal effect, and on the other hand, it optimizes and simplifies the layout of the wiring layer on the upper surface of the glass substrate 100.

[0069] In one embodiment, the semiconductor chip 300 without internal wiring may also be electrically connected to a portion of the through glass via interconnect structure 103 in the glass substrate 100 through a portion of the first interconnect structure 101 .

[0070] In one embodiment, the semiconductor substrate of the semiconductor chip 300 without internal wiring has a through silicon via interconnect structure (TSV) (not shown in the figure), and the through silicon via interconnect structure (TSV) is electrically connected to part of the third interconnect structure and part of the through glass via interconnect structure 103.

[0071] In one embodiment, continue to refer to Figure 8 and Fig. 9, the device layer also includes a bottom inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, the bottom inorganic dielectric layer 303 covers the semiconductor device 304, the device layer also includes a conductive connection structure 307 located in the bottom inorganic dielectric layer 303 and electrically connected to the active area of ​​the semiconductor device 304, the conductive connection structure 307 is electrically connected to the third interconnect structure 305, the bottom inorganic dielectric layer 303 directly exposes part or all of the active area of ​​the semiconductor device 304, and the bottom inorganic dielectric layer 303 exposes the upper end surface of the conductive connection structure 307. In one embodiment, the semiconductor substrate 302 can be a wafer. In one embodiment, the material of the semiconductor substrate 302 is silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V compounds such as gallium arsenide. The semiconductor substrate 302 can also be implanted with certain doping ions according to design requirements to change electrical parameters. In one embodiment, a shallow trench isolation structure 306 is further formed in the semiconductor substrate 302, and the shallow trench isolation structure is used to isolate different semiconductor devices 304 to prevent electrical connection between different semiconductor devices 304. The material of the bottom inorganic dielectric layer 303 and the shallow trench isolation structure 306 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0072] In one embodiment, the semiconductor device 304 includes one or a combination of bipolar transistors, field effect transistors, and insulated gate bipolar transistors. In another embodiment, the semiconductor device 304 also includes one or a combination of diodes, resistors, capacitors, and inductors. It should be noted that: Figure 8 and Fig. 9 The semiconductor device 304 is described by taking two field effect transistors as an example. In other embodiments, the semiconductor device 304 may be other semiconductor devices, other quantities, or other layout structures.

[0073] The bipolar transistor (full name bipolar junction transistor (BJT), commonly known as triode, is an electronic device with three terminals, made of three parts of semiconductors with different doping levels in a semiconductor substrate, including an emitter, a base and a collector. The base has different doping types from the emitter and the collector. For example, for an NPN triode, the base is doped with a P type, and the emitter and the collector are doped with an N type. For the field effect transistor (FET), please refer to Fig. 9 , including a gate 304a located on the upper surface of a semiconductor substrate 302 and a source 304b and a drain 304c in the semiconductor substrate 302 located on both sides of the gate 304a, and the field effect transistor also includes a sidewall 304d located on the sidewall surface of the gate 304a. The field effect transistor may include a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-EffectTransistor, MOSFET) or a fin field effect transistor (Fin Field-EffectTransistor, FinFET), and the metal oxide semiconductor field effect transistor includes a PMOS transistor and an NMOS transistor. The insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor—IGBT) includes a gate, a collector and an emitter with different doping levels, and the gate has different doping types from the emitter and the collector. For example, in an N-type IGBT, when the gate is doped with a P-type, the emitter and the collector are doped with an N-type.

[0074] In one embodiment, before burying the semiconductor chip 300 without internal wiring in the first inorganic dielectric layer 104a, a corresponding groove needs to be formed in the first inorganic dielectric layer 104a, and then the semiconductor chip 300 without internal wiring is placed in the groove. In one embodiment, before placing the semiconductor chip 300 without internal wiring in the groove, an adhesive is applied to the lower surface of the semiconductor chip 300.

[0075] Another embodiment of the present application further provides a semiconductor packaging structure, referring to Figure 6 ,include: A glass substrate 100, wherein the glass substrate 100 has a plurality of discrete through-glass interconnect structures 103, wherein the upper surface and the lower surface of the glass substrate 100 expose the upper end surface and the lower end surface of the through-glass interconnect structures 103 respectively; An inorganic dielectric layer 104 located on the upper surface of the glass substrate 100 and a first interconnect structure 101 located in the inorganic dielectric layer 104, wherein the first interconnect structure 101 is electrically connected to the upper end surface of the through-glass via interconnect structure 103; an organic passivation layer 105 located on the lower surface of the glass substrate 100 and a second interconnection structure 102 located in the organic passivation layer 105, wherein the second interconnection structure 102 is electrically connected to the lower end surface of the through-glass via interconnection structure 103, and the density of the first interconnection structure 101 is greater than that of the second interconnection structure 102, and the characteristic size of the first interconnection structure 101 is smaller than that of the second interconnection structure 102; At least one first semiconductor chip 201 is mounted on the upper surface of the inorganic dielectric layer 104 , and the first semiconductor chip 201 is electrically connected to the first interconnect structure 101 .

[0076] In one embodiment, the structure further includes: a plurality of discrete first welding protrusions 106 located on the lower surface of the organic passivation layer 105 , wherein the first welding protrusions 106 are electrically connected to the second interconnect structure 102 .

[0077] In one embodiment, the first interconnect structure 101 includes one or a combination of metal lines, metal plugs, damascene structures or dual damascene structures; and the second interconnect structure 102 is a rewiring layer.

[0078] In one embodiment, the inorganic dielectric layer 104 is a single-layer or multi-layer stacked structure, and the first interconnect structure 101 is correspondingly a single-layer or multi-layer stacked structure; the material of the inorganic dielectric layer 104 is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer 105 is a resin material, and the material of the first interconnect structure 101 and the second interconnect structure 102 is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0079] In one embodiment, the characteristic size of the first interconnect structure 101 is 0.2-0.8 microns, the characteristic size of the second interconnect structure 102 is 1.5-2.5 microns, and the inorganic dielectric layer 104 and the first interconnect structure 101 are formed by the BEOL process in the semiconductor front-end process, and the organic passivation layer 105 and the second interconnect structure 102 are formed by the RDL process in the semiconductor back-end process.

[0080] In another embodiment, reference Figure 7 , the glass substrate 100 is used as a transfer plate; the packaging structure also includes: a packaging substrate 120, the first welding protrusion 106 is welded on the upper surface of the packaging substrate 120; and a plurality of discrete second welding protrusions 122 are formed on the lower surface of the packaging substrate 120.

[0081] In another embodiment, reference Figure 6 The packaging structure further includes: a bridge chip 301, wherein the bridge chip 301 has a wiring layer (not shown in the figure), the density of the wiring layer is greater than the density of the first interconnect structure 101, the bridge chip 301 is buried in the inorganic dielectric layer 104, and the wiring layer on the bridge chip 301 is electrically connected to a portion of the first interconnect structure 101.

[0082] In another embodiment, reference Figure 8 Combined with reference Fig. 9The inorganic dielectric layer 104 includes a first inorganic dielectric layer 104a located on the upper surface of the glass substrate 100 and a second inorganic dielectric layer 104b located on the upper surface of the first inorganic dielectric layer 104a, and the first interconnection structure 101 includes a first sub-interconnection structure 101a located in the first inorganic dielectric layer 104a and a second sub-interconnection structure 101b located in the second inorganic dielectric layer 104b and electrically connected to the first sub-interconnection structure 101a. The packaging structure further includes: a semiconductor chip 300 without internal wiring, wherein the semiconductor chip 300 without internal wiring includes a semiconductor substrate 302 and a device layer located on the upper surface of the semiconductor substrate 302, wherein the device layer has a semiconductor device 304; the semiconductor chip 300 without internal wiring is buried in the first inorganic dielectric layer 104a, and a third interconnect structure 305 is located in the second inorganic dielectric layer 104b, wherein the density of the third interconnect structure 305 is greater than or equal to the density of the first interconnect structure 101, the third interconnect structure 305 is electrically connected to the semiconductor device 304 in the device layer of the semiconductor chip 300 without internal wiring, and a portion of the third interconnect structure 305 is also electrically connected to a portion of the first interconnect structure 101, and the semiconductor chip 300 without internal wiring, the third interconnect structure 305 and a portion of the second inorganic dielectric layer 104b constitute a second semiconductor chip 310.

[0083] In one embodiment, the device layer also includes an underlying inorganic dielectric layer 303 located on the upper surface of the semiconductor substrate 302, and the underlying inorganic dielectric layer 303 covers the semiconductor device 304. The device layer also includes a conductive connection structure 307 located in the underlying inorganic dielectric layer 303 and electrically connected to the active area of ​​the semiconductor device 304, and the conductive connection structure 307 is electrically connected to the third interconnection structure 305.

[0084] In one embodiment, the semiconductor device 304 includes a bipolar transistor, a field effect transistor (refer to Fig. 9 ) and insulated gate bipolar transistor or a combination of these.

[0085] In another embodiment, the semiconductor device 304 may further include one or a combination of a diode, a resistor, a capacitor and an inductor.

[0086] It should be noted that the parts in the embodiment of the aforementioned semiconductor packaging structure that are the same or similar to those in the embodiment of the aforementioned method for forming the semiconductor packaging structure will not be repeated in the embodiment of the semiconductor packaging structure. Please refer to the limitations or descriptions of the corresponding parts in the embodiment of the method for forming the aforementioned semiconductor packaging structure for details.

[0087] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a semiconductor packaging structure, characterized in that: include: Providing a glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively; An inorganic dielectric layer and a first interconnect structure located in the inorganic dielectric layer are formed on the upper surface of the glass substrate, the first interconnect structure is electrically connected to the upper end surface of the through-glass via interconnect structure, and the inorganic dielectric layer and the first interconnect structure are manufactured by a BEOL process in a semiconductor front-end process, the density of the formed first interconnect structure is greater than the density of a second interconnect structure subsequently formed on the lower surface of the glass substrate, and the characteristic size of the first interconnect structure is smaller than the characteristic size of the second interconnect structure subsequently formed; An organic passivation layer and a second interconnection structure located in the organic passivation layer are formed on the lower surface of the glass substrate, the second interconnection structure is electrically connected to the lower end surface of the through-glass hole interconnection structure, and the organic passivation layer and the second interconnection structure are manufactured by using an RDL process in a semiconductor back-end process; At least one first semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the first semiconductor chip is electrically connected to the first interconnection structure.

2. The method for forming a semiconductor package structure according to claim 1, wherein: Also includes: A plurality of discrete first welding protrusions are formed on the lower surface of the organic passivation layer, and the first welding protrusions are electrically connected to the second interconnection structure.

3. The method for forming a semiconductor package structure according to claim 2, wherein: The glass substrate is used as a transfer plate; the forming method further comprises: providing a packaging substrate, welding the first welding protrusion to the upper surface of the packaging substrate; and forming a plurality of discrete second welding protrusions on the lower surface of the packaging substrate.

4. The method for forming a semiconductor package structure according to claim 1 or 3, wherein: The first interconnect structure includes one or a combination of metal wires, metal plugs, damascene structures or dual damascene structures; the second interconnect structure is a rewiring layer.

5. The method for forming a semiconductor package structure according to claim 4, wherein: The inorganic dielectric layer is a single-layer or multi-layer stacked structure, and the first interconnect structure is correspondingly a single-layer or multi-layer stacked structure.

6. The method for forming a semiconductor package structure according to claim 5, wherein: The material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure and the second interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

7. The method for forming a semiconductor package structure according to claim 6, wherein: The characteristic size of the first interconnect structure is 0.2-0.8 microns, and the characteristic size of the second interconnect structure is 1.5-2.5 microns.

8. The method for forming a semiconductor package structure according to claim 1, wherein: Providing a bridge chip, wherein the bridge chip has a wiring layer, and the density of the wiring layer is greater than the density of the first interconnect structure; The forming method further includes: burying the bridge chip in the inorganic dielectric layer, and the wiring layer on the bridge chip is electrically connected to a portion of the first interconnect structure.

9. The method for forming a semiconductor package structure according to claim 1, wherein: The inorganic dielectric layer includes a first inorganic dielectric layer located on the upper surface of a glass substrate and a second inorganic dielectric layer located on the upper surface of the first inorganic dielectric layer. The first interconnect structure includes a first sub-interconnect structure and a second sub-interconnect structure electrically connected to the first sub-interconnect structure. The process of forming the inorganic dielectric layer and the first interconnect structure includes: forming a first inorganic dielectric layer on the upper surface of the glass substrate; forming a first sub-interconnect structure in the first inorganic dielectric layer; forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; and forming a second sub-interconnect structure in the second inorganic dielectric layer.

10. The method for forming a semiconductor package structure according to claim 9, wherein: The formation method further includes: providing a semiconductor chip without internal wiring, wherein the semiconductor chip without internal wiring comprises a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, wherein the device layer has semiconductor devices; before or after forming the first sub-interconnection structure in the first inorganic dielectric layer, burying the semiconductor chip without internal wiring; after burying the semiconductor chip without internal wiring, forming a second inorganic dielectric layer on the upper surface of the first inorganic dielectric layer; while forming the second sub-interconnection structure in the second inorganic dielectric layer, forming a third interconnection structure in the second inorganic dielectric layer, wherein the density of the third interconnection structure is greater than or equal to the density of the first interconnection structure, the third interconnection structure is electrically connected to the semiconductor devices in the device layer of the semiconductor chip without internal wiring, and part of the third interconnection structure is also electrically connected to part of the first interconnection structure, and the semiconductor chip without internal wiring, the third interconnection structure and part of the second inorganic dielectric layer constitute a second semiconductor chip.

11. The method for forming a semiconductor package structure according to claim 10, wherein: The device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, the conductive connection structure is electrically connected to the third interconnection structure.

12. The method for forming a semiconductor package structure according to claim 11, wherein: The semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

13. The method for forming a semiconductor package structure according to claim 12, wherein: The semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

14. A semiconductor packaging structure, used to implement the method for forming a semiconductor packaging structure according to any one of claims 1 to 13, characterized in that: include: A glass substrate having a plurality of discrete through-glass interconnect structures, wherein the upper surface and the lower surface of the glass substrate expose the upper end surface and the lower end surface of the through-glass interconnect structures respectively; an inorganic dielectric layer located on the upper surface of the glass substrate and a first interconnect structure located in the inorganic dielectric layer, wherein the first interconnect structure is electrically connected to the upper end surface of the through-glass via interconnect structure; an organic passivation layer located on the lower surface of the glass substrate and a second interconnection structure located in the organic passivation layer, wherein the density of the first interconnection structure is greater than the density of the second interconnection structure, and the characteristic size of the first interconnection structure is smaller than the characteristic size of the second interconnection structure; At least one first semiconductor chip is mounted on the upper surface of the inorganic dielectric layer, and the first semiconductor chip is electrically connected to the first interconnection structure.

15. The semiconductor package structure according to claim 14, wherein: Also includes: A plurality of discrete first welding protrusions are located on the lower surface of the organic passivation layer, wherein the first welding protrusions are electrically connected to the second interconnect structure.

16. The semiconductor package structure according to claim 15, wherein: The glass substrate is used as a transfer plate; the packaging structure further comprises: a packaging substrate, the first welding protrusion is welded on the upper surface of the packaging substrate; and a plurality of discrete second welding protrusions are formed on the lower surface of the packaging substrate.

17. The semiconductor package structure according to claim 14 or 16, wherein: The first interconnect structure includes one or a combination of metal wires, metal plugs, damascene structures or dual damascene structures; the second interconnect structure is a rewiring layer.

18. The semiconductor package structure according to claim 17, wherein: The inorganic dielectric layer is a single-layer or multi-layer stacked structure, and the first interconnection structure is correspondingly a single-layer or multi-layer stacked structure; the material of the inorganic dielectric layer is one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or a low dielectric constant material, the material of the organic passivation layer is a resin material, and the material of the first interconnection structure and the second interconnection structure is one or a combination of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

19. The semiconductor package structure according to claim 18, wherein: The characteristic size of the first interconnect structure is 0.2-0.8 microns, the characteristic size of the second interconnect structure is 1.5-2.5 microns, and the inorganic dielectric layer and the first interconnect structure are formed by the BEOL process in the semiconductor front-end process, and the organic passivation layer and the second interconnect structure are formed by the RDL process in the semiconductor back-end process.

20. The semiconductor package structure according to claim 14, wherein: The packaging structure also includes: a bridge chip, the bridge chip has a wiring layer, the density of the wiring layer is greater than the density of the first interconnect structure, the bridge chip is buried in the inorganic dielectric layer, and the wiring layer on the bridge chip is electrically connected to part of the first interconnect structure.

21. The semiconductor package structure according to claim 14, wherein: The inorganic dielectric layer includes a first inorganic dielectric layer located on the upper surface of the glass substrate and a second inorganic dielectric layer located on the upper surface of the first inorganic dielectric layer. The first interconnect structure includes a first sub-interconnect structure located in the first inorganic dielectric layer and a second sub-interconnect structure located in the second inorganic dielectric layer and electrically connected to the first sub-interconnect structure.

22. The semiconductor package structure according to claim 21, wherein: The packaging structure also includes: a semiconductor chip without internal wiring, the semiconductor chip without internal wiring includes a semiconductor substrate and a device layer located on the upper surface of the semiconductor substrate, and the device layer has a semiconductor device; the semiconductor chip without internal wiring is buried in the first inorganic dielectric layer, and a third interconnect structure is located in the second inorganic dielectric layer, the density of the third interconnect structure is greater than or equal to the density of the first interconnect structure, the third interconnect structure is electrically connected to the semiconductor device in the device layer of the semiconductor chip without internal wiring, and part of the third interconnect structure is also electrically connected to part of the first interconnect structure, the semiconductor chip without internal wiring, the third interconnect structure and part of the second inorganic dielectric layer constitute a second semiconductor chip.

23. The semiconductor package structure according to claim 22, wherein: The device layer also includes an underlying inorganic dielectric layer located on the upper surface of the semiconductor substrate, the underlying inorganic dielectric layer covers the semiconductor device, and the device layer also includes a conductive connection structure located in the underlying inorganic dielectric layer and electrically connected to the active area of ​​the semiconductor device, the conductive connection structure is electrically connected to the third interconnection structure.

24. The semiconductor package structure according to claim 23, wherein: The semiconductor device includes one or a combination of bipolar transistors, field effect transistors and insulated gate bipolar transistors.

25. The semiconductor package structure according to claim 24, wherein: The semiconductor device further includes one or a combination of a diode, a resistor, a capacitor and an inductor.

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