Packaging substrate, design method thereof and electronic equipment

Abstract

The invention discloses a packaging substrate, a design method thereof and electronic equipment, and the method comprises the steps: obtaining the radius of a first through hole of the packaging substrate, the radius of a second through hole connected with the first through hole, and the hole pitch, according to the radius of the first via hole, the radiuses of the second via holes, the hole pitch and a preset position constraint condition of the first via hole and the plurality of second via holes connected with the first via hole, obtaining a position relationship between the first via hole and the second via holes connected with the first via hole, and according to the position relationship between the first via hole and the second via holes connected with the first via hole, obtaining the distance between the first via hole and the second via holes connected with the first via hole; any one of the plurality of first via holes of the packaging substrate and the second via holes connected with the first via hole are arranged, so that the plurality of second via holes can be arranged in a trapezoid shape through the position constraint condition, and the area of the first via hole and the area of the plurality of second via holes connected with the first via hole are reduced. Therefore, the area of the hollowed-out area of the conductive plane with the attribute different from that of the first via hole can be reduced, the probability that the conductive plane is broken can be reduced, and the conductivity of the conductive plane is improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a packaging substrate and a design method thereof and an electronic device. Background Art

[0002] The packaging substrate generally includes a core layer and a plurality of metal layers and a plurality of dielectric layers respectively located on both sides of the core layer. The core layer or dielectric layer is located between adjacent metal layers, and the traces or conductive planes on the adjacent metal layers are connected through vias penetrating the core layer or dielectric layer. Each via penetrating the core layer, i.e., the first via, is connected to four vias penetrating the adjacent dielectric layers, i.e., the second vias, and the four second vias are arranged in a centrally symmetrical manner. However, the density of the first vias in the current packaging substrate is relatively high, resulting in an excessively high density of hollowed-out areas of the conductive planes with different properties from the first vias in the adjacent metal layers, which easily leads to the partial hollowed-out areas of the conductive planes being connected together, resulting in the disconnection of some non-hollowed-out areas of the conductive planes, thereby affecting the conductivity of the conductive planes. Summary of the invention

[0003] The present application discloses a packaging substrate and a design method thereof and an electronic device, so as to solve the problem that the conductivity of the conductive plane is affected by the high density of via holes in the core layer.

[0004] In a first aspect, the present application discloses a design method for a packaging substrate, comprising: obtaining the radius of a first via hole of the packaging substrate, the radius of a second via hole connected to the first via hole, and a hole spacing; the first via hole comprises a via hole penetrating a core layer of the packaging substrate; the second via hole comprises a via hole penetrating a dielectric layer of the packaging substrate; according to the radius of the first via hole, the radius of the second via hole, the hole spacing, and preset position constraints of the first via hole and a plurality of second via holes connected thereto, obtaining the position relationship between the first via hole and the second via holes connected thereto; wherein the position constraints comprise: the plurality of second via holes are arranged around the first via hole, and the plurality of second via holes are arranged in a trapezoidal shape; according to the position relationship between the first via hole and the second via hole connected thereto, arranging any first via hole among the plurality of first via holes of the packaging substrate and the second via hole connected thereto.

[0005] In this way, the area of ​​the first via and the multiple second vias connected thereto can be reduced by arranging the multiple second vias in a trapezoidal shape, thereby reducing the area of ​​the hollowed-out region of the conductive plane having different properties from the first via. Further, at the same via density, the area of ​​the conductive plane between the hollowed-out regions can be increased, thereby reducing the probability of the conductive plane being disconnected and improving the conductivity of the conductive plane.

[0006] In some embodiments of the present application, obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, and preset positional constraints of the first via and the multiple second vias connected thereto includes: obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, preset positional constraints of the first via and the multiple second vias connected thereto, and preset arrangement constraints of the first via; wherein the arrangement constraints of the first vias include: the area of ​​the hollowed-out region of the conductive plane having properties different from those of the first via is the smallest, or the density of the first vias is the largest.

[0007] In this way, different positional relationships between the first via holes and the second via holes connected thereto can be obtained according to different arrangement constraints.

[0008] In some embodiments of the present application, obtaining the positional relationship between the first via and the second via connected thereto based on the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, and the preset arrangement constraints of the first via includes: obtaining the positional relationship between the first via and one of the second vias connected thereto based on the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, the preset positional relationship between adjacent first vias in the first direction, and the preset positional relationship between adjacent second vias, when the arrangement constraint of the first via is that the area of ​​the hollowed-out region of the conductive plane having different properties from the first via is minimized.

[0009] In this way, the positional relationship between the first via and a second via connected thereto can be obtained relatively simply when the arrangement constraint condition of the first via is that the area of ​​the hollowed-out region of the conductive plane having different properties from the first via is minimized.

[0010] In some embodiments of the present application, obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, and the preset arrangement constraints of the first via includes: when the arrangement constraint of the first via is that the density of the first via is maximum, obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, the preset positional relationship between the adjacent second vias, and the preset positional relationship between the first via and the second via not connected thereto.

[0011] In this way, when the arrangement constraint condition of the first via holes is that the density of the first via holes is the maximum, the positional relationship between the first via holes and a second via hole connected thereto can be obtained relatively simply.

[0012] In some embodiments of the present application, obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and the multiple second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, the preset positional relationship between the adjacent second vias, and the preset positional relationship between the first via and the second via not connected thereto includes: obtaining the positional relationship between the first via and one of the second vias connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and the multiple second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, and the preset positional relationship between the adjacent second vias; obtaining the positional relationship between the first via and another of the second vias connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and the multiple second vias connected thereto, the preset positional relationship between the first via and the second via not connected thereto, and the preset positional relationship between the adjacent second vias.

[0013] In some embodiments of the present application, the obtaining of the positional relationship between the first via and one of the second vias connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the plurality of second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, and the preset positional relationship between the second vias adjacent to each other includes: obtaining, according to the radius of the first via, the hole spacing, and the preset positional relationship between the first vias adjacent to each other in the first direction, a functional relationship of the first side length of a triangle where a line connecting the center of the first via and the center of one of the second vias connected thereto is located; obtaining, according to the radius of the second via, the hole spacing, and the preset positional relationship between the first vias adjacent to each other in the first direction, a functional relationship of the first side length of a triangle where a line connecting the center of the first via and the center of the second via ... The functional relationship of the second side length of the triangle is obtained according to the distance and the preset positional relationship of the adjacent second via hole; the functional relationship of the third side length of the triangle is obtained according to the radius of the first via hole, the radius of the second via hole and the preset positional constraints of the first via hole and the multiple second via holes connected thereto; the first angle is obtained according to the functional relationship of the first side length of the triangle, the functional relationship of the second side length of the triangle and the functional relationship of the third side length of the triangle; the first angle is the angle between the line connecting the center of the first via hole and the center of one of the second via holes connected thereto and the first direction; the positional relationship between the first via hole and one of the second via holes connected thereto is obtained according to the first angle.

[0014] In some embodiments of the present application, the obtaining of the positional relationship between the first via and another second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, the preset positional relationship between the first via and the second via not connected thereto, and the preset positional relationship between the second vias adjacent thereto comprises: obtaining a second angle according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the multiple second vias connected thereto, the preset positional relationship between the first via and the second via not connected thereto, and the preset positional relationship between the second vias adjacent thereto; the second angle is the first The angle between the line connecting the center of the via and the center of the second via connected thereto and the line connecting the center of the first via and the center of the second via not connected thereto; a third angle is obtained according to the second angle, the first angle, the radius of the first via, the hole spacing, the radius of the second via, the preset position constraints of the first via and the multiple second vias connected thereto, and the preset position relationship between the first via and the second via not connected thereto; the third angle is the angle between the line connecting the center of the first via and the center of another second via connected thereto and the second direction; the second direction intersects with the first direction; according to the third angle, the position relationship between the first via and another second via connected thereto is obtained.

[0015] In a second aspect, the present application discloses a computer device, comprising a memory and a processor; the memory is used to store instructions; the processor is used to execute the packaging substrate design method as described in any of the above items according to the instructions stored in the memory.

[0016] In a third aspect, the present application discloses a computer-readable storage medium storing instructions for executing the method for designing a packaging substrate as described in any one of the above items.

[0017] In a fourth aspect, the present application discloses a packaging substrate, comprising a core layer and a plurality of metal layers and a plurality of dielectric layers respectively located on both sides of the core layer; the core layer or the dielectric layer is located between adjacent metal layers, and adjacent metal layers are connected by vias penetrating the core layer or the dielectric layer; the vias penetrating the core layer are first vias; the vias penetrating the dielectric layer are second vias; each of the first vias is connected to a plurality of second vias, the plurality of second vias are arranged around the first via, and the plurality of second vias are arranged in a trapezoidal shape.

[0018] In this way, the area of ​​the first via and the multiple second vias connected thereto can be reduced by arranging the multiple second vias in a trapezoidal shape, thereby reducing the area of ​​the hollowed-out region of the conductive plane having different properties from the first via. Further, at the same via density, the area of ​​the conductive plane between the hollowed-out regions can be increased, thereby reducing the probability of the conductive plane being disconnected and improving the conductivity of the conductive plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0020] Figure 1 The figure is a schematic diagram of the cross-sectional structure of a packaging substrate.

[0021] Figure 2 The present invention is a schematic structural diagram of a first via hole, a second via hole connected thereto, and an adjacent metal layer.

[0022] Figure 3 This is a flow chart of a method for designing a packaging substrate disclosed in an embodiment of the present application.

[0023] Figure 4 It is a schematic diagram of the three-dimensional structure of a first via hole and a second via hole connected thereto disclosed in an embodiment of the present application.

[0024] Figure 5 The schematic diagram of the top view structure of a first via hole and a second via hole connected thereto disclosed in an embodiment of the present application.

[0025] Figure 6 This is a schematic structural diagram of a plurality of first vias and second vias connected thereto disclosed in an embodiment of the present application.

[0026] Figure 7 It is a schematic structural diagram of a first via hole, a second via hole connected thereto, and an adjacent metal layer disclosed in an embodiment of the present application.

[0027] Figure 8 This is a schematic structural diagram of a plurality of first vias and second vias connected thereto disclosed in an embodiment of the present application.

[0028] Fig. 9 This is a schematic diagram of the structure of another plurality of first vias and second vias connected thereto disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] The bare die usually needs to be packaged together with the packaging substrate connected to it to form a chip packaging structure connected to the printed circuit board. Figure 1 As shown, Figure 1 The cross-sectional structure diagram of a package substrate includes a core layer 110 and a plurality of metal layers 111 and a plurality of dielectric layers 112 respectively located on both sides of the core layer 110. The core layer 110 or the dielectric layer 112 is located between adjacent metal layers 111, and the conductive traces 1110 or conductive planes 1111 on adjacent metal layers 111 are connected through vias penetrating the core layer 110 or the dielectric layer 112. The conductive traces 1110 or conductive planes 1111 on the outermost metal layer 111 are connected to the bare die through the first pad 113, and are connected to the printed circuit board through the second pad 114.

[0031] The via hole penetrating the core layer 110 is the first via hole 1112, and the via hole connected to the first via hole 1112 and penetrating the dielectric layer 112 adjacent to the core layer 110 is the second via hole 1113. Figure 2 As shown, Figure 2 The schematic diagram is a structural diagram of a first via hole, a second via hole connected thereto, and an adjacent metal layer, wherein the first via hole 1112 is connected to four second via holes 1113, and the four second via holes 1113 are arranged around the first via hole 1112, and the four second via holes 1113 are arranged in a central symmetric manner. Optionally, the first via hole 1112 is a plated through hole (PTH for short), and the second via hole 1113 is a blind buried hole.

[0032] Furthermore, in order to prevent the conductive plane 1111 having different properties from the first via 1112 in the metal layer 111 adjacent to the core layer 110 from affecting the quality of the signal transmitted by the first via 1112, the area of ​​the conductive plane 1111 whose orthographic projection overlaps with the first via 1112 and the second via 1113 connected thereto is hollowed out. The properties of the first via 1112 may be power, ground, or signal, and the properties of the conductive plane 1111 may also be power, ground, or signal, etc.

[0033] However, as the integration of the package substrate increases, the density of the first vias 1112 increases, and the density of the hollowed-out areas of the conductive plane 1111 increases, which may easily cause some of the hollowed-out areas of the conductive plane 1111 to be connected together. Figure 2As shown, one hollowed-out area A1 is connected to another hollowed-out area B1 , resulting in that part of the non-hollowed-out area of ​​the conductive plane 1111 is disconnected, thus affecting the conductivity of the conductive plane 1111 .

[0034] Based on this, the present application discloses a design scheme for a packaging substrate, which reduces the area of ​​the first via and the second via connected thereto by designing the arrangement pattern of the four second vias into a trapezoid, and reduces the area of ​​the hollowed-out region of the conductive plane having different properties from the first via. As a result, at the same via density, the area of ​​the conductive plane between the hollowed-out regions can be increased, thereby reducing the probability of the conductive plane being disconnected and improving the conductivity of the conductive plane.

[0035] As an optional implementation of the disclosure of this application, the embodiment of this application discloses a design method for a packaging substrate, such as Figure 3 As shown, Figure 3 This is a flow chart of a design method for a packaging substrate disclosed in an embodiment of the present application, the design method comprising:

[0036] S101: Obtain a radius of a first via hole of a packaging substrate, a radius of a second via hole connected to the first via hole, and a hole spacing.

[0037] like Figure 1 As shown, the first via hole 1112 is a via hole penetrating the core layer 110 of the package substrate, and the second via hole 1113 is a via hole connected to the first via hole 1112 and penetrating the adjacent dielectric layer 112 of the core layer 110. The parameters of the first via hole 1112 and the second via hole 1113 are pre-designed, and the radius of the first via hole 1112, the radius of the second via hole 1113, and the hole spacing can be obtained by obtaining the design parameters of the package substrate.

[0038] It should be noted that the hole pitch refers to the minimum pitch between adjacent vias. For example, the hole pitch is the minimum pitch between the first vias 1112 and the first vias 1112, the minimum pitch between the second vias 1113 and the second vias 1113, and the minimum pitch between the first via 1112 and the second via 1113 that is not connected thereto.

[0039] S102: Obtaining a positional relationship between a first via hole and a second via hole connected thereto according to a radius of the first via hole, a radius of the second via hole, a hole spacing, and preset positional constraints of the first via hole and a plurality of second via holes connected thereto.

[0040] like Figure 4 and Figure 5 As shown, Figure 4 Schematic diagram of a three-dimensional structure of a first via hole and a second via hole connected thereto disclosed in an embodiment of the present application. Figure 5The schematic diagram of the top view structure of a first via hole and a second via hole connected thereto disclosed in an embodiment of the present application, wherein the preset position constraints of the first via hole 1112 and the plurality of second via holes 1113 connected thereto include: the plurality of second via holes 1113 are arranged around the first via hole 1112, and the plurality of second via holes 1113 are arranged in a trapezoidal shape. Optionally, the plurality of second via holes 1113 are arranged in an isosceles trapezoidal shape.

[0041] It should be noted that the position constraint condition only limits the multiple second vias 1113 to be arranged in a trapezoidal shape, but does not limit the specific parameters of the trapezoid, for example, the two angles α and β of the trapezoid are not limited. Therefore, in the specific application process, it is necessary to calculate the angles α and / or β of the trapezoid according to specific requirements and the radius R1 of the first via 1112, the radius R2 of the second via 1113, and the hole spacing D, so as to obtain the size relationship between the center coordinates of the first via 1112 and the center coordinates of the second via 1113, that is, to obtain the positional relationship between the first via 1112 and the second via 1113 connected thereto.

[0042] S103: Arrange any first via hole among a plurality of first via holes of the packaging substrate and a second via hole connected thereto according to a positional relationship between the first via hole and the second via hole connected thereto.

[0043] After the positional relationship between the first via hole 1112 and the second via hole 1113 connected thereto is obtained, the positional relationship between any first via hole 1112 among the plurality of first via holes 1112 in the packaging substrate and the second via hole 1113 connected thereto can be obtained.

[0044] In some embodiments of the present invention, Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of a plurality of first vias and second vias connected thereto disclosed in an embodiment of the present application, wherein the plurality of first vias 1112 are arranged in an array in a first direction X and a second direction Y, and the positional relationship between any two first vias 1112 and the second vias 1113 connected thereto are the same, and the first direction X and the second direction Y intersect.

[0045] And, in some embodiments, as Figure 6 As shown, the second via holes 1113 of two adjacent first via holes 1112 in the first direction X are arranged center-symmetrically, and the second via holes 1113 of two adjacent first via holes 1112 in the second direction Y are arranged axis-symmetrically, so as to increase the density of the first via holes 1112 .

[0046] Of course, the present application is not limited thereto, and in other embodiments, without considering the maximum density, the second vias 1113 of two adjacent first vias 1112 in the first direction X may also be arranged axially symmetrically. In addition, the spacing between any two adjacent first vias 1112, second vias 1113, or first vias 1112 and second vias 1113 is greater than or equal to the above-mentioned hole spacing.

[0047] like Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of a first via, a second via connected thereto, and an adjacent metal layer disclosed in an embodiment of the present application. By arranging the plurality of second vias 1113 in a trapezoidal shape, the area of ​​the first via 1112 and the plurality of second vias 1113 connected thereto can be reduced, thereby reducing the area of ​​the hollowed-out region of the conductive plane 1111 having different properties from the first via 1112, for example, reducing the area of ​​one hollowed-out region A2 and another hollowed-out region B2, and further increasing the area of ​​the conductive plane 1111 between the hollowed-out regions at the same via density, for example, increasing the area of ​​the conductive plane 1111 between one hollowed-out region A2 and another hollowed-out region B2, thereby reducing the probability of the conductive plane 1111 being disconnected, improving the current carrying capacity, i.e., the conductivity, of the conductive plane 1111, and improving the power distribution network (PDN) impedance of the packaging substrate.

[0048] The performance of the package substrate is described below in combination with the through-hole adequacy coefficient of the bump and the core-layer via adequacy coefficient of the transfer hole. The parallelogram surrounded by four first vias 1112 is used as the sampling area. The ratio of the number of bumps, i.e., first pads 113, in the sampling area to the number of core-layer vias, i.e., first vias 1112 is called the through-hole adequacy coefficient of the bump, and the ratio of the number of transfer holes, i.e., second vias 1113, connecting the core-layer vias, i.e., first vias 1112, in the sampling area to the number of core-layer vias, i.e., first vias 1112 is called the core-layer via adequacy coefficient of the transfer hole. Among them, the smaller the through-hole adequacy coefficient of the bump, the more core-layer vias corresponding to the bump in the sampling area, and the better the power connectivity. The smaller the core-layer via adequacy coefficient of the transfer hole, the more core-layer vias corresponding to the transfer hole in the sampling area, and the better the power connectivity.

[0049] In a package substrate including 10 or less metal layers 111, the bumps, i.e., the first pads 113, will affect the connection of the core layer vias, i.e., the first vias 1112, resulting in the inability to increase the density of the first vias 1112. Therefore, compared with the centrally symmetrical arrangement of the plurality of second vias 1113, the through hole margin coefficient of the bumps and the core layer via margin coefficient of the transfer holes in the trapezoidal arrangement of the plurality of second vias 1113 remain substantially unchanged, and only the electrical connectivity of the conductive plane 1111 is additionally increased.

[0050] In a package substrate including 12 or more metal layers 111, since the connection between the bump, i.e., the first pad 113, and the core layer via, i.e., the first via 1112, is decoupled, there is no clear requirement for the position of the transfer hole, i.e., the second via 1113, of the core layer via 1112, and the density of the first via 1112 can be increased. Therefore, compared with the centrally symmetrical arrangement of the plurality of second vias 1113, the through hole margin factor of the bump, the core layer via margin factor of the transfer hole, and the electrical connectivity of the conductive plane 1111 are all improved in the trapezoidal arrangement of the plurality of second vias 1113.

[0051] In some embodiments of the present application, the positional relationship between the first via 1112 and the second vias 1113 connected thereto can be obtained based on the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset positional constraints of the first via 1112 and the plurality of second vias 1113 connected thereto, and the preset arrangement constraints of the first via 1112. The arrangement constraints of the first via 1112 include: the area of ​​the hollowed-out region of the conductive plane 1111 having different properties from the first via 1112 is the smallest, or the density of the first vias 1112 is the largest.

[0052] For example, when the arrangement constraint of the first via 1112 is that the area of ​​the hollowed-out region of the conductive plane 1111 having properties different from those of the first via 1112 is minimized, the positional relationship between the first via 1112 and the second vias 1113 connected thereto can be obtained based on the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, and an operation method.

[0053] When the arrangement constraint condition of the first via 1112 is that the density of the first via 1112 is the maximum, the positional relationship between the first via 1112 and the second vias 1113 connected thereto can be obtained based on the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, and another calculation method.

[0054] Of course, the present application is not limited to this, and in other embodiments, the positional relationship between the first via 1112 and the second via 1113 connected thereto may be obtained according to other arrangement constraints. In other embodiments, if the arrangement constraints and calculation method of the first via 1112 have been pre-set, the positional relationship between the first via 1112 and the second via 1113 connected thereto may be obtained directly according to the radius of the first via 1112, the radius of the second via 1113, the hole spacing, and the preset positional constraints of the first via 1112 and the plurality of second vias 1113 connected thereto.

[0055] In some embodiments of the present application, when the arrangement constraint of the first via 1112 is that the area of ​​the hollowed-out region of the conductive plane 1111 having properties different from those of the first via 1112 is minimized, the positional relationship between the first via 1112 and the second vias 1113 connected thereto can be obtained based on the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset positional constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the preset positional relationship between adjacent first vias 1112 in the first direction X, and the preset positional relationship between adjacent second vias 1113, or the preset positional relationship between the first via 1112 and the second via 1113 not connected thereto.

[0056] In some embodiments, Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a plurality of first vias and second vias connected thereto disclosed in an embodiment of the present application. According to the radius r1 of the first via 1112, the hole spacing D, and the preset positional relationship of the adjacent first vias 1112 in the first direction X, the functional relationship of the first side length OB of the triangle OBC where the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected thereto is located is obtained. Among them, the preset positional relationship of the adjacent first vias 1112 in the first direction X is: the spacing between the adjacent first vias 1112 is equal to the hole spacing D. The functional relationship of the first side length OB is: OB = 1 / 2 (2 × r1 + D).

[0057] The functional relationship of the second side length OC of the triangle OBC is obtained according to the radius r2 of the second via hole 1113, the hole spacing D and the preset positional relationship of the adjacent second via holes 1113. The preset positional relationship of the adjacent second via holes 1113 is: the spacing between the adjacent second via holes 1113 is equal to the hole spacing D. The functional relationship of the second side length OC is: OC=1 / 2(2×r2+D).

[0058] According to the radius r1 of the first via 1112, the radius r2 of the second via 1113, and the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the functional relationship of the third side length BC of the triangle OBC is obtained. Among them, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto include: the spacing between the first via 1112 and the second vias 1113 connected thereto is equal to 0. The functional relationship of the third side length BC is: BC=r1+r2.

[0059] According to the functional relationship of the first side length OB, the second side length OC and the third side length BC of the triangle OBC, the first angle α between the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected thereto and the first direction X is calculated.

[0060] According to the cosine theorem,

[0061] According to the first angle α between the center line BC and the first direction X, the positional relationship between the first via 1112 and a second via 1113 connected thereto is obtained, that is, the size relationship between the center coordinates of the first via 1112 and a second via 1113 connected thereto is obtained.

[0062] Of course, the present application is not limited to this. In other embodiments, the functional relationship of the first side length AB of the triangle ABC where the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected thereto is located can be obtained according to the radius r1 of the first via 1112, the hole spacing D, and the preset positional relationship of the adjacent first vias 1112 in the first direction X. Among them, the preset positional relationship of the adjacent first vias 1112 in the first direction X is: the spacing between the adjacent first vias 1112 is equal to the hole spacing D. The functional relationship of the first side length AB is: AB=2×r1+D.

[0063] According to the radius r1 of the first via hole 1112, the radius r2 of the second via hole 1113, the hole spacing D, and the positional relationship between the first via hole 1112 and the second via hole 1113 not connected thereto, the functional relationship of the second side length AC of the triangle ABC is obtained. Among them, the preset positional relationship between the first via hole 1112 and the second via hole 1113 not connected thereto is: the spacing between the first via hole 1112 and the second via hole 1113 not connected thereto is equal to the hole spacing D. The functional relationship of the second side length AC is: AC=r1+r2+D.

[0064] According to the radius r1 of the first via 1112, the radius r2 of the second via 1113, and the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the functional relationship of the third side length BC of the triangle ABC is obtained. Among them, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto include: the spacing between the first via 1112 and the second vias 1113 connected thereto is equal to 0. The functional relationship of the third side length BC is: BC=r1+r2.

[0065] According to the functional relationship of the first side length AB, the second side length AC and the third side length BC of triangle ABC, the first angle α between the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected thereto and the first direction X is calculated.

[0066] According to the cosine theorem,

[0067] In some embodiments of the present application, when the arrangement constraint condition of the first via 1112 is that the density of the first via 1112 is the maximum, the positional relationship between the first via 1112 and the second vias 1113 connected thereto can be obtained based on the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset positional constraint conditions of the first via 1112 and the multiple second vias 1113 connected thereto, the preset positional relationship between adjacent first vias 1112 in the first direction X, the preset positional relationship between adjacent second vias 1113, and the preset positional relationship between the first via 1112 and the second vias 1113 not connected thereto.

[0068] On this basis, in some embodiments of the present application, the positional relationship between the first via 1112 and a second via 1113 connected thereto can be obtained according to the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset positional constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the preset positional relationship between the adjacent first vias 1112 in the first direction X, and the preset positional relationship between the adjacent second vias 1113, or the preset positional relationship between the first via 1112 and the second via 1113 not connected thereto; the positional relationship between the first via 1112 and another second via 1113 connected thereto can be obtained according to the radius of the first via 1112, the radius of the second via 1113, the hole spacing, the preset positional constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the preset positional relationship between the first via 1112 and the second via 1113 not connected thereto, and the preset positional relationship between the adjacent second vias 1113.

[0069] It should be noted that, because the other two second vias 1113 are arranged symmetrically with the two second vias 1113 about the second direction Y, the positional relationship between the first via 1112 and the two second vias 1113 can be obtained, and the positional relationship between the first via 1112 and the four second vias 1113 can be obtained.

[0070] Wherein, according to the radius of the first via hole 1112, the radius of the second via hole 1113, the hole spacing, the preset position constraint conditions of the first via hole 1112 and the plurality of second via holes 1113 connected thereto, the preset position relationship of the adjacent first via holes 1112 in the first direction X and the preset position relationship of the adjacent second via holes 1113, or the preset position relationship of the first via hole 1112 and the second via hole 1113 not connected thereto, the method for obtaining the position relationship of the first via hole 1112 and the second via hole 1113 connected thereto can refer to Figure 8 And related descriptions will not be repeated here.

[0071] On this basis, in some embodiments of the present application, the size of the second angle can be obtained according to the radius of the first via hole 1112, the radius of the second via hole 1113, the hole spacing, the preset position constraint conditions of the first via hole 1112 and the multiple second via holes 1113 connected thereto, the preset position relationship between the first via hole 1112 and the second via hole 1113 not connected thereto, and the preset position relationship between the adjacent second via holes 1113; the second angle is the distance between the center of the first via hole 1112 and the center of a second via hole 1113 connected thereto and the center of the first via hole 1112 and the center of a second via hole 1113 not connected thereto. The third angle is obtained according to the second angle, the first angle, the radius of the first via 1112, the hole spacing, the radius of the second via 1113, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, and the preset position relationship between the first via 1112 and the second via 1113 not connected thereto; the third angle is the angle between the center of the first via 1112 and the center of another second via 1113 connected thereto and the second direction Y; according to the third angle, the position relationship between the first via 1112 and another second via 1113 connected thereto is obtained.

[0072] like Fig. 9 As shown, Fig. 9This is another schematic diagram of the structure of multiple first vias and second vias connected thereto disclosed in an embodiment of the present application. According to the radius r2 of the second via 1113, the hole spacing D and the preset positional relationship of the adjacent second vias 1113, the functional relationship of the first side length CF of the triangle BCF where the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected thereto is located is obtained. Among them, the preset positional relationship of the adjacent second vias 1113 is: the spacing between the adjacent second vias 1113 is equal to the hole spacing D. The functional relationship of the first side length CF is: CF = 2×r2+D.

[0073] According to the radius r1 of the first via hole 1112, the radius r2 of the second via hole 1113, the hole spacing D, and the positional relationship between the first via hole 1112 and the second via hole 1113 not connected thereto, the functional relationship of the second side length BF of the triangle BCF is obtained. Among them, the preset positional relationship between the first via hole 1112 and the second via hole 1113 not connected thereto is: the spacing between the first via hole 1112 and the second via hole 1113 not connected thereto is equal to the hole spacing D. The functional relationship of the second side length BF is: BF=r1+r2+D.

[0074] According to the radius r1 of the first via 1112, the radius r2 of the second via 1113, and the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the functional relationship of the third side length BC of the triangle BCF is obtained. Among them, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto include: the spacing between the first via 1112 and the second vias 1113 connected thereto is equal to 0. The functional relationship of the third side length BC is: BC=r1+r2.

[0075] According to the functional relationship of the first side length CF, the second side length BF and the third side length BC of the triangle BCF, the second angle γ between the line BC connecting the center of the first via 1112 and the center of a second via 1113 connected to it and the line BF connecting the center of the first via 1112 and the center of a second via 1113 not connected to it is calculated.

[0076] According to the cosine theorem,

[0077] Taking the perpendicularity between the first direction X and the second direction Y as an example, since ∠ABE=90°, ∠FBE=90°-α-γ. According to ∠FBE and the cosine theorem, the functional relationship of the side length BE can be obtained.

[0078] According to the radius r1 of the first via 1112, the radius r2 of the second via 1113, and the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto, the functional relationship of the third side length EF of the triangle FEB is obtained. Among them, the preset position constraints of the first via 1112 and the multiple second vias 1113 connected thereto include: the spacing between the first via 1112 and the second vias 1113 connected thereto is equal to 0. The functional relationship of the third side length EF is: EF=r1+r2.

[0079] According to the functional relationship of the first side length BE, the second side length BF and the third side length EF of the triangle FEB, the third angle β between the line EF connecting the center of the first via 1112 and the center of the other second via 1113 connected thereto and the second direction Y can be calculated. According to the third angle β, the positional relationship between the first via 1112 and the other second via 1113 connected thereto can be obtained, that is, the size relationship between the center coordinates of the first via 1112 and the center coordinates of the other second via 1113 connected thereto can be obtained.

[0080] in,

[0081] Assuming that the center coordinates of the first via 1112 are (x0, y0), the center coordinates of a second via 1113 connected thereto are (x1, y1), and the center coordinates of another second via 1113 connected thereto are (x2, y2), then (x1-x0) / (r1+r2)=cosα, (y1-y0) / (r1+r2)=sinα, (x2-x0) / (r1+r2)=sinβ, (y2-y0) / (r1+r2)=cosβ. Assuming that the center coordinates of another second via 1113 symmetrical to a second via 1113 are (x3, y3), then y3=y1, [(x1-x3) / 2] / (r1+r2)=sin(90°-α). Assuming that the center coordinates of another second via hole 1113 symmetrical to another second via hole 1113 are (x4, y4), then y4=y2, x2-x4=2r2.

[0082] As another optional implementation of the content disclosed in this application, the embodiment of this application also discloses a packaging substrate, referring to Figure 1 The package substrate includes a core layer 110 and a plurality of metal layers 111 and a plurality of dielectric layers 112 respectively located on both sides of the core layer 110. The core layer 110 or the dielectric layer 112 is located between adjacent metal layers 111, and the traces 1110 or the conductive planes 1111 on adjacent metal layers 111 are connected through vias penetrating the core layer 110 or the dielectric layer 112.

[0083] The via hole penetrating the core layer 110 is the first via hole 1112, and the via hole connected to the first via hole 1112 and penetrating the dielectric layer 112 adjacent to the core layer 110 is the second via hole 1113. Figure 4 and Figure 5 As shown, the first via hole 1112 is connected to a plurality of second via holes 1113 , and the plurality of second via holes 1113 are arranged around the first via hole 1112 , and the plurality of second via holes 1113 are arranged in a trapezoidal shape. Optionally, the first via hole 1112 is connected to four second via holes 1113 .

[0084] In some embodiments of the present application, Figure 6 As shown, a plurality of first via holes 1112 of the package substrate are arranged in an array in the first direction X and the second direction Y, and the positional relationship between any first via hole 1112 and the second via hole 1113 connected thereto is the above positional relationship, and the first direction X and the second direction Y intersect.

[0085] And, in some embodiments, as Figure 6 As shown, the second vias 1113 of two adjacent first vias 1112 in the first direction X are arranged axially symmetrically, and the second vias 1113 of two adjacent first vias 1112 in the second direction Y are arranged centrally symmetrically, so as to increase the density of the first vias 1112. Of course, the present application is not limited thereto, and in other embodiments, without considering the maximum density, the second vias 1113 of two adjacent first vias 1112 in the second direction Y may also be arranged axially symmetrically. In addition, the spacing between any two vias is greater than or equal to the above-mentioned hole spacing.

[0086] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer device, including a memory and a processor; the memory is used to store instructions; the processor is used to execute the design method of the packaging substrate disclosed in any of the above embodiments according to the instructions stored in the memory.

[0087] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer-readable storage medium on which instructions for executing the design method of the packaging substrate disclosed in any of the above embodiments are stored.

[0088] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0089] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer program product, which includes computer program instructions, and when the computer program instructions are executed by a processor, the processor executes the design method of the packaging substrate disclosed in any of the above embodiments.

[0090] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0091] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A method for designing a packaging substrate, characterized in that: include: Obtaining a radius of a first via hole of a packaging substrate, a radius of a second via hole connected to the first via hole, and a hole spacing; The first via hole comprises a via hole penetrating through the core layer of the packaging substrate; the second via hole comprises a via hole penetrating through the dielectric layer of the packaging substrate; According to the radius of the first via hole, the radius of the second via hole, the hole spacing, and the preset position constraint conditions of the first via hole and the plurality of second via holes connected thereto, the position relationship between the first via hole and the second via holes connected thereto is obtained; wherein the position constraint conditions include: the plurality of second via holes are arranged around the first via hole, and the plurality of second via holes are arranged in a trapezoidal shape; According to the positional relationship between the first via hole and the second via hole connected thereto, any first via hole among the plurality of first via holes of the packaging substrate and the second via hole connected thereto are arranged.

2. The method according to claim 1, characterized in that The obtaining the positional relationship between the first via hole and the second via holes connected thereto according to the radius of the first via hole, the radius of the second via hole, the hole spacing, and the preset positional constraints of the first via hole and the plurality of second via holes connected thereto comprises: Obtaining a positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, a preset position constraint condition of the first via and a plurality of second vias connected thereto, and a preset arrangement constraint condition of the first via; The arrangement constraint conditions of the first vias include: the area of ​​the hollowed-out region of the conductive plane having different properties from those of the first vias is the smallest, or the density of the first vias is the largest.

3. The method according to claim 2, characterized in that The obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the plurality of second vias connected thereto, and the preset arrangement constraints of the first via comprises: When the arrangement constraint of the first via is that the area of ​​the hollowed-out region of the conductive plane with different properties from the first via is minimized, the positional relationship between the first via and one of the second vias connected to it is obtained based on the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and multiple second vias connected to it, the preset positional relationship between adjacent first vias in the first direction, and the preset positional relationship between adjacent second vias.

4. The method according to claim 2, characterized in that: The obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints of the first via and the plurality of second vias connected thereto, and the preset arrangement constraints of the first via comprises: When the arrangement constraint of the first via is that the density of the first via is maximum, the positional relationship between the first via and the second via connected to it is obtained according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraint of the first via and the multiple second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, the preset positional relationship between the adjacent second vias, and the preset positional relationship between the first via and the second vias not connected thereto.

5. The method according to claim 4, characterized in that The obtaining the positional relationship between the first via and the second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraint conditions between the first via and the plurality of second vias connected thereto, the preset positional relationship between the first vias adjacent to each other in the first direction, the preset positional relationship between the second vias adjacent to each other, and the preset positional relationship between the first via and the second vias not connected thereto comprises: Obtaining a positional relationship between the first via and one of the second vias connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, a preset positional constraint condition between the first via and a plurality of second vias connected thereto, a preset positional relationship between adjacent first vias in the first direction, and a preset positional relationship between adjacent second vias; The positional relationship between the first via and another second via connected to it is obtained based on the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and multiple second vias connected to it, the preset positional relationship between the first via and a second via not connected to it, and the preset positional relationship between the adjacent second vias.

6. The method according to claim 3 or 5, characterized in that: The obtaining the positional relationship between the first via and one of the second vias connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and a plurality of second vias connected thereto, the preset positional relationship between the first vias adjacent thereto in the first direction, and the preset positional relationship between the second vias adjacent thereto comprises: Obtaining a functional relationship of a first side length of a triangle where a line connecting the center of the first via hole and the center of one of the second via holes connected thereto lies according to the radius of the first via hole, the hole spacing, and a preset positional relationship of adjacent first via holes in the first direction; Obtaining a functional relationship of the second side length of the triangle according to the radius of the second via hole, the hole spacing, and a preset positional relationship between adjacent second via holes; Obtaining a functional relationship of the third side length of the triangle according to the radius of the first via hole, the radius of the second via hole, and preset position constraints of the first via hole and a plurality of second via holes connected thereto; A first angle is obtained according to a functional relationship of the first side length of the triangle, a functional relationship of the second side length of the triangle, and a functional relationship of the third side length of the triangle; the first angle is an angle between a line connecting the center of the first via hole and the center of one of the second via holes connected thereto and the first direction; According to the first angle, a positional relationship between the first via hole and one of the second via holes connected thereto is obtained.

7. The method according to claim 6, characterized in that The obtaining the positional relationship between the first via and another second via connected thereto according to the radius of the first via, the radius of the second via, the hole spacing, the preset positional constraints between the first via and a plurality of second vias connected thereto, the preset positional relationship between the first via and a second via not connected thereto, and the preset positional relationship between the adjacent second vias comprises: A second angle is obtained according to the radius of the first via hole, the radius of the second via hole, the hole spacing, a preset position constraint condition of the first via hole and a plurality of second via holes connected thereto, a preset position relationship between the first via hole and a second via hole not connected thereto, and a preset position relationship between adjacent second via holes; the second angle is the angle between a line connecting the center of the first via hole and the center of one of the second via holes connected thereto and a line connecting the center of the first via hole and the center of one of the second via holes not connected thereto; A third angle is obtained according to the second angle, the first angle, the radius of the first via hole, the hole spacing, the radius of the second via hole, a preset position constraint condition of the first via hole and a plurality of second via holes connected thereto, and a preset position relationship between the first via hole and a second via hole not connected thereto; the third angle is an angle between a line connecting the center of the first via hole and the center of another second via hole connected thereto and a second direction; the second direction intersects the first direction; According to the third angle, the positional relationship between the first via hole and another second via hole connected thereto is obtained.

8. A computer device, characterized in that: including memory and processor; The memory is used to store instructions; The processor is used to execute the packaging substrate design method as described in any one of claims 1 to 7 according to the instructions stored in the memory.

9. A computer-readable storage medium, characterized in that: Instructions for executing the method for designing a packaging substrate as claimed in any one of claims 1 to 7 are stored thereon.

10. A packaging substrate, characterized in that: It comprises a core layer and a plurality of metal layers and a plurality of dielectric layers respectively located on both sides of the core layer; The core layer or the dielectric layer is located between adjacent metal layers, and the adjacent metal layers are connected via vias penetrating the core layer or the dielectric layer; The via hole penetrating the core layer is a first via hole; The via hole penetrating the dielectric layer is a second via hole; Each of the first via holes is connected to a plurality of second via holes, the plurality of second via holes are arranged around the first via holes, and the plurality of second via holes are arranged in a trapezoidal shape.

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