General JPEG grayscale image compression module based on FPGA

Abstract

The invention provides an FPGA-based universal JPEG grayscale image compression module. The FPGA-based universal JPEG grayscale image compression module comprises a grayscale data caching module, a grayscale data reading module, a one-dimensional DCT conversion module, a two-dimensional DCT conversion module, a quantization module, a zigzag scanning module, a DC coefficient coding module, an AC coefficient coding module, a JPEG data stream generation module and an output framing module. According to the method, the storage area occupied by the image data in the DDR3 is stipulated by configuring the initial storage address of the DDR3; by configuring image width and image height parameters, performing JPEG (Joint Photographic Experts Group) compression processing on any grayscale image which is smaller than the capacity of the DDR memory and has image height and image width which are positive multiples of 8; adjusting the speed of an image compression process by configuring a compression speed parameter; and the quality of the compressed image and the total data volume of the JPEG data stream are accurately controlled by configuring an image compression ratio parameter. The transmission efficiency of the remote sensing image is improved, and the occupied storage space is reduced; and the method can be conveniently and flexibly applied through parameterized configuration, and is easy to transplant and high in universality.

Description

Technical Field

[0001] The invention relates to the field of electrical technology, and in particular to a universal JPEG grayscale image compression module based on FPGA. Background Art

[0002] In recent years, with the update and iteration of various imaging equipment technologies such as radar and cameras, the images they generate have become larger, with higher frame rates and richer details. Direct transmission and storage of original images will extend the transmission time and consume a lot of resources for communication equipment and storage devices. However, through image compression, redundant information (time, space, spectrum redundancy, etc.) in the image can be removed without or with little loss of image quality, and most of the necessary information of the image can be retained, which significantly improves transmission efficiency, reduces storage usage, and improves the real-time performance of image processing.

[0003] Existing image compression algorithms are mainly divided into two categories, namely lossless compression and lossy compression. Lossless compression means that no information of the image is lost, and it is achieved simply by encoding the statistical characteristics of the data stream, but this type of compression usually cannot meet the requirements of high compression ratios. Lossy compression refers to the loss of certain redundant information or insensitive information during the compression process, which will not have much impact on subsequent image processing, but can achieve a high compression ratio. The JPEG compression algorithm is the most widely used lossy compression algorithm, which has the characteristics of high compression efficiency and simple and easy-to-implement algorithm. It is widely used in digital photography, network transmission, remote sensing communication and other fields.

[0004] Compared with the traditional method of implementing JPEG compression algorithm only by software, the advantages of FPGA are reflected in efficient parallel processing, strong customizability, high resource utilization, etc. Therefore, in many application scenarios with high real-time requirements, researchers prefer to implement image compression based on FPGA.

[0005] Therefore, there is an urgent need for an efficient method for JPEG compression using FPGA. Summary of the invention

[0006] The present invention is to solve the problem of JPEG compression coding efficiency, and provides a universal JPEG grayscale image compression module based on FPGA. By configuring the starting storage address of DDR3, the storage area occupied by image data in DDR3 is specified; by configuring the image width and image height parameters, JPEG compression processing can be performed on any grayscale image that is smaller than the DDR memory capacity and whose image height and image width are both positive multiples of 8; by configuring the compression speed parameter, the speed of the image compression process can be adjusted; by configuring the image compression ratio parameter, the compressed image quality and the total data volume of the JPEG data stream can be accurately controlled. The present invention integrates different functions into a pipeline design, greatly improving the processing efficiency of the data stream, and at the same time, multiple configurable parameter interfaces are designed at the input end, increasing the flexibility of application.

[0007] The present invention provides a universal JPEG grayscale image compression module based on FPGA, comprising a grayscale data cache module, a grayscale data reading module, a one-dimensional DCT transformation module, a two-dimensional DCT transformation module, a quantization module, a zigzag scanning module, a DC coefficient encoding module and an AC coefficient encoding module, which are electrically connected in sequence to the output end of the zigzag scanning module, and a JPEG data stream generation module and an output framing module, which are electrically connected in sequence to the output end of the DC coefficient encoding module and the output end of the AC coefficient encoding module.

[0008] The grayscale data cache module writes the input grayscale image to be processed pixel by pixel in sequence into the FPGA memory and generates a write completion flag signal after the writing is completed. The grayscale data reading module reads the write completion flag signal and reads the grayscale data one by one from the FPGA memory according to the compression speed parameter by pixel block. The one-dimensional DCT transformation module performs a one-dimensional DCT transformation on each row of grayscale data in the pixel block to obtain a one-dimensional DCT transformation result. The two-dimensional DCT transformation module performs a two-dimensional DCT transformation on the one-dimensional DCT transformation result to obtain a two-dimensional DCT transformation result. The quantization module quantizes the two-dimensional DCT transformation result according to the brightness quantization table to obtain the pixel block. quantization result, the zigzag scanning module converts the quantization result of the pixel block into a zigzag sequence, the sequence head of the zigzag sequence is the DC coefficient, and the sequence head is the AC coefficient, the DC coefficient encoding module encodes the DC coefficient to obtain the DC Huffman encoding result, the AC coefficient encoding module encodes the AC coefficient to obtain the AC Huffman encoding result, the JPEG data stream generation module integrates the DC Huffman encoding result and the AC Huffman encoding result to obtain the JPEG data stream, and the output framing module supplements the JPEG data stream with the frame header information and fills the JPEG data stream with zeros to the data amount corresponding to the image compression ratio parameter, and then outputs the compressed data frame result;

[0009] The two-dimensional DCT transform module uses a pipelined data processing method, and the JPEG data stream generation module and the output framing module both use a state machine method for timing control;

[0010] Before compressing the grayscale image to be processed, processing parameters are set, and the processing parameters include the starting storage address of the FPGA memory, image width, image height, compression speed parameter and image compression ratio parameter.

[0011] The present invention discloses a universal JPEG grayscale image compression module based on FPGA. As a preferred embodiment, the FPGA memory is a DDR3 memory external to the FPGA. The minimum value of the starting storage address of the DDR3 memory is 0 and the storage space after the starting storage address is sufficient to accommodate the size of a whole frame of image. The storage area occupied by the image data in the DDR3 is specified by configuring the starting storage address of the DDR3.

[0012] The image width and image height of the grayscale image to be processed are both positive integer multiples of 8;

[0013] The grayscale data cache module controls the grayscale data of each row in each 8*8 pixel block to be read out row by row from top to bottom by operating the DDR3 memory address. The pixel blocks are output block by block from top to bottom and from left to right. The reading interval between pixel blocks is controlled by the compression speed parameter.

[0014] The grayscale data cache module first converts the 8-bit unsigned pixel grayscale value into an 8-bit signed number, and then converts it into a 16-bit signed number by padding the high bit so that the grayscale values ​​of every 8 adjacent pixels form a 128-bit width and are stored in one address space of the DDR3 memory.

[0015] The compression speed parameter value is greater than or equal to 119; the image compression ratio parameter range is 1 to 15;

[0016] The processing parameters cannot be modified during the compression process of the grayscale image to be processed.

[0017] The present invention discloses a universal JPEG grayscale image compression module based on FPGA, and as a preferred embodiment, the pipeline data processing method includes the following steps:

[0018] SA1, the two-dimensional DCT transform module sequentially caches the one-dimensional DCT transform results of 1 to 8 rows input in sequence in 8 row cache fifos;

[0019] SA2, synchronously read 8 row cache fifos, after 8 clocks, all row cache fifos are read empty, and the transposition operation of row input and column reading is completed to obtain the transposed data;

[0020] SA3, read out the transposed data and input it into the one-dimensional DCT transformation module again to perform column-dimensional DCT transformation to obtain a column-dimensional DCT transformation result;

[0021] SA4, cache the column-dimensional DCT transform results of columns 1 to 8 in 8 column cache fifos in sequence;

[0022] SA5. After the 8-column data cache is completed, the 8 column cache fifos are read synchronously. After 8 clocks, all column cache fifos are read empty, and the transposition operation of column input and row reading is completed again to obtain the two-dimensional DCT transformation result.

[0023] The present invention discloses a universal JPEG grayscale image compression module based on FPGA. As a preferred embodiment, when the quantization module performs quantization processing, if the range of the configured image compression ratio parameter is 1 to 5, the brightness quantization table A is selected; if the range of the configured image compression ratio parameter is 6 to 10, the brightness quantization table B is selected; if the range of the configured image compression ratio parameter is 11 to 15, the brightness quantization table C is selected;

[0024] The quantization step of the brightness quantization table C is greater than the quantization step of the brightness quantization table B, and the quantization step of the brightness quantization table B is greater than the quantization step of the brightness quantization table A.

[0025] The present invention discloses a universal JPEG grayscale image compression module based on FPGA. As a preferred embodiment, the AC coefficient encoding module includes an encoding pipeline, and the encoding pipeline includes a stroke detection module, an AC coefficient size query module and an AC coefficient Huffman encoding lookup table module which are electrically connected in sequence;

[0026] The processing method of the encoding pipeline includes the following steps:

[0027] SB1, the stroke detection module performs zero stroke length detection on the input AC coefficient, and synchronously outputs the effective AC coefficient, zero stroke length, current sequence end flag, and stroke detection output enable after t0 time;

[0028] SB2, the effective AC coefficient is input into the AC coefficient size query module to query the tail codeword and the effective coding length of the tail codeword corresponding to the current AC coefficient. The process takes time t1. At the same time, the zero run length, the current sequence tail flag and the run detection output enable are respectively fixed with a delay of t1;

[0029] SB3, AC coefficient Huffman coding lookup table module queries and outputs the final Huffman codeword and the effective coding length of the Huffman codeword according to the effective coding length of the tail codeword and the zero run length, which takes t2. At the same time, the tail codeword, the effective coding length of the tail codeword, the current sequence tail flag and the codeword output enable a fixed delay of t2 and output to obtain the AC Huffman coding result.

[0030] The present invention discloses a universal JPEG grayscale image compression module based on FPGA. As a preferred embodiment, the timing states of the JPEG data stream generation module include: idle state, ready state, DC reading state, DC size encoding state, DC tail code state, AC reading state, AC Huffman encoding state, AC tail code state, zero padding judgment state, zero padding state and end state.

[0031] The generation method of the JPEG data stream generation module comprises the following steps:

[0032] SC1. The default state of the JPEG data stream generation module is the idle state. When the DC encoding buffer fifo becomes non-empty, step SC2 is entered;

[0033] SC2, the JPEG data stream generation module is in a ready state, and enters step SC3 after staying in the ready state for a specified period;

[0034] SC3, the JPEG data stream generation module is in the DC reading state, stays in the DC reading state for 1 clock cycle, reads a set of DC encoding results from the DC encoding buffer fifo, and then enters step SC4;

[0035] SC4, JPEG data stream generation module is in DC size encoding state, converting the read DC size code into a single bit data stream;

[0036] When the DC size coding data stream conversion is completed and the DC tail code is not all 0, it jumps to the DC tail code state, converts the DC tail code into a single bit data stream and enters step SC5;

[0037] When the DC size coding data stream conversion is completed and the DC tail code is all 0, jump to step SC5;

[0038] SC5, the JPEG data stream generation module is in the AC reading state, stays for 1 clock cycle, reads a set of AC encoding results from the AC encoding buffer fifo, and then enters step SC6;

[0039] SC6, JPEG data stream generation module is in AC Huffman coding state, converting the read AC Huffman code into a single-bit data stream;

[0040] If the current AC coefficient Huffman coding data stream conversion has been completed and the tail code is not all 0, jump to step SC7;

[0041] If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, and there are remaining AC coefficient codes in the current sequence that have not been processed, jump back to step SC5;

[0042] If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, and all AC coefficient coding of the current sequence has been processed, then jump back to step SC3 and wait for the coding result of the next sequence to arrive;

[0043] If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, the coding of all AC coefficients in the current sequence has been completed and it is the last sequence of the current frame image, then go to step SC8;

[0044] SC7, JPEG data stream generation module is in AC tail code state, converting the read AC tail code into a single bit data stream;

[0045] If the current AC tail code encoding data stream conversion is completed, and the current sequence AC coefficient encoding has not yet ended, return to step SC5 to continue reading;

[0046] If the current AC coefficient tail code data stream conversion is completed and the current sequence AC coefficient code conversion is completed, jump back to step SC3 to read the next sequence DC code;

[0047] If the current AC coefficient tail code data stream conversion is completed and all AC coefficient codes of the current sequence are converted, and it is the last sequence of the current frame image, jump to step SC8;

[0048] SC8, the JPEG data stream generation module is in the zero-filling judgment state, stays for 1 clock cycle and judges whether the total number of bits generated by the data stream of this frame image is a positive integer multiple of 16; if yes, it goes to step SC10; if not, it goes to step SC9 to perform zero-filling operation;

[0049] SC9, the JPEG data stream generation module is in a zero-filling state, and fills 0 bit by bit at the end of the data stream so that the number of bits in the final data stream is a positive integer multiple of 16, and then proceeds to step SC10;

[0050] SC10, the JPEG data stream generation module is in the end state, generates a JPEG data stream generation completion flag to indicate that the byte data stream output stage is completed, and returns to step SC1.

[0051] In the FPGA-based universal JPEG grayscale image compression module described in the present invention, as a preferred embodiment, step SC2 stays for 10 clock cycles.

[0052] The present invention discloses a universal JPEG grayscale image compression module based on FPGA, as a preferred embodiment, the timing state of the output framing module includes: framing idle state, header information state, JPEG data stream state and tail state;

[0053] The control method of the output framing module comprises the following steps:

[0054] SD1, the default state of the output framing module is the framing idle state, and when the JPEG data stream is input, it enters step SD2;

[0055] SD2, the output framing module is in the header information state, the output framing module outputs the frame header information, and after the output is completed, it enters step SD3;

[0056] SD3, the output framing module is in the JPEG data stream state, the output framing module only outputs the JPEG data stream, and when the JPEG data stream generation completion mark is received, step SD4 is entered;

[0057] SD4, the output framing module is in the tail state, the output framing module splices and fills 0s byte by byte at the tail of the frame until the frame byte length corresponding to the compression ratio parameter is reached, and then returns to step SD1.

[0058] The FPGA-based universal JPEG grayscale image compression module described in the present invention is, as a preferred embodiment, in step SD2, the frame header information includes original image height information and original image width information, and the frame header information is 4 bytes in total.

[0059] The FPGA-based universal JPEG grayscale image compression module described in the present invention is preferably configured such that in step SD4:

[0060] Frame_length=ceil(H*W / 2 / Ratio);

[0061] Among them, Frame_length is the total frame length of the compressed data frame after framing, in words; ceil() is a rounding up function; H is the height of the grayscale image to be processed; W is the width of the grayscale image to be processed; Ratio is the image compression ratio parameter.

[0062] The present invention has the following advantages:

[0063] The present invention provides an efficient implementation scheme for JPEG standard image compression; by configuring the starting storage address of DDR3, the storage area occupied by image data in DDR3 is specified; by configuring the image width and image height parameters, JPEG compression processing can be performed on any grayscale image whose image height and image width are both positive multiples of 8 and which is smaller than the capacity of the DDR memory; by configuring the compression speed parameter, the speed of the image compression process can be adjusted; by configuring the image compression ratio parameter, the compressed image quality and the total data volume of the JPEG data stream can be accurately controlled. The present invention improves the transmission efficiency of remote sensing images and reduces the storage space occupied; and can be conveniently configured through parameterization and flexibly applied in different fields, working conditions and requirements, is easy to transplant, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is a generalized JPEG grayscale image compression module structure and operation flow chart based on FPGA;

[0065] Figure 2 A schematic diagram of a brightness quantization table A of a universal JPEG grayscale image compression module based on FPGA;

[0066] Figure 3 A schematic diagram of a brightness quantization table B of a generalized JPEG grayscale image compression module based on FPGA;

[0067] Figure 4 A schematic diagram of a brightness quantization table C of a universal JPEG grayscale image compression module based on FPGA;

[0068] Figure 5 It is a pipeline processing flow chart of the AC coefficient encoding module of a universal JPEG grayscale image compression module based on FPGA;

[0069] Figure 6 It is a state transition diagram of a JPEG data stream generation module state machine of a generalized JPEG grayscale image compression module based on FPGA;

[0070] Figure 7 The figure is a state transition diagram of a generalized JPEG grayscale image compression module output framing module state machine based on FPGA. DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0072] Example 1

[0073] A universal JPEG grayscale image compression module based on FPGA, which includes 11 sub-modules, such as Figure 1 As shown, they are a grayscale data cache module, a grayscale data reading module, a DDR3 memory controller, a one-dimensional DCT transformation module, a two-dimensional DCT transformation module, a quantization module, a zigzag scanning module, a DC coefficient encoding module, an AC coefficient encoding module, a JPEG data stream generation module, and an output framing module.

[0074] The overall processing flow is described as follows:

[0075] (1) Configure various parameters of the image to be processed in the next frame, including the starting storage address of DDR3, image width, image height, compression speed parameter, and image compression ratio parameter;

[0076] (2) The grayscale image data is input pixel by pixel in the order of "from top to bottom and from left to right" in the image, and is written into the FPGA external DDR3 memory through the grayscale data cache module. After the entire frame of grayscale image data is completely input, a write completion flag signal is generated;

[0077] (3) The grayscale data reading module receives the write completion flag and controls the grayscale data of each row in each 8*8 pixel block to be read out row by row in the order of "from top to bottom" by operating the DDR3 address, and the grayscale data between pixel blocks is output block by block in the order of "from top to bottom, from left to right". Note that the reading interval between pixel blocks is controlled by the compression speed parameter;

[0078] (4) The grayscale data of each row in each pixel block read out enters the one-dimensional DCT transformation module row by row, and the one-dimensional DCT transformation results are obtained row by row;

[0079] (5) The one-dimensional DCT transformation result of the pixel block is input into the two-dimensional DCT transformation module row by row to obtain the two-dimensional DCT transformation result of the pixel block;

[0080] (6) The quantization module quantizes the input two-dimensional DCT transform result. Three different brightness quantization tables are pre-stored in the FPGA. When quantization starts, one of them is selected according to the value of the image compression ratio parameter.

[0081] (7) The quantization result of the pixel block is input into the zigzag scanning module and converted into an output in the order of a zigzag sequence, where the first coefficient of the sequence is used as the DC coefficient and the rest are used as the AC coefficients;

[0082] (8) The DC coefficient is input into the DC coefficient encoding module to obtain a DC Huffman encoding result, and the AC coefficient is input into the AC coefficient encoding module to obtain an AC Huffman encoding result;

[0083] (9) The JPEG data stream generation module aggregates and integrates the input DC and AC Huffman coding results and outputs a JPEG data stream;

[0084] (10) The output framing module adds frame header information to the JPEG data stream and fills it with zeros to the data amount corresponding to the image compression ratio parameter, and finally outputs the compressed data frame result.

[0085] The configurable parameters include: the starting storage address of DDR3, the minimum value is 0, and the storage space after the starting address should be enough to accommodate the size of a whole frame of image. When a DDR needs to multiplex multiple functions, the storage area can be controlled according to the starting storage address;

[0086] The image width and height are both positive integer multiples of 8, for example, the image width and height are: 8*8, 32*8, or 64*128, etc.;

[0087] The compression speed parameter refers to the time period for reading ddr in the program. By changing the compression speed parameter, the duration of the compression process can be controlled. The compression speed parameter value should be greater than or equal to 119;

[0088] The image compression ratio parameter is the ratio of the original image size to the compressed output image size, and the value range is 1 to 15.

[0089] These parameters are latched once at the beginning of a frame of image input, that is, in the middle of a frame of image input, changes in configurable parameters will not be responded to.

[0090] The grayscale data cache module first converts the 8-bit unsigned pixel grayscale value into an 8-bit signed number, and then converts it into a 16-bit signed number by padding the high bits. In this way, the grayscale values ​​of every 8 adjacent pixels form a 128-bit width, which is just stored in one address space of DDR3.

[0091] The pipeline data processing method of the two-dimensional DCT transform module includes the following sub-steps:

[0092] (5.1) The one-dimensional DCT transform results of 1 to 8 rows input sequentially are cached in 8 row cache fifos in sequence;

[0093] (5.2) After the 8 rows of data are cached, the 8 row cache fifos are read synchronously. After 8 clocks, all the fifos are read empty, which means the transposition operation of "row input, column read" is completed;

[0094] (5.3) The transposed data read out is input into the multiplexed one-dimensional DCT transformation module to perform column-dimensional DCT transformation to obtain a column-dimensional DCT transformation result;

[0095] (5.4) Cache the column-dimensional DCT transform results of columns 1 to 8 in 8 column cache fifos in sequence;

[0096] (5.5) After the 8 columns of data are cached, the 8 column cache fifos are read synchronously. After 8 clocks, all fifos are read empty, which completes the re-transposition operation of "column input, row read", and finally outputs the two-dimensional DCT transformation result.

[0097] Quantization module such as Figure 2 , 3, 4, where the corresponding relationship between the image compression ratio parameter and the three pre-stored brightness quantization tables is: if the image compression ratio parameter is configured in the range of 1 to 5, the brightness quantization table A is selected, and the image information loss is relatively small when this table is used; if the image compression ratio parameter is configured in the range of 6 to 10, the brightness quantization table B is selected, and the image information loss is moderate when this table is used; if the image compression ratio parameter is configured in the range of 11 to 15, the brightness quantization table C is selected, and the image information loss is relatively large when this table is used.

[0098] The brightness quantization table C is easier to compress the image smaller than the brightness quantization table A. The quantization step of the brightness quantization table C is larger than the quantization step of the brightness quantization table B, and the quantization step of the brightness quantization table B is larger than the quantization step of the brightness quantization table A.

[0099] AC coefficient encoding module such as Figure 5 As shown, the encoding process adopts a pipeline design, including the following sub-steps:

[0100] (8.1) The stroke detection module performs zero stroke length detection on the input AC coefficient, and synchronously outputs the valid AC coefficient, zero stroke length, current sequence end flag and stroke detection output enable after t0 time;

[0101] (8.2) The effective AC coefficient is input into the AC coefficient size query module to query the tail codeword and the effective coding length of the tail codeword corresponding to the current AC coefficient. The process takes time t1. Synchronously, the zero run length, the current sequence tail flag and the run detection output enable are fixed with a delay of t1 respectively.

[0102] (8.3) The AC coefficient Huffman coding lookup table queries and outputs the final Huffman codeword and the effective coding length of the Huffman codeword based on the effective coding length of the tail codeword and the zero run length, which takes time t2. Synchronously, the tail codeword, the effective coding length of the tail codeword, the current sequence tail flag and the codeword output enable are output with a fixed delay of t2. The codeword output enable is obtained after the delay beat of the run detection output enable.

[0103] JPEG data stream generation module such as Figure 6 As shown, the state machine method is used to realize the timing control in the process of integrating DC and AC Huffman coding results. The state transfer is described as follows:

[0104] (9.1) Idle state: The default state. If the DC encoding cache fifo is not empty, it will immediately jump to the ready state.

[0105] (9.2) Ready state: After staying in this state for 10 clock cycles, it automatically jumps to the DC reading state.

[0106] (9.3) DC read state: stay for 1 clock cycle, read a set of DC encoding results from the DC encoding cache fifo, and then jump to the DC size encoding state.

[0107] (9.4) DC size encoding state: In this state, the read DC size code is converted into a single-bit data stream. There are two paths to jump to this state:

[0108] (9.4.1) When the DC size encoding data stream conversion is completed and the corresponding DC tail code is not all 0, it jumps to the DC tail code state;

[0109] (9.4.2) When the DC size encoding data stream conversion is completed, the corresponding DC tail code is all 0, then jump to the AC reading state.

[0110] (9.5) AC read state: stay for 1 clock cycle, read a set of AC encoding results from the AC encoding buffer fifo, and then jump to the AC Huffman encoding state.

[0111] (9.6) AC Huffman coding state: In this state, the read AC Huffman code is converted into a single-bit data stream. There are four paths to jump to this state:

[0112] (9.6.1) If the current AC coefficient Huffman coding data stream conversion has been completed and the tail code is not all 0, jump to the AC tail code state;

[0113] (9.6.2) If the current AC coefficient Huffman coding data stream conversion has been completed, and the tail code is all 0, and there are remaining AC coefficient codes in the current sequence that have not been processed, then jump back to the AC reading state;

[0114] (9.6.3) If the Huffman coding data stream conversion of the current AC coefficient has been completed, and the tail code is all 0, and all AC coefficient coding of the current sequence has been processed, then jump back to the DC reading state and wait for the coding result of the next sequence to arrive;

[0115] (9.6.4) The current AC coefficient Huffman coding data stream conversion has been completed, and the tail code is all 0. The coding of all AC coefficients in the current sequence has ended, and it is the last sequence of this frame image, then jump to the zero filling judgment state.

[0116] (9.7) AC tail code state: In this state, the read AC tail code is converted into a single-bit data stream. There are three paths to jump to this state:

[0117] (9.7.1) The current AC tail code encoding data stream conversion is completed, and the current sequence AC coefficient encoding has not yet ended, and it returns to the AC reading state to continue reading;

[0118] (9.7.2) After the current AC coefficient tail code data stream conversion is completed and the current sequence AC coefficient code conversion is completed, it jumps back to the DC reading state to read the DC code of the next sequence;

[0119] (9.7.3) When the current AC coefficient tail code data stream conversion is completed, and all AC coefficient codes in the current sequence are converted, and it is the last sequence of this frame image, then jump to the zero-filling judgment state.

[0120] (9.8) Zero-filling judgment state: This state stays for 1 clock cycle to determine whether the total number of bits generated by the data stream of this frame image is a positive integer multiple of 16, that is, whether it can be converted into a complete word data stream. If so, it jumps to the end state; if not, it jumps to the zero-filling state to perform the zero-filling operation.

[0121] (9.9) Zero-filling state: fill the end of the data stream with 0s bit by bit until the number of bits in the final data stream is a positive integer multiple of 16, that is, until it can be converted into a complete word data stream, and then jump to the end state.

[0122] (9.10) End state: Generates a JPEG signal data stream generation completion flag to indicate that the byte data stream output phase is completed, and then returns to the idle state.

[0123] Output framing module such as Figure 7 As shown, the timing control is performed in the form of a state machine, which is described as follows:

[0124] (10.1) Idle state: the default state, when the JPEG data stream is input, it will jump to the header information state immediately;

[0125] (10.2) Header information state: In this state, the original image height and width information are output as frame header information, a total of 4 bytes. After the output is completed, jump to the JPEG data stream state;

[0126] (10.3) JPEG data stream state: In this state, only the JPEG data stream is output until the JPEG data stream generation completion mark arrives, and then jumps to the tail state;

[0127] (10.4) Tail state: In this state, the tail of the frame is spliced ​​and padded with 0 byte by byte until the frame byte length corresponding to the compression ratio parameter is reached. Then it returns to the idle state.

[0128] Note: The frame byte length corresponding to the compression ratio parameter is calculated as follows:

[0129] Frame_length=ceil(H*W / 2 / Ratio)

[0130] Among them, Frame_length represents the total frame length of the compressed data frame after framing, in words; ceil() represents a rounding up function; H represents the image height; W represents the image width; and Ratio represents the image compression ratio parameter.

[0131] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A universal JPEG grayscale image compression module based on FPGA, characterized by: It includes a grayscale data buffer module, a grayscale data reading module, a one-dimensional DCT transformation module, a two-dimensional DCT transformation module, a quantization module, and a zigzag scanning module, which are electrically connected in sequence, a DC coefficient encoding module and an AC coefficient encoding module, which are electrically connected to the output end of the zigzag scanning module, and a JPEG data stream generation module and an output framing module, which are electrically connected to the output end of the DC coefficient encoding module and the output end of the AC coefficient encoding module in sequence; The grayscale data cache module writes the input grayscale image to be processed pixel by pixel in sequence into the FPGA memory and generates a write completion flag signal after the writing is completed. The grayscale data reading module reads the write completion flag signal and reads the grayscale data one by one from the FPGA memory according to the compression speed parameter by pixel block. The one-dimensional DCT transformation module performs a one-dimensional DCT transformation on each row of grayscale data in the pixel block to obtain a one-dimensional DCT transformation result. The two-dimensional DCT transformation module performs a two-dimensional DCT transformation on the one-dimensional DCT transformation result to obtain a two-dimensional DCT transformation result. The quantization module performs a quantization process on the two-dimensional DCT transformation result according to the brightness quantization table to obtain a quantization result of the pixel block. The zigzag scanning module converts the quantization result of the pixel block into a zigzag sequence, the sequence head of the zigzag sequence is a DC coefficient, and the sequence heads are AC coefficients, the DC coefficient encoding module encodes the DC coefficient to obtain a DC Huffman encoding result, the AC coefficient encoding module encodes the AC coefficient to obtain an AC Huffman encoding result, the JPEG data stream generation module integrates the DC Huffman encoding result and the AC Huffman encoding result to obtain a JPEG data stream, and the output framing module supplements the JPEG data stream with frame header information and fills zeros to the data amount corresponding to the image compression ratio parameter, and then outputs a compressed data frame result; The two-dimensional DCT transform module uses a pipeline data processing method, and the JPEG data stream generation module and the output frame assembly module both use a state machine method for timing control; Before compressing the grayscale image to be processed, processing parameters are set, and the processing parameters include the starting storage address of the FPGA memory, image width, image height, compression speed parameter and image compression ratio parameter.

2. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: The FPGA memory is a DDR3 memory external to the FPGA, the minimum value of the starting storage address of the DDR3 memory is 0, and the storage space after the starting storage address is sufficient to accommodate the size of a whole frame of image, and the storage area occupied by the image data in the DDR3 is specified by configuring the starting storage address of the DDR3; The image width and image height of the grayscale image to be processed are both positive integer multiples of 8; The grayscale data cache module controls the grayscale data of each row in each 8*8 pixel block to be read out row by row in a top-to-bottom order by operating the DDR3 memory address, and outputs the grayscale data between pixel blocks in a top-to-bottom and left-to-right order, and the reading interval between pixel blocks is controlled by the compression speed parameter; The grayscale data cache module first converts the 8-bit unsigned pixel grayscale value into an 8-bit signed number, and then converts it into a 16-bit signed number by padding the high bits so that every 8 adjacent pixel grayscale values ​​form a 128-bit width and are stored in an address space of the DDR3 memory; The compression speed parameter value is greater than or equal to 119; the image compression ratio parameter ranges from 1 to 15; The processing parameters cannot be modified during the compression process of the grayscale image to be processed.

3. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: The pipeline data processing method includes the following steps: SA1, the two-dimensional DCT transformation module sequentially caches 1 to 8 rows of one-dimensional DCT transformation results input in sequence in 8 row buffer fifos; SA2, synchronously read 8 row cache fifos, after 8 clocks, all row cache fifos are read empty, and the transposition operation of row input and column reading is completed to obtain the transposed data; SA3, read out the transposed data and input it into the one-dimensional DCT transformation module again to perform column-dimensional DCT transformation to obtain a column-dimensional DCT transformation result; SA4, sequentially cache the column-dimensional DCT transformation results of columns 1 to 8 in 8 column cache fifos; SA5. After the 8 columns of data are cached, the 8 column cache fifos are read synchronously. After 8 clocks, all column cache fifos are read empty, and the transposition operation of column input and row reading is completed again to obtain the two-dimensional DCT transformation result.

4. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: When the quantization module performs quantization processing, if the image compression ratio parameter is configured in the range of 1 to 5, the brightness quantization table A is selected; if the image compression ratio parameter is configured in the range of 6 to 10, the brightness quantization table B is selected; if the image compression ratio parameter is configured in the range of 11 to 15, the brightness quantization table C is selected; The quantization step of the brightness quantization table C is greater than the quantization step of the brightness quantization table B, and the quantization step of the brightness quantization table B is greater than the quantization step of the brightness quantization table A.

5. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: The AC coefficient encoding module includes an encoding pipeline, and the encoding pipeline includes a stroke detection module, an AC coefficient size query module and an AC coefficient Huffman encoding lookup table module which are electrically connected in sequence; The processing method of the encoding pipeline comprises the following steps: SB1, the stroke detection module performs zero stroke length detection on the input AC coefficient, and synchronously outputs the valid AC coefficient, zero stroke length, current sequence end flag, and stroke detection output enable after t0 time; SB2, the effective AC coefficient is input into the AC coefficient size query module, and the tail codeword and the effective coding length of the tail codeword corresponding to the current AC coefficient are queried. The process takes time t1. At the same time, the zero run length, the current sequence tail flag and the run detection output enable are respectively fixed with a delay of t1; SB3, the AC coefficient Huffman coding lookup table module queries and outputs the final Huffman codeword and the effective coding length of the Huffman codeword according to the effective coding length of the tail codeword and the zero run length, which takes time t2. At the same time, the tail codeword, the effective coding length of the tail codeword, the current sequence tail flag and the codeword output enable a fixed delay of t2 and output to obtain the AC Huffman coding result.

6. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: The timing states of the JPEG data stream generation module include: idle state, ready state, DC reading state, DC size encoding state, DC tail code state, AC reading state, AC Huffman encoding state, AC tail code state, zero padding judgment state, zero padding state and end state; The generation method of the JPEG data stream generation module comprises the following steps: SC1, the default state of the JPEG data stream generation module is the idle state, and when the DC encoding buffer fifo becomes non-empty, step SC2 is entered; SC2, the JPEG data stream generation module is in the ready state, and enters step SC3 after staying in the ready state for a specified period; SC3, the JPEG data stream generation module is in the DC reading state, stays in the DC reading state for 1 clock cycle, reads a set of DC encoding results from the DC encoding buffer fifo, and then enters step SC4; SC4, the JPEG data stream generation module is in the DC size encoding state, converting the read DC size code into a single-bit data stream; When the DC size coding data stream conversion is completed and the DC tail code is not all 0, it jumps to the DC tail code state, converts the DC tail code into a single bit data stream and enters step SC5; When the DC size coding data stream conversion is completed and the DC tail code is all 0, jump to step SC5; SC5, the JPEG data stream generation module is in the AC reading state, stays for one clock cycle, reads a set of AC encoding results from the AC encoding buffer fifo, and then enters step SC6; SC6, the JPEG data stream generation module is in the AC Huffman coding state, converting the read AC Huffman coding into a single-bit data stream; If the current AC coefficient Huffman coding data stream conversion has been completed and the tail code is not all 0, jump to step SC7; If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, and there are remaining AC coefficient codes in the current sequence that have not been processed, jump back to step SC5; If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, and all AC coefficient coding of the current sequence has been processed, then jump back to step SC3 and wait for the coding result of the next sequence to arrive; If the Huffman coding data stream conversion of the current AC coefficient has been completed and the tail code is all 0, the coding of all AC coefficients in the current sequence has been completed and it is the last sequence of the current frame image, then go to step SC8; SC7, the JPEG data stream generation module is in the AC tail code state, and converts the read AC tail code into a single-bit data stream; If the current AC tail code encoding data stream conversion is completed, and the current sequence AC coefficient encoding has not yet ended, return to step SC5 to continue reading; If the current AC coefficient tail code data stream conversion is completed and the current sequence AC coefficient code conversion is completed, jump back to step SC3 to read the next sequence DC code; If the current AC coefficient tail code data stream conversion is completed and all AC coefficient codes of the current sequence are converted, and it is the last sequence of the current frame image, jump to step SC8; SC8, the JPEG data stream generation module is in the zero-filling judgment state, stays for 1 clock cycle and judges whether the total number of bits generated by the data stream of the current frame image is a positive integer multiple of 16; if yes, proceeds to step SC10; if not, proceeds to step SC9 to perform zero-filling operation; SC9, the JPEG data stream generation module is in a zero-filling state, and fills 0 bit by bit at the end of the data stream so that the number of bits of the final data stream is a positive integer multiple of 16, and then proceeds to step SC10; SC10: The JPEG data stream generation module is in the end state, generates a JPEG data stream generation completion flag to indicate that the byte data stream output stage is completed, and returns to step SC1.

7. The universal JPEG grayscale image compression module based on FPGA according to claim 6, characterized in that: Step SC2 stays for 10 clock cycles.

8. The universal JPEG grayscale image compression module based on FPGA according to claim 1, characterized in that: The timing states of the output framing module include: framing idle state, header information state, JPEG data stream state and tail state; The control method of the output framing module comprises the following steps: SD1, the default state of the output framing module is the framing idle state, and when the JPEG data stream is input, the process enters step SD2; SD2, the output framing module is in the header information state, the output framing module outputs the frame header information, and after the output is completed, it enters step SD3; SD3, the output framing module is in the JPEG data stream state, the output framing module only outputs the JPEG data stream, and when the JPEG data stream generation completion mark is received, step SD4 is entered; SD4, the output framing module is in the tail state, the output framing module splices and fills 0s byte by byte at the tail of the frame until the frame byte length corresponding to the compression ratio parameter is reached, and returns to step SD1.

9. The universal JPEG grayscale image compression module based on FPGA according to claim 8, characterized in that: In step SD2, the frame header information includes original image height information and original image width information, and the frame header information is 4 bytes in total.

10. The universal JPEG grayscale image compression module based on FPGA according to claim 8, characterized in that: In step SD4: Frame_length=ceil(H*W / 2 / Ratio); Among them, Frame_length is the total frame length of the compressed data frame after framing, in words; ceil() is a rounding up function; H is the height of the grayscale image to be processed; W is the width of the grayscale image to be processed; Ratio is the image compression ratio parameter.

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