Lateral enhanced gallium oxide field effect transistor with NiO extended gate field plate

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a transverse enhancement type gallium oxide field effect transistor with a NiO extended gate field plate. When the device is in forward conduction, an electron accumulation layer is formed in the drift region below the extended gate field plate, so that the on-resistance of the device is reduced, and the defect that the specific on-resistance of an enhanced MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is large is overcome; in a blocking state, the extending gate structure and the N-type gallium oxide drift region form a super-junction-like structure, electric field distribution is modulated, depletion of the drift region is assisted, the breakdown voltage of the device is improved, the doping concentration of an epitaxial layer of the device is further improved, and the on-resistance is reduced. The invention has the beneficial effects that the device is an enhanced device and has the dual advantages of low on-resistance and high breakdown voltage, in addition, the applied nickel oxide deposition process is simple, an additional etching process is not introduced, and the manufacturing cost is reduced. And etching damage in the drift region of the device and advanced breakdown caused by an interface problem between gallium oxide and nickel oxide are avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors and relates to a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate. Background Art

[0002] Gallium oxide (Ga2O3)-based power devices have gradually become the new favorite in the field of power devices due to their ultra-wide bandgap (4.9eV), ultra-high critical breakdown field strength (8MV / cm), and low-cost, large-scale and high-quality single crystal substrate growth advantages. β-Ga2O3 is the only crystal structure among many Ga2O3 crystal phases that can be grown by melt method. Compared with traditional silicon-based and third-generation semiconductor materials such as gallium nitride and silicon carbide, β-Ga2O3-based power devices have the triple advantages of high breakdown voltage, low on-resistance and low cost, and have great application prospects in the fields of high voltage, high power, high efficiency and energy saving. However, since β-Ga2O3 has not yet formed effective P-type doping, most of the current β-Ga2O3 power MOSFETs are depletion-type devices, which will increase the off-state power consumption of the device. However, the enhanced β-Ga2O3 power MOSFET prepared based on groove gate, P-NiO gate and other methods will weaken the current capability of the device and increase the device's specific on-resistance. In addition, the existing groove gate gallium oxide MOSFET and superjunction gallium oxide MOSFET inevitably undergo etching and trenching in the drift region of the device, which not only occupies the drift region space and increases the on-resistance, but also causes complex interface problems. Summary of the invention

[0003] In view of the above problems, the present invention proposes a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate.

[0004] The technical solution of the present invention is:

[0005] A lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate, wherein a gallium oxide substrate 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 are sequentially stacked from bottom to top along the vertical direction of the device;

[0006] The invention is characterized in that a drain heavily doped region 4 and a source heavily doped region 5 are respectively provided on both sides of the gallium oxide epitaxial layer 3; the lower surface of the drain heavily doped region 4 contacts the upper surface of the gallium oxide epitaxial layer 3, and the end of the upper surface of the drain heavily doped region 4 away from the source heavily doped region 5 has a drain metal 6; the lower surface of the source heavily doped region 5 contacts the upper surface of the gallium oxide epitaxial layer 3, and the end of the upper surface of the source heavily doped region 5 away from the drain heavily doped region 4 has a source metal 7; a gate oxide layer 8 is provided on the upper surface of the drain heavily doped region 4, the upper surface of the gallium oxide epitaxial layer 3 and the upper surface of the source heavily doped region 5 between the drain metal 6 and the source metal 7; a gate structure is provided on the side of the upper surface of the gate oxide layer 8 close to the source metal 7, and the gate structure is composed of a nickel oxide strip and a gate metal 10, the nickel oxide strip is respectively in contact with the gate oxide layer 8 and the gate metal 10, and the nickel oxide strip extends along the upper surface of the gate oxide layer 8 to the side close to the drain metal 6 to form an extended gate field plate.

[0007] Furthermore, the gate structure is a planar gate structure, and the nickel oxide strip includes a first P-type nickel oxide strip 91 and a second P-type nickel oxide strip 92, the first P-type nickel oxide strip 91 is located on the upper surface of the gate oxide layer 8, the second P-type nickel oxide strip 92 is located on the upper surface of the first P-type nickel oxide strip 91, and the end of the second P-type nickel oxide strip 92 close to the source metal 7 is flush with the end of the first P-type nickel oxide strip 91 close to the source metal 7 in the vertical direction; the gate metal 10 is located on the upper surface of the second P-type nickel oxide strip 92; wherein the lateral width of the second P-type nickel oxide strip 92 is equal to the lateral width of the gate metal 10, and the two ends of the second P-type nickel oxide strip 92 are completely aligned with the two ends of the gate metal 10 in the vertical direction; the lateral width of the first P-type nickel oxide strip 91 is less than the lateral width of the gallium oxide epitaxial layer 3, and there is a spacing between the two ends of the first P-type nickel oxide strip 91 and the two ends of the gallium oxide epitaxial layer 3.

[0008] Furthermore, the gate structure is a trench gate structure, a groove is formed on the upper layer of the gallium oxide epitaxial layer 3, the gate oxide layer 8 is filled in the bottom and inner wall of the groove, the gate metal 10 is filled in the groove and extends out of the groove, and the nickel oxide strip is a first P-type nickel oxide strip 91, and one end of the first P-type nickel oxide strip 91 is in contact with the side wall of the gate metal 10.

[0009] Furthermore, the gate structure is a trench gate structure, a groove is formed on the upper layer of the gallium oxide epitaxial layer 3, the gate oxide layer 8 is filled in the bottom and inner wall of the groove, the nickel oxide strip includes a first P-type nickel oxide strip 91 and a second P-type nickel oxide strip 92, the second P-type nickel oxide strip 92 is filled in the groove and the upper surface of the second P-type nickel oxide strip 92 is flush with the upper surface of the gate oxide layer 8; the first P-type nickel oxide strip 91 covers the second P-type nickel oxide strip 92, and the end of the first P-type nickel oxide strip 91 close to the drain metal 6 is flush with the end face of the second P-type nickel oxide strip 92 in the vertical direction; the gate metal 10 is located on the upper surface of the second P-type nickel oxide strip 92 and the gate metal 10 is located directly above the second P-type nickel oxide strip 92, and the lateral width of the gate metal 10 is the same as the lateral width of the second P-type nickel oxide strip 92.

[0010] The manufacturing method of the device of the present invention comprises the following steps:

[0011] Step 1: epitaxially forming a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3 on the upper surface of a gallium oxide substrate 1 in sequence;

[0012] Step 2: forming a source heavily doped region 5 and a drain heavily doped region 4 at both ends of the gallium oxide epitaxial layer 3 by high energy ion implantation;

[0013] Step 3: Depositing drain metal 6 and source metal 7 on the drain heavily doped region 4 and the source heavily doped region 5 respectively by lift-off technology;

[0014] Step 4: forming a gate oxide layer 8 by an atomic layer deposition process;

[0015] Step 5: Generate a gate structure on the gate oxide layer 8 .

[0016] When the gate structure is a planar gate structure, the manufacturing method is:

[0017] A sputtering process forms a first P-type nickel oxide strip 91 on the upper surface of the gate oxide layer 8, and then a second P-type nickel oxide strip 92 is formed on the first P-type nickel oxide strip 91 by a sputtering process, wherein the oxygen flux when forming the second P-type nickel oxide strip 92 by sputtering is greater than the oxygen flux when forming the first P-type nickel oxide strip 91, so as to ensure the formation of the first P-type nickel oxide strip 91 with a low hole concentration and the second P-type nickel oxide strip 92 with a high hole concentration;

[0018] The gate metal 10 is deposited on the upper surface of the second P-type nickel oxide strip 92 .

[0019] When the gate structure is a trench gate structure, the manufacturing methods correspond to the following two methods:

[0020] 1) forming a groove by ICP etching, repairing the etching interface damage by wet method, and then forming a gate oxide layer 8 by atomic layer deposition process;

[0021] A first P-type nickel oxide strip 91 is formed on the gate oxide layer by a sputtering process;

[0022] A gate metal 10 is deposited on the upper surface of the gate oxide layer 8 above the groove and is in contact with the first P-type nickel oxide strip 91 .

[0023] 2) forming a groove by ICP etching, repairing the etching interface damage by wet method, and then forming a gate oxide layer 8 by atomic layer deposition ALD process;

[0024] A second P-type nickel oxide 92 is deposited and filled in the groove of the gate oxide layer 8 until it is flush with the etching table, and then a first P-type nickel oxide strip 91 is formed on the upper surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by a sputtering process;

[0025] The gate metal 10 is deposited on the upper surface of the first P-type nickel oxide strip 91 and is aligned with the edge of the groove gate.

[0026] The beneficial effects of the present invention are as follows: the device of the present invention is an enhancement type device, when forward conducting, an electron accumulation layer is formed under the extended gate, reducing the on-resistance of the device, when in the blocking state, the extended gate structure and the N-type gallium oxide drift region form a quasi-superjunction structure, modulate the electric field distribution, assist in depleting the drift region, increase the breakdown voltage of the device, further increase the doping concentration of the drift region, and reduce the on-resistance. The nickel oxide deposition process used in the present invention is simple, does not introduce an additional etching process, and avoids the etching damage in the drift region of the device and the premature breakdown caused by the interface problem between gallium oxide and nickel oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the structure of the device described in Example 1 of the present invention;

[0028] Figure 2 is a schematic structural diagram of the device described in Example 2 of the present invention;

[0029] Figure 3 is a schematic diagram of the structure of the device described in Example 3 of the present invention;

[0030] Figure 4 is a schematic diagram of the process flow of the device described in Example 1 of the present invention; DETAILED DESCRIPTION

[0031] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0032] Embodiment 1:

[0033] like Figure 1 As shown, a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate comprises:

[0034] Along the vertical direction of the device, from bottom to top, it includes a gallium oxide substrate 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3;

[0035] The invention is characterized in that a drain heavily doped region 4 is provided on the right side of the gallium oxide epitaxial layer 3, and a source heavily doped region 5 is provided on the left side of the gallium oxide epitaxial layer 3; a drain metal 6 is provided on the upper surface of the drain heavily doped region 4, and a source metal 7 is provided on the upper surface of the source heavily doped region 5; a gate structure is formed above the gallium oxide epitaxial layer 3 and between the drain metal 6 and the source metal 7, including a gate oxide layer 8, a first P-type nickel oxide strip 91, a second P-type nickel oxide strip 92 and a gate metal 10, wherein the gate oxide layer 8 covers the upper surface of the gallium oxide epitaxial layer 3, and the upper surface of the gate oxide layer 8 is covered with a first P-type nickel oxide strip 91, the first P-type nickel oxide strip 91 extends from the side away from the drain to the side close to the drain but does not contact the drain metal 6, forming an extended gate field plate, the second P-type nickel oxide strip 92 covers the upper surface of the first P-type nickel oxide strip 91 away from the drain side, the left end of the second P-type nickel oxide strip 92 is aligned with the first P-type nickel oxide strip 91, the right side of the second P-type nickel oxide strip 92 does not extend to the side close to the drain, and the second P-type nickel oxide strip 92 is covered with a gate metal 10.

[0036] This example works like this:

[0037] The present invention proposes a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate, which uses a high-concentration second P-type nickel oxide strip 92 to deplete the carrier concentration under the device gate to form an enhancement type device; when forward conducting, a positive voltage is applied to the gate metal 10 and the drain metal 6, and the voltage applied to the gate metal 10 is greater than the voltage applied to the drain metal 6, the source metal 7 is grounded, and an electron accumulation layer is formed in the drift region under the extended gate field plate, thereby reducing the device on-resistance, thereby compensating for the deficiency of the enhancement type MOSFET having a larger on-resistance; when in a blocking state, the gate metal 10 and the source metal 7 are grounded, a high voltage is applied to the drain metal 6, and the extended gate structure and the N-type gallium oxide drift region form a quasi-superjunction structure, modulate the electric field distribution, assist in depleting the drift region, increase the device breakdown voltage, further increase the doping concentration of the device epitaxial layer, and reduce the on-resistance.

[0038] like Figure 4 (a)-(f) are schematic diagrams of the process flow of Example 1 of the present invention, which specifically include the following steps:

[0039] Step 1: epitaxially forming a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3 on a gallium oxide substrate 1 in sequence;

[0040] Step 2: forming a source heavily doped region 5 and a drain heavily doped region 4 by high energy ion implantation;

[0041] Step 3: Depositing drain metal 6 and source metal 7 on the drain heavily doped region 4 and the source heavily doped region 5 respectively by lift-off technology;

[0042] Step 4: forming a gate oxide layer 8 by an atomic layer deposition (ALD) process;

[0043] Step 5: forming a first P-type nickel oxide strip 91 on the gate oxide layer by a sputtering process, and then forming a second P-type nickel oxide strip 92 on the first P-type nickel oxide strip 91 by a sputtering process, wherein the oxygen flux when forming the second P-type nickel oxide strip 92 by sputtering should be greater than the oxygen flux when forming the first P-type nickel oxide strip 91, so as to ensure the formation of the first P-type nickel oxide strip 91 with a low hole concentration and the second P-type nickel oxide strip 92 with a high hole concentration;

[0044] Step 6: Deposit gate metal 10 on the upper surface of the second P-type nickel oxide strip 92 .

[0045] Embodiment 2:

[0046] like Figure 2 , which is a schematic diagram of the structure of a lateral enhancement type gallium oxide field effect transistor with a recessed gate and a NiO extended gate field plate according to Example 2. The difference between this example and Example 1 is that the device enhancement type is realized by a recessed gate structure instead of a high-concentration second P-type nickel oxide strip 92 in this example. The working principle is basically the same as that of Example 1.

[0047] The process steps of this example are different from those of Example 1 in that, in step 4, a recessed gate structure is first formed by ICP etching, and the etching interface damage is repaired by wet method, and then a gate oxide layer 8 is formed by atomic layer deposition ALD process; in step 5, a second P-type nickel oxide 92 is first deposited and filled in the recess of the gate oxide layer 8 until it is flush with the etching table, and then a first P-type nickel oxide strip 91 is formed on the upper surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by sputtering process; in step 6, a gate metal 10 is deposited on the upper surface of the first P-type nickel oxide strip 91 and aligned with the edge of the recessed gate.

[0048] Embodiment 3:

[0049] like Figure 3 As shown, it is a schematic diagram of the structure of a lateral enhancement type gallium oxide field effect transistor with a recessed gate and a NiO extended gate field plate according to Example 3. The structure of this example is different from that of Example 1 in that this example has a recessed gate structure, and the recessed gate is filled with a high-concentration second P-type nickel oxide strip 92. The two work together to further improve the device threshold. Its working principle is basically the same as that of Example 1.

[0050] The process steps of this example differ from those of Example 1 in that, in step 4, a recessed gate structure is first formed by ICP etching, and the etching interface damage is repaired by wet method, and then a gate oxide layer 8 is formed by atomic layer deposition ALD process; in step 5, a second P-type nickel oxide 92 is first deposited and filled in the recess of the gate oxide layer 8 until it is flush with the etching table, and then a first P-type nickel oxide strip 91 is formed on the upper surface of the gate oxide layer 8 and the second P-type nickel oxide 92 by sputtering process; in step 6, a gate metal 10 is deposited on the upper surface of the first P-type nickel oxide strip 91 and aligned with the edge of the recessed gate.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate, wherein a gallium oxide substrate (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3) are stacked in sequence from bottom to top along the vertical direction of the device; It is characterized in that A drain heavily doped region (4) and a source heavily doped region (5) are respectively provided on both sides of the gallium oxide epitaxial layer (3); the lower surface of the drain heavily doped region (4) contacts the upper surface of the gallium oxide epitaxial layer (3), and an end of the upper surface of the drain heavily doped region (4) away from the source heavily doped region (5) has a drain metal (6); the lower surface of the source heavily doped region (5) contacts the upper surface of the gallium oxide epitaxial layer (3), and an end of the upper surface of the source heavily doped region (5) away from the drain heavily doped region (4) has a source metal (7); The upper surface of the drain heavily doped region (4) between the metal (6) and the source metal (7), the upper surface of the gallium oxide epitaxial layer (3) and the upper surface of the source heavily doped region (5) are provided with a gate oxide layer (8); a gate structure is provided on the upper surface of the gate oxide layer (8) close to the source metal (7), the gate structure being composed of a nickel oxide strip and a gate metal (10), the nickel oxide strip being in contact with the gate oxide layer (8) and the gate metal (10) respectively, and the nickel oxide strip extending along the upper surface of the gate oxide layer (8) towards the side close to the drain metal (6) to form an extended gate field plate.

2. The lateral enhancement mode gallium oxide field effect transistor with NiO extended gate field plate according to claim 1, characterized in that: The gate structure is a planar gate structure, the nickel oxide strip comprises a first P-type nickel oxide strip (91) and a second P-type nickel oxide strip (92), the first P-type nickel oxide strip (91) is located on the upper surface of the gate oxide layer (8), the second P-type nickel oxide strip (92) is located on the upper surface of the first P-type nickel oxide strip (91), and an end of the second P-type nickel oxide strip (92) close to the source metal (7) is flush with an end of the first P-type nickel oxide strip (91) close to the source metal (7) in a vertical direction; the gate metal (1 0) is located on the upper surface of the second P-type nickel oxide strip (92); wherein the lateral width of the second P-type nickel oxide strip (92) is equal to the lateral width of the gate metal (10), and the two ends of the second P-type nickel oxide strip (92) are completely aligned with the two ends of the gate metal (10) in the vertical direction; the lateral width of the first P-type nickel oxide strip (91) is smaller than the lateral width of the gallium oxide epitaxial layer (3), and there is a spacing between the two ends of the first P-type nickel oxide strip (91) and the two ends of the gallium oxide epitaxial layer (3).

3. The lateral enhancement mode gallium oxide field effect transistor with NiO extended gate field plate according to claim 1, characterized in that: The gate structure is a groove gate structure, a groove is formed on the upper layer of the gallium oxide epitaxial layer (3), a gate oxide layer (8) is filled in the bottom and inner wall of the groove, a gate metal (10) is filled in the groove and extends out of the groove, and the nickel oxide strip is a first P-type nickel oxide strip (91), and one end of the first P-type nickel oxide strip (91) is in contact with the side wall of the gate metal (10).

4. The lateral enhancement mode gallium oxide field effect transistor with NiO extended gate field plate according to claim 1, characterized in that: The gate structure is a trench gate structure, wherein a groove is formed on the upper layer of the gallium oxide epitaxial layer (3), the gate oxide layer (8) is filled at the bottom and inner wall of the groove, the nickel oxide strip comprises a first P-type nickel oxide strip (91) and a second P-type nickel oxide strip (92), the second P-type nickel oxide strip (92) is filled in the groove and the upper surface of the second P-type nickel oxide strip (92) is flush with the upper surface of the gate oxide layer (8); the first P-type nickel oxide strip (91) covers the second P-type nickel oxide strip (92), and the end of the first P-type nickel oxide strip (91) close to the drain metal (6) is flush with the end surface of the second P-type nickel oxide strip (92) in the vertical direction; the gate metal (10) is located on the upper surface of the second P-type nickel oxide strip (92) and the gate metal (10) is located directly above the second P-type nickel oxide strip (92), and the lateral width of the gate metal (10) is the same as the lateral width of the second P-type nickel oxide strip (92).

5. A method for manufacturing a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate as claimed in claim 1, characterized in that: The steps include: Step 1: epitaxially forming a gallium oxide buffer layer (2) and a gallium oxide epitaxial layer (3) on the upper surface of a gallium oxide substrate (1); Step 2: forming a source heavily doped region (5) and a drain heavily doped region (4) at both ends of the gallium oxide epitaxial layer (3) by high energy ion implantation; Step 3: Depositing drain metal (6) and source metal (7) on the drain heavily doped region (4) and the source heavily doped region (5) respectively by lift-off technology; Step 4: forming a gate oxide layer (8) by an atomic layer deposition process; Step 5: Generate a gate structure on the gate oxide layer (8).

6. The method for manufacturing a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate according to claim 5, characterized in that: The gate structure is a planar gate structure, and the manufacturing method is: A first P-type nickel oxide strip (91) is formed on the upper surface of the gate oxide layer (8) by a sputtering process, and then a second P-type nickel oxide strip (92) is formed on the first P-type nickel oxide strip (91) by a sputtering process, wherein the oxygen flux when forming the second P-type nickel oxide strip (92) by sputtering is greater than the oxygen flux when forming the first P-type nickel oxide strip (91), so as to ensure the formation of the first P-type nickel oxide strip (91) with a low hole concentration and the second P-type nickel oxide strip (92) with a high hole concentration; A gate metal (10) is deposited on the upper surface of the second P-type nickel oxide strip (92).

7. The method for manufacturing a lateral enhancement type gallium oxide field effect transistor with a NiO extended gate field plate according to claim 5, characterized in that: The gate structure is a trench gate structure, and the manufacturing method is: Forming a groove by ICP etching, repairing etching interface damage by wet method, and then forming a gate oxide layer (8) by atomic layer deposition process; Forming a first P-type nickel oxide strip (91) on the gate oxide layer by a sputtering process; A gate metal (10) is deposited on the upper surface of the gate oxide layer (8) above the groove and is in contact with the first P-type nickel oxide strip (91).

8. The method for manufacturing a lateral enhancement mode gallium oxide field effect transistor with a NiO extended gate field plate according to claim 5, characterized in that: The gate structure is a trench gate structure, and the manufacturing method is: A groove is formed by ICP etching, and the etching interface damage is repaired by wet method, and then a gate oxide layer is formed by atomic layer deposition (ALD) process (8); Depositing and filling a second P-type nickel oxide (92) in the groove of the gate oxide layer (8) until it is flush with the etching table, and then forming a first P-type nickel oxide strip (91) on the gate oxide layer (8) and the upper surface of the second P-type nickel oxide (92) by a sputtering process; A gate metal (10) is deposited on the upper surface of the first P-type nickel oxide strip (91) and aligned with the edge of the groove gate.

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