Method for manufacturing semiconductor element

Abstract

The invention relates to a manufacturing method of a semiconductor element. According to one embodiment, a method for manufacturing a semiconductor element may include a gap filling step of forming a gap-filling oxide film by embedding a gap-filling oxide in a trench formed on a substrate. In one embodiment, the gap filling process may include a high pressure oxidation (HPO) process, and the gap filling process may include a high pressure oxidation (HPO) process. According to the embodiment, a semiconductor element with improved electrical characteristics can be manufactured compared with the prior art.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element. Background Art

[0002] When manufacturing semiconductor components, component isolation technology is used to electrically isolate independent components such as transistors or capacitors from each other. Recently, in the field of high-integration memory component manufacturing, shallow trench isolation (STI) technology is applied to form a component isolation area by forming a trench on a substrate and burying a gap-fill oxide film in the trench.

[0003] Figure 1 FIG. 1 is a cross-sectional view showing a device isolation region of a semiconductor device according to the prior art.

[0004] As shown in the figure, a semiconductor element 1 according to the prior art includes a substrate 11 and an element isolation region formed on the substrate 11. According to the prior art, in the process of forming the element isolation region, a liner nitride film 13 is formed inside the trench 12, and a liner oxide film 14 is formed on the liner nitride film 13. After the liner oxide film 14 is formed, the inside of the trench 12 is gap-filled with an oxide to form a gap-fill oxide film 15, and planarization is performed by a chemical mechanical polishing (CMP) process to complete the element isolation region.

[0005] When the width of the groove to be formed in the element isolation area is less than 30nm, due to the necessity of high aspect ratio and low temperature process, the deposition of plasma and thermochemical methods will have gap filling restrictions, so it is necessary to develop a gap filling process using a material with flow characteristics. A representative method of using flow characteristics is a coating method using spin-on-glass (SOG). However, in the case of the coating method using SOG, it is difficult to ensure the subsequent thermal process conditions for the densification and stabilization of the gap filling oxide film, and the electrical characteristics of the semiconductor element may be degraded due to the gaps (voids) V1 and V2 in the gap filling oxide film and the cracking of the gap filling oxide film.

[0006] Due to the above problems, a gap filling oxide film can be formed by chemical vapor deposition (CVD) instead of coating. However, according to the CVD method, the gap filling oxide film may be cracked and the electrical characteristics of the semiconductor element may be degraded due to the degradation of the adhesion of the gap filling oxide and changes caused by stress during the subsequent heat treatment. Summary of the invention

[0007] Technical issues

[0008] The purpose of this specification is to provide a method for manufacturing a semiconductor element, which can reduce the gaps generated in the gap-filling oxide film and reduce the cracking phenomenon of the gap-filling oxide film.

[0009] An object of the present specification is to provide a method for manufacturing a semiconductor element having improved electrical characteristics than those currently available.

[0010] The purpose of this specification is not limited to the above purpose, and other purposes and advantages of this specification that are not mentioned can be more clearly understood through the embodiments of this specification described below. In addition, the purposes and advantages of this specification can be achieved through the structural elements described in the claims and their combinations.

[0011] Technical Solution

[0012] According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include a gap-filling process, burying a gap-filling oxide into a trench formed on a substrate to form a gap-filling oxide film.

[0013] In one embodiment, the gap filling process may include a high pressure oxidation (HPO) process.

[0014] In one embodiment, the HPO process may be performed in a treatment device supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

[0015] In one embodiment, when the HPO process is performed, the internal pressure of the processing device may be maintained at 2 to 50 atmospheres.

[0016] In one embodiment, when performing the HPO process, the internal temperature of the processing device may be maintained at 200° C. to 1000° C.

[0017] In one embodiment, the gap-fill oxide film may be formed by performing the HPO process after performing a flowable chemical vapor deposition (FCVD) process using the gap-fill oxide.

[0018] According to another embodiment, a method for manufacturing a semiconductor element may include the following steps: etching a substrate to form a groove; forming a liner layer on the inner surface of the groove; forming a gap-filling oxide film on the liner layer for gap-filling the inside of the groove; and planarizing the gap-filling oxide film.

[0019] In another embodiment, the gap-filling oxide film may be formed by a gap-filling process including a high pressure oxidation (HPO) process.

[0020] In another embodiment, the HPO process may be performed in a treatment device supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

[0021] In another embodiment, when the HPO process is performed, the internal pressure of the processing device may be maintained at 2 to 50 atmospheres.

[0022] In another embodiment, when the HPO process is performed, the internal temperature of the processing device may be maintained at 200° C. to 1000° C.

[0023] In another embodiment, the gap-filling oxide film may be formed by performing the HPO process after performing a flowable chemical vapor deposition (FCVD) process.

[0024] In another embodiment, the liner layer may have a single-layer or multi-layer structure composed of at least one of a nitride film, an oxide film, and polysilicon.

[0025] Effects of the Invention

[0026] According to the embodiment, the gaps generated in the gap-filling oxide film can be reduced and the density of the gap-filling oxide film can be increased in the process of generating the element isolation region of the semiconductor element. In addition, the cracking phenomenon of the gap-filling oxide film can be reduced in the process of generating the element isolation region of the semiconductor element. Therefore, a semiconductor element with improved electrical characteristics than before can be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 1 is a cross-sectional view showing a device isolation region of a semiconductor device according to the prior art.

[0028] Figures 2 to 7 A process of forming an element isolation region of a semiconductor element according to an embodiment is shown.

[0029] Figure 8 is a cross-sectional view of a capacitor element including a gap-filling oxide film.

[0030] Fig. 9 Graphs showing leakage values ​​measured when voltage is applied to capacitor elements including a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment, respectively.

[0031] Fig.10 Graphs showing charge retention times measured when voltage is applied to capacitor elements including a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment, respectively.

[0032] Fig.11 FIG. 1 is a graph showing the etching rates of a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment. DETAILED DESCRIPTION

[0033] The above-mentioned objects, features and advantages will be described in detail with reference to the accompanying drawings, so that a person of ordinary skill in the technical field to which this specification belongs can easily implement the embodiments of this specification. When describing this specification, when it is determined that the specific description of the known technology related to this specification does not necessarily make the subject matter of the present invention unclear, its detailed description will be omitted. Below, with reference to the accompanying drawings, the preferred embodiments of this specification will be described in detail. The same figure numbers in the drawings refer to the same or similar structural elements.

[0034] The embodiments of the present specification may be applied without limitation to any method for manufacturing a semiconductor device including a gap-filling process for a trench formed on a substrate and forming a gap-filling oxide film through the gap-filling process.

[0035] The features of the present invention will be described below with reference to the accompanying drawings, taking shallow trench isolation (STI) technology as an embodiment, but the present invention is not limited thereto, which is obvious to those skilled in the art.

[0036] Figures 2 to 7 A process of forming an element isolation region of a semiconductor element according to an embodiment is shown.

[0037] First, if Figure 2 As shown, a first pad oxide film 22, a pad nitride film 23 and a second pad oxide film 24 are sequentially deposited on the semiconductor substrate 21. In another embodiment, the second pad oxide film 24 may not be deposited.

[0038] The semiconductor substrate 21 may be made of at least one of Si and SiGe. In one embodiment, the semiconductor substrate 21 may be a single layer made of Si or a single layer made of SiGe. In another embodiment, the semiconductor substrate 21 may have a multilayer structure in which a first layer made of Si and a second layer made of SiGe are alternately stacked.

[0039] Next, the first pad oxide film 22 , the pad nitride film 23 , and a portion of the second pad oxide film 24 are etched by a patterning process and an etching process using an element isolation mask, thereby forming a trench 200 to be an element isolation region of the semiconductor substrate 21 .

[0040] Next, a liner layer may be formed on the semiconductor element 2. For example, Figure 3 and Figure 4 As shown, the pad layers 25 and 26 composed of two layers can be formed by first depositing a pad nitride film 25 on the semiconductor element 2 and then oxidizing the pad nitride film 25 to form a pad oxide film 26 .

[0041] The pad nitride film 25 is used to compensate for the compressive stress (Compressive Stress) generated by the gap filling oxide buried in the trench 200. That is, the compressive stress applied to the semiconductor substrate 21 due to the gap filling oxide is offset by the tensile stress (Tensile Stress) of the pad nitride film 25, thereby preventing the electrical characteristics of the semiconductor element 2 from being degraded due to the element isolation region.

[0042] In particular, the pad nitride film 25 can prevent defects generated in the startup region of the semiconductor element 2 from diffusing into the element isolation region, thereby improving the refresh characteristics of the cell region. A silicon nitride film (Si3N4) can be used as the pad nitride film 25. The pad nitride film 25 can be formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition), but is not limited thereto.

[0043] Although not shown, a wall oxide film may be formed on the surface of the trench 200 by oxidizing the surface of the trench 200 before forming the liner nitride film 25. The wall oxide film is used to repair defects such as crystal defects and plasma damage that may be generated during the formation of the trench 200. When the wall oxide film is formed, the liner nitride film 25 may be formed on the wall oxide film.

[0044] The role of the liner oxide film 26 is to prevent the liner nitride film 25 from being damaged due to the formation of the gap-filling oxide film 27 when the gap-filling oxide is buried in the trench 200 to form the gap-filling oxide film 27 .

[0045] Figure 3 and Figure 4 An embodiment is shown in which the pad layer (pad nitride films 25, 26) has a multilayer structure, which includes: a pad nitride film 25, and a pad oxide film 26 stacked on the pad nitride film 25. However, in another embodiment, the pad layer may also be composed of a pad oxide film and a pad nitride film stacked on the pad oxide film. In another embodiment, the pad layer may also be composed of a pad oxide film and a polysilicon layer stacked on the pad oxide film.

[0046] In another embodiment, the liner layer may have a single-layer structure. For example, the liner layer may include only a polysilicon layer.

[0047] Next, if Figure 5 As shown, the gap-filling oxide film 27 is formed by burying the gap-filling oxide inside the trench 200 .

[0048] In one embodiment, the gap-filling oxide film 27 may be formed by a gap-filling process, which includes a flowable chemical vapor deposition (FCVD) process and a high pressure oxidation (HPO) process, which is performed after the FCVD process.

[0049] In one embodiment, an FCVD process may be first performed to form the gap-filling oxide film 27. According to the FCVD process, a flowable film such as a liquid or a gel and containing a Si component may be deposited as a gap-filling oxide inside the trench 200. After the gap-filling oxide is buried inside the trench 200, curing or annealing may be performed to combine substances in the gap-filling oxide.

[0050] The HPO process may be performed after the FCVD process is performed. When the HPO process is performed, at least one gas of O2, O3, H2O (steam), D2O (steam), N2O, CO, and CO2 may be supplied to a processing device (e.g., a chamber or a furnace) loaded with the substrate 21. Furthermore, when the HPO process is performed, the internal gas pressure of the processing device loaded with the substrate 21 may be maintained at 2 to 50 atmospheres. Furthermore, when the HPO process is performed, the internal temperature of the processing device loaded with the substrate 21 may be maintained at 200° C. to 1000° C. The gap-filling oxide film 27 may be formed by performing the HPO process under such conditions.

[0051] As described above, in the manufacturing process of the semiconductor device according to one embodiment, the gap filling oxide film 27 can be formed by performing the HPO process in a high pressure (2 to 50 atmospheres) oxygen atmosphere and a low temperature (200° C. to 1000° C.) environment after performing the FCVD process.

[0052] When the gap filling oxide film 27 is formed by the FCVD process and the HPO process performed sequentially, the gaps caused by foreign matter removed during the formation of the gap filling oxide film 27 or by physical changes of the film that may occur due to curing or annealing during the FCVD process (stress generated when the film becomes solid) are filled with at least one gas of O2, O3, H2O (steam), D2O (steam), N2O, CO, and CO2, so that the density of the gap filling oxide film 27 is greater than the current density. In this way, when the quality of the gap filling oxide film 27 is improved, the electrical characteristics of the semiconductor element 2 can be improved compared to the current state.

[0053] Next, if Figure 6 As shown, the gap filling oxide film 27 is planarized by performing a chemical mechanical polishing (CMP) process using the pad oxide film 26 as a polishing stopper film.

[0054] Next, if Figure 7 As shown, the element isolation region can be completed by removing the pad oxide film 26, the pad nitride film 25, the second pad oxide film 24, and the pad nitride film 23 in sequence.

[0055] Figure 8 is a cross-sectional view of a capacitor element including a gap-filling oxide film. And, Fig. 9 Graphs showing leakage values ​​measured when voltage is applied to capacitor elements including a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment, respectively, Fig.10 Graphs showing charge retention times measured when voltage is applied to capacitor elements including a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment, respectively.

[0056] Figure 8 The capacitor element shown is used to confirm the electrical characteristics of a semiconductor element including a gap-filling oxide film of the prior art and the electrical characteristics of a semiconductor element including a gap-filling oxide film of an embodiment.

[0057] Reference Figure 8 According to an embodiment, the capacitor element 3 includes a substrate 31 , an oxide film 32 , a dielectric layer 33 , and an electrode 34 .

[0058] The substrate 31 is made of a material such as silicon (Si) and may be P-type doped.

[0059] In another embodiment, the substrate 31 may be made of at least one of Si and SiGe. For example, the substrate 31 may be a single layer made of Si or a single layer made of SiGe. As another example, the substrate 31 may have a multilayer structure in which a first layer made of Si and a second layer made of SiGe are alternately stacked.

[0060] The oxide film 32 is an insulating layer and can be formed by at least one process of high density plasma (HDP), flowable chemical vapor deposition (FCVD), and high pressure oxidation (HPO).

[0061] The dielectric layer 33 is made of a dielectric (eg, HfO 3 ), and plays a role in inducing charges between the substrate 31 and the electrode 34 .

[0062] The electrode 34 may be made of a metal material (eg, TiN).

[0063] Fig. 9 and 10 They show the Figure 8 The electrical characteristics of the capacitor element 3, namely the leakage current and the charge retention time, are measured when a voltage is applied to the capacitor element 3 shown in FIG. Fig. 9 and 10 , M1 refers to a capacitor element in which the oxide film 32 is formed by the HDP process, M2 refers to a capacitor element in which the oxide film 32 is formed by additionally performing the HDP process after performing the FCVD process, and M3 refers to a capacitor element in which the oxide film 32 is formed by additionally performing the HPO process after performing the FCVD process according to the embodiment.

[0064] like Fig. 9 As shown, the leakage current of the capacitor element M3 including the oxide film 32 formed by performing the HPO process additionally after performing the FCVD process according to one embodiment is smaller than the leakage current of the capacitor elements (M1, M2) including the oxide film formed by other processes. Fig.10 As shown, the charge retention time of the capacitor element M3 including the oxide film 32 formed by performing the HPO process additionally after the FCVD process according to one embodiment is greater than the charge retention time of the capacitor elements ( M1 , M2 ) including the oxide films formed by other processes.

[0065] Therefore, according to one embodiment, a semiconductor element including an oxide film formed by performing an HPO process additionally after performing an FCVD process can exhibit better electrical characteristics than a semiconductor element including an oxide film formed by an HDP process or an oxide film formed by performing an HDP process additionally after performing an FCVD process.

[0066] Fig.11 FIG. 1 is a graph showing the etching rates of a gap-filling oxide film according to the prior art and a gap-filling oxide film according to an embodiment.

[0067] exist Fig.11 In the figure, F1 represents a gap-filling oxide film formed by a general wet oxidation process, F2 represents a gap-filling oxide film formed by a HDP process, F3 represents a gap-filling oxide film formed by performing an HDP process additionally after performing an FCVD process, and F4 represents a gap-filling oxide film formed by performing an HPO process additionally after performing an FCVD process according to an embodiment.

[0068] Fig.11 The etching rates (Wet Etching Rate, WER) measured when each gap filling oxide film (F1 to F4) is wet etched under the same conditions are shown. Fig.11 As shown, the etching rate of the gap filling oxide film F4 formed by performing the HPO process additionally after the FCVD process according to one embodiment is lower than the etching rate of other gap filling oxide films (F1, F2, F3). This result means that the density of the gap filling oxide film F4 formed by performing the HPO process additionally after the FCVD process according to one embodiment is higher than the density of the gap filling oxide films (F1, F2, F3) formed by other processes. Therefore, as in one embodiment, when the gap filling oxide film is formed by performing the HPO process additionally after the FCVD process, the gap filling oxide film is more dense and stable, and the density of the gap filling oxide film is increased, so that the cracking phenomenon of the gap filling oxide film can be prevented during the formation of the element isolation region.

[0069] As described above, in the method for manufacturing a semiconductor element according to the present invention, a gap filling process including a high pressure oxidation (HPO) process is performed to form a gap filling oxide film. In particular, a semiconductor element including an oxide film formed by additionally performing a high pressure oxidation (HPO) process after performing a flowable chemical vapor deposition (FCVD) process exhibits excellent electrical characteristics compared to a semiconductor element including an oxide film formed by a conventional process.

[0070] On the other hand, as another embodiment, the gap-filling oxide film may be formed by additionally performing a HDP process after sequentially performing a FCVD process and a HPO process.

[0071] As described above, the present specification is described with reference to the drawings shown, but the present specification is not limited to the embodiments and drawings disclosed in the present specification, and various modifications can be made by a person skilled in the art. In addition, although the effects based on the configuration of the present specification are not explicitly described in the description of the embodiments of the present specification, the effects that can be predicted based on the configuration should be recognized.

Claims

1. A method for manufacturing a semiconductor element, characterized in that: include: The gap filling step is to bury the gap filling oxide into the groove formed on the substrate to form a gap filling oxide film. Wherein, the gap filling process includes a high pressure oxidation process.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The high-pressure oxidation process is performed in a treatment device supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: When the high-pressure oxidation process is performed, the internal pressure of the treatment device is maintained at 2 atmospheres to 50 atmospheres.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: When the high pressure oxidation process is performed, the internal temperature of the processing device is maintained at 200°C to 1000°C.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The gap-filling oxide film is formed by performing the high-pressure oxidation process after performing a flowable chemical vapor deposition process using the gap-filling oxide.

6. A method for manufacturing a semiconductor element, It is characterized in that The following steps are involved: etching the substrate to form a groove; forming a lining layer on the inner surface of the groove; forming a gap-filling oxide film on the liner layer for gap-filling the inside of the trench; and planarizing the gap filling oxide film, The gap-filling oxide film is formed by a gap-filling process including a high-pressure oxidation process.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The high-pressure oxidation process is performed in a treatment device supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: When the high-pressure oxidation process is performed, the internal pressure of the treatment device is maintained at 2 atmospheres to 50 atmospheres.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: When the high pressure oxidation process is performed, the internal temperature of the processing device is maintained at 200°C to 1000°C.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The gap-filling oxide film is formed by performing the high pressure oxidation process after performing a flowable chemical vapor deposition process.

11. The method for manufacturing a semiconductor device according to claim 6, wherein: The liner layer has a single-layer or multi-layer structure composed of at least one component of a nitride film, an oxide film, and polysilicon.

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