SPICE model modeling method and device, simulation method and device, medium and equipment
By automatically generating test key matrix and GDS layout and using these tools to automatically fit SPICE models, the problem of long modeling time in the existing technology is solved, improving simulation efficiency and reducing costs.
Patent Information
- Application Number
- CN202411795791.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-03-18
AI Technical Summary
The modeling process of existing SPICE models takes a long time, resulting in slower efficiency in simulating semiconductor devices using SPICE models.
By obtaining semiconductor device information and design rule information, determining the test key category, automatically generating the test key matrix and GDS layout, and automatically fitting the initial SPICE model using the GDS layout to obtain the final SPICE model and model card.
The modeling time of SPICE model is shortened, the efficiency of using SPICE model to simulate semiconductor devices is improved, and labor costs are reduced.
Smart Images
Figure CN119647383A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a SPICE modeling method, a simulation method and a device, a medium and equipment. Background Art
[0002] SPICE (Simulation Program with Integrated Circuit Emphasis) is a language simulator software used for circuit description and simulation. It is used to detect the integrity of circuit connections and functions, and to predict the behavior of circuits.
[0003] In order to perform SPICE simulation, you must first establish a device-level SPICE model, such as a SPICE model for MOS devices, so that there is a specific mathematical model in the simulation program to describe the corresponding semiconductor device. The SPICE model of semiconductor devices is closely related to the semiconductor manufacturing process, and the SPICE model of semiconductor devices can be used to simulate the characteristics of semiconductor devices produced by the corresponding semiconductor manufacturing plant.
[0004] However, the modeling process of the existing SPICE model is time-consuming, resulting in low efficiency in simulating semiconductor devices using the SPICE model. Summary of the invention
[0005] The problem to be solved by the present invention is to shorten the modeling time of the SPICE model so as to improve the efficiency of simulating semiconductor devices by using the SPICE model.
[0006] To solve the above problems, an embodiment of the present invention provides a SPICE modeling method, the method comprising:
[0007] Acquiring semiconductor device information and design rule information of each semiconductor device;
[0008] Determining the test key categories of various semiconductor devices included in the semiconductor device information;
[0009] Based on the test key categories of various semiconductor devices and the corresponding design rule information, the corresponding test key matrix is automatically generated;
[0010] Based on the test key matrix, automatically generate a corresponding GDS layout;
[0011] The generated GDS layout is used to automatically fit the initial SPICE model to obtain the final SPICE model and model card.
[0012] In a possible embodiment, determining the test key category of each semiconductor device included in the semiconductor device information includes:
[0013] Classifying each semiconductor device included in the semiconductor device information;
[0014] All test key categories of various semiconductor devices in the semiconductor device information are obtained from a preset test key category database; the test key category of the semiconductor device is a classification of semiconductor devices under the same device category according to physical characteristics.
[0015] In a possible embodiment, the automatically generating a corresponding test key matrix based on the test key category of the semiconductor device and the corresponding design rule information includes:
[0016] Based on the test key category of the semiconductor device, determining key parameters corresponding to the test key category;
[0017] Based on the design rule information of the semiconductor device, identifying the maximum value and the minimum value of the key parameter of each of the test key categories;
[0018] Based on the recognition result, a test key matrix of the semiconductor device is automatically obtained.
[0019] In a possible embodiment, automatically obtaining the test key matrix of the semiconductor device based on the recognition result includes:
[0020] Based on the maximum and minimum values of the key parameters of each test key category, obtaining each vertex of the test key matrix;
[0021] Connecting the vertices of the test key matrix in sequence to obtain the edges of the test key matrix;
[0022] Taking values of the key parameters of the test key category on each edge of the test key matrix and within the graphics enclosed by each edge according to the preset matrix precision;
[0023] The value results of the key parameters of the test key category are recorded, and the non-key parameters of the test key category are assigned values.
[0024] In a possible embodiment, the automatically generating a corresponding GDS layout based on the test key matrix includes:
[0025] Based on the design rule information of the semiconductor device, assigning values to key parameters of the semiconductor device, and assigning values to the GDS number and GDS type of the GDS layout;
[0026] Reading the test key matrix and assigning values to key parameters of the test key category;
[0027] The preset function is called to generate the GDS layout based on the assignment results of the key parameters of the semiconductor device, the assignment results of the GDS number and the GDS type of the GDS layout, and the assignment results of the key parameters of the test key category.
[0028] In a possible embodiment, generating a corresponding GDS layout based on the test key matrix further includes:
[0029] In the GDS layout, a test terminal of the semiconductor device is generated, and based on the test key matrix, the test terminal is connected with other terminals of the semiconductor device in the GDS layout.
[0030] In a possible embodiment, the method of automatically fitting the initial SPICE model using the generated GDS layout to obtain the final SPICE model and model card includes:
[0031] Carry out tape-out according to the generated GDS layout, and perform WAT test on the semiconductor devices obtained by tape-out to obtain WAT test results;
[0032] By using an artificial intelligence module, the WAT test results are compared with target values, the initial SPICE model is automatically fitted, and the final SPICE models and model cards corresponding to various semiconductor devices are obtained.
[0033] An embodiment of the present invention further provides a semiconductor device simulation method, the method comprising:
[0034] Automatically calling the SPICE model of the semiconductor device to simulate the semiconductor device;
[0035] Wherein, the SPICE model is obtained by using any of the above-mentioned SPICE model modeling methods.
[0036] The embodiment of the present invention further provides a SPICE modeling device, the device comprising:
[0037] An acquisition unit, adapted to acquire semiconductor device information and design rule information of each semiconductor device;
[0038] a determination unit, adapted to determine the test key categories of various semiconductor devices included in the semiconductor device information;
[0039] A matrix generation unit, adapted to automatically generate a corresponding test key matrix based on the test key categories of various semiconductor devices and corresponding design rule information;
[0040] A layout generation unit, adapted to automatically generate a corresponding GDS layout based on the test key matrix;
[0041] The fitting unit is suitable for automatically fitting the initial SPICE model using the generated GDS layout to obtain the final SPICE model and model card.
[0042] An embodiment of the present invention further provides a semiconductor device simulation device, which includes: a simulation unit, adapted to automatically call a SPICE model of the semiconductor device to simulate the semiconductor device; wherein the SPICE model is obtained using the above-mentioned SPICE model modeling device.
[0043] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any of the above methods.
[0044] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.
[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0046] By applying the solution of the present invention, after obtaining semiconductor device information and design rule information of each semiconductor device, the test key category of each semiconductor device is first determined, and then based on the test key category of the semiconductor device and the corresponding design rule information, the corresponding test key matrix is automatically generated, and then the corresponding GDS layout can be automatically generated based on the test key matrix, and finally the generated GDS layout is used to automatically fit the initial SPICE model to obtain the final SPICE model and model card corresponding to each of the semiconductor devices. Among them, by automatically generating the corresponding test key matrix, compared with manually generating the test key matrix, the time spent on generating the test key matrix can be shortened, and the labor cost can be reduced. In addition, by automatically generating the GDS layout, compared with manually drawing the GDS layout, the drawing cycle of the GDS layout can be shortened, and the labor cost can be reduced. And by using the generated GDS layout, the initial SPICE model is automatically fitted, compared with manual fitting, the time spent on fitting can also be shortened, and the labor cost can be reduced. Therefore, by adopting the solution of the present invention, the time spent on test key matrix, GDS layout and model fitting can be shortened, and the labor cost can be reduced, thereby shortening the modeling time of the SPICE model, thereby improving the efficiency of simulating semiconductor devices using the SPICE model. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 is a flow chart of a SPICE modeling method in an embodiment of the present invention;
[0048] Figure 2 It is a schematic diagram of the principle of generating a test key matrix in an embodiment of the present invention;
[0049] Figure 3 It is a structural diagram of a GDS layout;
[0050] Figure 4 It is a schematic diagram of a process of obtaining a SPICE model and simulating a semiconductor device using the SPICE model in an embodiment of the present invention;
[0051] Figure 5 It is a structural schematic diagram of a SPICE modeling device in an embodiment of the present invention. DETAILED DESCRIPTION
[0052] At present, the modeling process of establishing a SPICE model takes a long time, resulting in a low efficiency in simulating semiconductor devices using the SPICE model.
[0053] To address this problem, the present invention provides a SPICE modeling method. By adopting this method, a SPICE model of a semiconductor device can be automatically established using a computer, thereby shortening the modeling time of the SPICE model and improving the efficiency of simulating semiconductor devices using the SPICE model.
[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0055] Reference Figure 1 The embodiment of the present invention provides a SPICE modeling method, which may include the following steps:
[0056] Step 11: Acquire semiconductor device information and design rule information of each semiconductor device.
[0057] In a specific implementation, the computer may receive a device list input from the outside to obtain semiconductor device information. The semiconductor device information includes a semiconductor device identifier, and the semiconductor device identifier may indicate which semiconductor device the semiconductor device is.
[0058] In a specific implementation, the design rule information of the semiconductor device may include: value range information of each size parameter of the semiconductor device. Taking a MOS tube as an example, the design rule information of the MOS tube may include: minimum width information of the active area, through hole size information, minimum spacing from the polysilicon area to the active area, length information, width information, distance from the isolation area (STI) to the gate structure (Gate), etc.
[0059] Step 12: Determine the test key category of each semiconductor device included in the semiconductor device information.
[0060] In an embodiment of the present invention, the test key category of the semiconductor device is a classification of semiconductor devices under the same device category according to physical characteristics, which belongs to the well-known technology in the art. That is to say, in this art, semiconductor devices have been classified according to the physical characteristics of semiconductor devices, and the category obtained by classifying semiconductor devices according to the physical characteristics of semiconductor devices is called a test key category. For example, semiconductor devices can be classified according to the DC characteristics, AC characteristics, temperature characteristics, noise characteristics, etc. of semiconductor devices. The same type of semiconductor devices may have only one test key category or may have multiple test key categories. Semiconductor devices of different test key categories have different corresponding key parameters. The key parameters of the test key category are used to reflect the physical characteristics of the semiconductor device corresponding to the test key category.
[0061] For example, for MOS tubes, according to the test key categories, they can be divided into basic MOS tubes, well proximity effect (WPE) MOS tubes, etc. The key parameters of the basic MOS tube are the channel length (L) and channel width (W) of the MOS tube. The key parameters of the WPE MOS tube include the channel length (L) and channel width (W) of the MOS tube, as well as the distance from the isolation region (STI) to the gate structure (Gate) (SA and SB, SA represents the distance from the isolation region on the first side of the gate structure to the gate structure, SB represents the distance from the isolation region on the second side of the gate structure to the gate structure, and the first side of the gate structure is opposite to the second side).
[0062] In one embodiment of the present invention, after obtaining semiconductor device information, each semiconductor device contained in the semiconductor device information can be classified, and then the test key category of each type of semiconductor device in the semiconductor device information can be obtained from a preset test key category database; all test key categories of the semiconductor device are classifications of semiconductor devices under the same device category according to physical characteristics.
[0063] The preset test key category database contains all test key categories corresponding to various types of semiconductor devices. According to the semiconductor device identification, the semiconductor devices are first classified, so that semiconductor devices belonging to the same category can be screened out, which is convenient for comparison with the preset test key category database. Among them, the categories of semiconductor devices may include: MOS tubes, diodes, triodes, etc. For example, all MOS tubes can be screened out from the semiconductor device list and then compared with the preset test key category database. After comparing with the preset test key category database, all test key categories contained in each type of semiconductor device can be automatically obtained.
[0064] Step 13: automatically generate a corresponding test key matrix based on the test key categories of various semiconductor devices and the corresponding design rule information.
[0065] Specifically, in one embodiment, the corresponding test key category key parameters can be determined based on the test key category of the semiconductor device, and then the maximum and minimum values of each test key category key parameter can be identified based on the design rule information of the semiconductor device. Finally, based on the identification result, the test key matrix of the semiconductor device can be automatically obtained.
[0066] Different test key categories have different corresponding test key category key parameters. Based on the test key category of the semiconductor device, the corresponding test key category key parameters can be determined, and then the values of the corresponding test key category key parameters can be identified from the design rule information of each semiconductor device of the same category, so as to obtain the maximum and minimum values of the test key category key parameters in the semiconductor device of this category. Finally, based on the identification results, the test key matrix of the semiconductor device is automatically obtained.
[0067] In one embodiment, automatically obtaining the test key matrix of the semiconductor device based on the recognition result may include: obtaining each vertex of the test key matrix based on the maximum and minimum values of the key parameters of each test key category; connecting the vertices of the test key matrix in sequence to obtain each edge of the test key matrix; taking values of the key parameters of the test key category on each edge of the test key matrix and in the graphics surrounded by each edge according to a preset matrix accuracy; recording the value results of the key parameters of the test key category, and assigning values to the non-critical design parameters of the test key category.
[0068] In a specific implementation, each vertex of the test key matrix is a maximum value combination of each test key category key parameter. In the coordinate system corresponding to the test key category key parameter, each test key category key parameter maximum value combination forms a plurality of points as the vertices of the test key matrix. Each vertex of the test key matrix is sequentially connected to obtain each edge of the test key matrix. Subsequently, the key parameters of the test key category can be taken and the non-key parameters of the test key category can be assigned values in the graph formed by the vertices and edges of the test key matrix.
[0069] Taking MOS transistors as an example, for devices whose test key category is basic MOS transistors, the corresponding test key category key parameters are the channel length (L) and channel width (W) of the MOS transistor. The maximum and minimum values of the channel length of the basic MOS transistor, as well as the maximum and minimum values of the channel width, can be obtained from the design rule information. For example, the minimum value of the channel length of the basic MOS transistor is 180nm and the maximum value is 10um.
[0070] Afterwards, refer to Figure 2 , each vertex of the test key matrix can be obtained according to the maximum and minimum values of the channel length and the channel width, wherein the minimum value of the channel width and the minimum value of the channel length (Wmin / Lmin) are used as the vertex A of the test key matrix, the maximum value of the channel width and the maximum value of the channel length (Wmax / Lmax) are used as the vertex B of the test key matrix, the minimum value of the channel width and the maximum value of the channel length (Wmin / Lmax) are used as the vertex C of the test key matrix, and the maximum value of the channel width and the minimum value of the channel length (Wmax / Lmin) are used as the vertex D of the test key matrix. Connecting vertices A, D, B and C in sequence, we can obtain edges AD, DB, BC and CA, and the figure surrounded by the vertices and the edges is a rectangle.
[0071] Next, you can take values on the four sides of the rectangle or within the rectangle according to the accuracy requirements, such as Figure 2 As shown in the blue dots in the middle. The channel length and channel width corresponding to each point are recorded as channel length and channel width, which can be stored in the execl table. At the same time, the non-critical parameters of the test key category can be assigned in the execl table. The data stored in the execl table are the values of each element of the test key matrix.
[0072] In a specific implementation, the test key category non-critical parameters refer to the parameters of the test key category other than the test key category critical parameters. The accuracy requirement may be input by a user through an input device or set in other ways.
[0073] In a specific implementation, a script algorithm or an interface program can be written in Python, so that the corresponding test key matrix can be automatically generated according to the test key categories of various semiconductor devices and the corresponding design rule information. The script algorithm or interface program can provide an adjustment interface, through which the user can adjust the accuracy of the test key matrix as needed.
[0074] Step 14: Automatically generate a corresponding GDS layout based on the test key matrix.
[0075] In the specific implementation, Python language can be used to write script algorithms or interface programs to automatically read the test key matrix, thereby automatically generating the corresponding GDS layout. Among them, GDS layout (Geometry Data System) is a binary file format used to describe the layout and circuit connections of semiconductor chips. GDS layout contains information such as various geometric shapes, hierarchical structures, circuit elements and connections, and is widely used in various stages of semiconductor design, including circuit design, layout design and manufacturing process.
[0076] Specifically, when implemented in Python language, the key parameters of the semiconductor device and the GDS number and GDS type of the GDS layout can be assigned based on the design rule information of the semiconductor device. Then, the test key matrix is read to assign the key parameters of the test key category. Finally, a preset function is called to generate the GDS layout based on the assignment results of the key parameters of the semiconductor device, the assignment results of the GDS number and GDS type of the GDS layout, and the assignment results of the key parameters of the test key category.
[0077] Among them, the key parameters of semiconductor devices refer to the key parameters that affect the size of semiconductor devices, such as the minimum width of the active area, the size of the through hole, the minimum spacing between the polysilicon area and the active area, etc. The key parameters of the semiconductor device are assigned to ensure that the generated GDS layout can pass the design rule check (DRC).
[0078] In the GDS layout, the layout information is recorded according to the GDS number and GDS type. Assigning the GDS number and GDS type of the GDS layout can ensure the normal generation of the GDS file.
[0079] Use the script algorithm or interface program to automatically read the test key matrix row by row, obtain the value of the test key matrix parameters (including the key parameters of the test key matrix and the non-key parameters of the test key matrix), and then call the underlying core function to automatically generate the corresponding GDS layout. The generated GDS layout is identified by the GDS number and GDS type. For examples of GDS layout, please refer to Figure 3 .
[0080] In one embodiment, generating the corresponding GDS layout based on the test key matrix may also include: generating a test terminal (PAD) of the semiconductor device in the GDS layout, and connecting the test terminal with other terminals of the semiconductor device in the GDS layout based on the test key matrix.
[0081] In practical applications, it is necessary to perform wafer acceptance test (WAT) on semiconductor devices after GDS layout tape-out. During the WAT test, the probe will be inserted into the test end for testing. To facilitate the WAT test, after the GDS layout is generated, the test end is generated in the GDS layout, and the connection is automatically performed according to the value results of the test key matrix. Among them, the number of test ends can include multiple. For example, using a script algorithm or an interface program, the drain (D), gate (G), and source (S) of the MOS tube can be automatically connected to the corresponding test end for the next step of WAT testing.
[0082] Step 15, using the generated GDS layout, automatically fit the initial SPICE model to obtain the final SPICE model and model card.
[0083] In a specific implementation, the initial SPICE model usually includes several model equations and several model parameters. Taking the MOS tube as an example, the initial SPICE model of the MOS tube has a model equation for characterizing the DC characteristics of the MOS device, a model equation for characterizing the AC characteristics of the MOS tube, and a model equation for characterizing other characteristics of the MOS tube (temperature characteristics, noise characteristics, layout characteristics, etc.), each model equation may include at least one equation, and each equation may include at least one model parameter. The model parameters in the initial SPICE model can be used to characterize the electrical characteristics of the target device, such as the model parameters for characterizing the saturation current I+, linear current I, turn-off current I of the MOS tube, linear threshold voltage V- and saturation threshold voltage Vtsat. Correspondingly, the model parameters in the initial SPICE model can also be used to characterize the physical characteristics of semiconductor devices, such as the model parameters for characterizing the channel length, channel width and gate oxide thickness of the MOS tube, which will not be illustrated one by one here. All model parameters constitute the model card of the initial SPICE model.
[0084] For ease of understanding, a simple initial SPICE model is used as an example to illustrate, and the initial SPICE model is defined as F(x, y, z)=f1(Ax)+f2(By+Cz), wherein f1(Ax) and f2(By+Cz) are model equations of the initial SPICE model, and A, B, and C are the three model parameters in the initial SPICE model. At this time, the values of the model parameters A, B, and C are all initial values.
[0085] It should be noted that the above initial SPICE model F(x, y, z)=f1(Ax)+f2(By+Cz) is only used to assist in explaining the solution of this embodiment and does not represent a similar initial SPICE model in practice.
[0086] In one embodiment, when fitting the initial SPICE model, the generated GDS layout can be firstly used for tape-out, and the semiconductor devices obtained by tape-out can be subjected to WAT test to obtain WAT test results, and then the WAT test results can be compared with the target values to automatically complete the fitting of the initial SPICE model and obtain the final SPICE models and model cards corresponding to various types of semiconductor devices.
[0087] The WAT test result refers to the silicon value of the semiconductor device obtained by the WAT test. The WAT test result is compared with the target silicon value, and the parameter values of each model equation in the initial SPICE model are adjusted based on the comparison result until the difference between the AT test result and the target silicon value meets the requirement. When the difference requirement is met, the parameter values of each model equation form a model card, and the SPICE model at this time is the final SPICE model.
[0088] In some embodiments, an artificial intelligence (AI) module can be used to automatically complete the fitting of the initial SPICE model to obtain a SPICE model that meets the requirements. At this time, the same type of semiconductor devices can be simulated using the same final SPICE model.
[0089] By adopting the solution of the embodiment of the present invention, after the user provides semiconductor device information and design rule information of each semiconductor device, SPICE models of multiple types of semiconductor devices can be automatically obtained based on Python and AI modules, which greatly shortens the modeling time of the SPICE model, thereby improving the efficiency of simulating semiconductor devices using the SPICE model.
[0090] An embodiment of the present invention further provides a semiconductor device simulation method, the method comprising: automatically calling a SPICE model of the semiconductor device to simulate the semiconductor device.
[0091] Wherein, the SPICE model is obtained by using any of the SPICE modeling methods in the above embodiments.
[0092] Figure 4 FIG. 1 is a schematic diagram of a process of obtaining a SPICE model and using the SPICE model to simulate a semiconductor device in an embodiment of the present invention. Figure 4 , after receiving the device list and semiconductor device design rule information, the Python language can be used to write a script algorithm or interface program to automatically generate a test key matrix. After that, the Python language can be used to write a script algorithm or interface program to automatically read the test key matrix and generate the corresponding GDS layout. Perform a WAT test based on the generated GDS layout to obtain the WAT test result, receive the target value provided externally, compare the WAT test result with the target value, automatically complete the fitting of the initial SPICE model, and the final model card. Finally, the Python language is used to write a script algorithm or interface program, call the final SPICE model, simulate the semiconductor device, and record the simulation results. By analyzing the simulation results later, the performance of the semiconductor device can be understood.
[0093] By using the semiconductor device simulation method in the embodiment of the present invention, the modeling process of the SPICE model is relatively short, thereby improving the simulation efficiency of the semiconductor device.
[0094] In order to enable those skilled in the art to better understand and implement the present invention, the device, test system, electronic device and computer-readable storage medium corresponding to the above method are described in detail below.
[0095] Reference Figure 5 The embodiment of the present invention further provides a SPICE model modeling device 50, which may include: an acquisition unit 51, a determination unit 52, a matrix generation unit 53, a layout generation unit 54, and a fitting unit 55. Among them:
[0096] The acquisition unit 51 is adapted to acquire semiconductor device information and design rule information of each semiconductor device;
[0097] The determining unit 52 is adapted to determine the test key categories of various semiconductor devices included in the semiconductor device information;
[0098] The matrix generating unit 53 is adapted to automatically generate a corresponding test key matrix based on the test key categories of various semiconductor devices and the corresponding design rule information;
[0099] The layout generation unit 54 is adapted to automatically generate a corresponding GDS layout based on the test key matrix;
[0100] The fitting unit 55 is adapted to automatically fit the initial SPICE model using the generated GDS layout to obtain the final SPICE model and model card.
[0101] Regarding the acquisition unit 51, the determination unit 52, the matrix generation unit 53, the layout generation unit 54 and the fitting unit 55, they can be specifically implemented with reference to the above description of the corresponding steps in the SPICE model building, which will not be repeated here.
[0102] The embodiment of the present invention further provides a semiconductor device simulation device, which may include: a simulation unit. The simulation unit is adapted to automatically call the SPICE model of the semiconductor device to simulate the semiconductor device. The SPICE model is obtained by the above-mentioned SPICE model modeling device.
[0103] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any of the above methods.
[0104] In a specific implementation, the computer-readable storage medium may include: ROM, RAM, magnetic disk or optical disk, etc.
[0105] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.
[0106] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of hardware such as circuits. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.
[0107] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A SPICE modeling method, characterized in that: include: Acquiring semiconductor device information and design rule information of each semiconductor device; Determining the test key categories of various semiconductor devices included in the semiconductor device information; Based on the test key categories of various semiconductor devices and the corresponding design rule information, the corresponding test key matrix is automatically generated; Based on the test key matrix, automatically generate a corresponding GDS layout; The generated GDS layout is used to automatically fit the initial SPICE model to obtain the final SPICE model and model card.
2. The SPICE modeling method according to claim 1, characterized in that: The determining of the test key category of each semiconductor device included in the semiconductor device information includes: Classifying each semiconductor device included in the semiconductor device information; All test key categories of various semiconductor devices in the semiconductor device information are obtained from a preset test key category database; the test key category of the semiconductor device is a classification of semiconductor devices under the same device category according to physical characteristics.
3. The SPICE modeling method according to claim 2, characterized in that: The method of automatically generating a corresponding test key matrix based on the test key category of the semiconductor device and the corresponding design rule information includes: Based on the test key category of the semiconductor device, determining key parameters corresponding to the test key category; Based on the design rule information of the semiconductor device, identifying the maximum value and the minimum value of the key parameter of each of the test key categories; Based on the recognition result, a test key matrix of the semiconductor device is automatically obtained.
4. The SPICE modeling method according to claim 3, characterized in that: The method of automatically obtaining a test key matrix of the semiconductor device based on the recognition result includes: Based on the maximum and minimum values of the key parameters of each test key category, obtaining each vertex of the test key matrix; Connecting the vertices of the test key matrix in sequence to obtain the edges of the test key matrix; taking values of the key parameters of the test key category on the edges of the test key matrix and in the graphs surrounded by the edges according to the preset matrix precision; The value results of the key parameters of the test key category are recorded, and the non-key parameters of the test key category are assigned values.
5. The SPICE modeling method according to claim 1, wherein: The method of automatically generating a corresponding GDS layout based on the test key matrix includes: Based on the design rule information of the semiconductor device, assigning values to key parameters of the semiconductor device, and assigning values to the GDS number and GDS type of the GDS layout; Reading the test key matrix and assigning values to key parameters of the test key category; The preset function is called to generate the GDS layout based on the assignment results of the key parameters of the semiconductor device, the assignment results of the GDS number and the GDS type of the GDS layout, and the assignment results of the key parameters of the test key category.
6. The SPICE modeling method according to claim 5, characterized in that: The generating a corresponding GDS layout based on the test key matrix also includes: In the GDS layout, a test terminal of the semiconductor device is generated, and based on the test key matrix, the test terminal is connected with other terminals of the semiconductor device in the GDS layout.
7. The SPICE modeling method according to claim 1, characterized in that: The method of automatically fitting the initial SPICE model using the generated GDS layout to obtain the final SPICE model and model card includes: Carry out tape-out according to the generated GDS layout, and perform WAT test on the semiconductor devices obtained by tape-out to obtain WAT test results; By using an artificial intelligence module, the WAT test results are compared with target values, the initial SPICE model is automatically fitted, and the final SPICE models and model cards corresponding to various semiconductor devices are obtained.
8. A semiconductor device simulation method, characterized in that: include: Automatically calling the SPICE model of the semiconductor device to simulate the semiconductor device; Wherein, the SPICE model is obtained by using the SPICE model modeling method described in any one of claims 1 to 7.
9. A SPICE modeling device, characterized in that: include: An acquisition unit, adapted to acquire semiconductor device information and design rule information of each semiconductor device; a determination unit, adapted to determine the test key categories of various semiconductor devices included in the semiconductor device information; A matrix generation unit, adapted to automatically generate a corresponding test key matrix based on the test key categories of various semiconductor devices and corresponding design rule information; The layout generation unit is suitable for automatically generating a corresponding GDS layout based on the test key matrix; the fitting unit is suitable for automatically fitting the initial SPICE model using the generated GDS layout to obtain a final SPICE model and a model card.
10. A semiconductor device simulation device, characterized in that: include: A simulation unit, adapted to automatically call a SPICE model of the semiconductor device to simulate the semiconductor device; Wherein, the SPICE model is obtained by using the SPICE model modeling device described in claim 9.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 8.
12. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor runs the computer program, the steps of the method according to any one of claims 1 to 8 are performed.