Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a conductive layer, and a resistor. The conductive layer is located above the substrate; the conductive layer comprises a plurality of metal wires which are arranged at intervals along a first direction; the resistor is located between any two adjacent metal wires; wherein the resistor covers the part, between any two adjacent metal wires, of the substrate and the side walls of any two adjacent metal wires, and at least part of the top surfaces of the metal wires are exposed. According to the invention, the process steps are effectively simplified, the problem of etching penetration of the resistor is avoided, and the yield of semiconductor products is improved while the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Integrated resistors are an important part of integrated circuits. The performance of analog integrated circuits is easily affected by electrical properties such as mismatch, temperature coefficient of resistance (TCR) and resistivity of integrated resistors. Film resistors are widely used in analog circuit design because of their advantages such as near-zero temperature coefficient of resistance (TCR), low noise, good matching performance and good electrical correction capability.

[0003] The thin film resistor in the related art is usually formed between the first metal layer and the second metal layer of the semiconductor structure. Since the contact structure between the first metal layer and the second metal layer is usually formed above the thin film resistor, it is usually necessary to form a patterned etch stop layer (for example, a TiN layer) above the thin film resistor to protect the thin film resistor during the formation of the contact hole.

[0004] However, this method is prone to cause the problem of etching through the thin film resistor during the formation of the contact hole, which not only reduces the electrical performance of the thin film resistor, but also easily causes process contamination problems, which has an adverse effect on the yield of semiconductor products. Summary of the invention

[0005] Based on this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, so as to effectively simplify the process steps and avoid the problem of resistor punch-through, thereby reducing production costs and improving the yield of semiconductor products.

[0006] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer and a resistor. The conductive layer is located above the substrate; the conductive layer includes a plurality of metal wires arranged at intervals along a first direction; the resistor is located between any two adjacent metal wires; wherein the resistor covers the substrate between any two adjacent metal wires and the sidewalls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires.

[0007] In some embodiments, the semiconductor structure further comprises a first electrode structure and a capacitor dielectric layer. The first electrode structure is located between the substrate and the conductive layer; the capacitor dielectric layer is located on a side of the first electrode structure away from the substrate; wherein the conductive layer is located on a side of the capacitor dielectric layer away from the first electrode structure; and a plurality of the metal wires are reused as a plurality of second electrode structures.

[0008] In some embodiments, the semiconductor structure further includes a first dielectric layer and a plurality of contact structures. The first dielectric layer is located on a side of the conductive layer away from the substrate; the first dielectric layer at least covers the conductive layer and the resistor; a plurality of contact structures are embedded in the first dielectric layer, electrically connected to the top surface of each of the metal wires, and extend along a second direction; wherein the second direction intersects the first direction; and there is no contact between the contact structure and the resistor.

[0009] In some embodiments, the semiconductor structure further comprises a metal contact layer. The metal contact layer covers the top surface of each of the metal wires; the contact structure is electrically connected to the top surface of the metal wire through the metal contact layer.

[0010] In some embodiments, the semiconductor structure further includes a top metal layer and a second dielectric layer. The top metal layer is located on a side of each contact structure away from the conductive layer, and the top metal layer is electrically connected to each contact structure; the second dielectric layer is located on a side of the top metal layer away from the first dielectric layer, and the second dielectric layer covers the top metal layer.

[0011] In some embodiments, the resistor forms an ohmic contact with a sidewall of the metal wire.

[0012] In some embodiments, the material of the resistor includes silicon-chromium alloy.

[0013] On the other hand, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments, which can be used to prepare the semiconductor structure described in the previous aspect of the present application; the method for manufacturing the semiconductor structure includes: providing a substrate; forming a conductive layer above the substrate, the conductive layer including a plurality of metal wires arranged at intervals along a first direction; forming a resistance material layer covering the conductive layer; at least etching the resistance material layer on the top of the metal wires so that the resistance material layer retained between any two adjacent metal wires constitutes a resistor; wherein the resistor covers the substrate between any two adjacent metal wires and the side walls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires.

[0014] In some embodiments, before forming a conductive layer above the substrate, the manufacturing method further includes: forming a first electrode structure above the substrate; forming a capacitor dielectric layer on a side of the first electrode structure away from the substrate; wherein the conductive layer is formed on a side of the capacitor dielectric layer away from the first electrode structure; and a plurality of the metal wires are reused as a plurality of second electrode structures.

[0015] In some embodiments, after etching at least the resistive material layer on the top of the metal wire so that the resistive material layer retained between any two adjacent metal wires constitutes a resistor, the manufacturing method further includes: forming a first dielectric layer on the side of the conductive layer away from the substrate; the first dielectric layer at least covers the conductive layer and the resistor; etching the first dielectric layer above each of the metal wires to form a plurality of contact holes; the contact holes expose a portion of the top surface of the metal wire and extend along a second direction; the second direction intersects with the first direction; forming a contact structure in each of the contact holes; a plurality of the contact structures are electrically connected to the top surface of each of the metal wires; wherein there is no contact between each of the contact structures and the resistor; forming a top metal layer on the side of each of the contact structures away from the conductive layer; the top metal layer is electrically connected to each of the contact structures; forming a second dielectric layer on the side of the top metal layer away from the first dielectric layer; the second dielectric layer covers the top metal layer.

[0016] The embodiments of the present application may or at least have the following advantages:

[0017] In the embodiment of the present application, a resistor is formed between any two adjacent metal wires arranged at intervals along a first direction, and the resistor covers the substrate between any two adjacent metal wires and the side walls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires; in this way, under the premise that the resistor plays a role in improving the electrical properties of the semiconductor structure, the contact hole of the metal wire and the resistor are effectively avoided from contacting, the problem of resistor penetration that may be caused during the formation of the contact hole is avoided, and the process contamination problem and the resistor performance failure problem are prevented, thereby improving the yield of the semiconductor product; and the resistor in the embodiment of the present application can be prepared and formed by a single deposition and etching process, and only requires a single mask definition, which effectively simplifies the process steps, saves costs and improves production efficiency.

[0018] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of a semiconductor structure provided in some embodiments;

[0021] Figure 2 A schematic diagram of another semiconductor structure provided in some embodiments;

[0022] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0023] Figure 4 is a flow chart of step S200 provided in some embodiments;

[0024] Figure 5 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0025] Figure 6 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0026] Figure 7 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0027] Figure 8 A schematic diagram of a structure obtained after forming a conductive layer provided in some embodiments;

[0028] Fig. 9 A schematic diagram of a structure obtained after forming a resistance material layer provided in some embodiments;

[0029] Fig.10 A schematic diagram of a structure obtained after forming a resistor provided in some embodiments;

[0030] Fig.11 A schematic diagram of a structure obtained after forming a first dielectric layer provided in some embodiments;

[0031] Fig.12 A schematic diagram of a structure obtained after forming a contact hole provided in some embodiments;

[0032] Fig.13 A schematic diagram of a structure obtained after forming a contact structure provided in some embodiments;

[0033] Fig.14 A schematic diagram of a structure obtained after forming a top metal layer provided in some embodiments;

[0034] Fig.15 A schematic diagram of a structure obtained after forming a first electrode material layer, a capacitor dielectric material layer, and a second electrode material layer provided in some embodiments;

[0035] Fig.16 A schematic diagram of a structure obtained after forming a first electrode structure, a capacitor dielectric layer, and a second electrode structure provided in some embodiments;

[0036] Fig.17 It is a schematic structural diagram of another structure obtained after forming a resistor provided in some embodiments.

[0037] Description of reference numerals:

[0038] S-substrate, 1-conductive layer, 11-metal wire, 2-resistor, 21-resistance material layer, 3-first dielectric layer, 4-contact structure, G-contact hole, 5-metal contact layer, 6-top metal layer, 7-second dielectric layer, 8-pad layer, P-pad, 9-capacitor structure, 91-first electrode structure, 910-first electrode material layer, 92-capacitor dielectric layer, 920-capacitor dielectric material layer, 93-second electrode structure, 930-second electrode material layer. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0044] The embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, so as to effectively simplify the process steps and avoid the problem of resistor 2 being etched through, thereby reducing production costs and improving the yield of semiconductor products.

[0045] In some embodiments, see Figure 1 , the semiconductor structure includes a substrate S, a conductive layer 1 and a resistor 2. The conductive layer 1 is located above the substrate S; the conductive layer 1 includes a plurality of metal wires 11 arranged at intervals along a first direction (for example, an X direction); the resistor 2 is located between any two adjacent metal wires 11; wherein the resistor 2 covers the substrate S between any two adjacent metal wires 11 and the sidewalls of any two adjacent metal wires 11, and exposes at least a portion of the top surface of the metal wires 11.

[0046] For example, the substrate S can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate S can be a single-layer structure or a multi-layer structure. For example, the substrate S can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate S can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate S should not limit the scope of protection of the present application.

[0047] In some embodiments, the substrate S includes a transistor; the transistor includes a source region, a drain region, and a gate structure.

[0048] For example, the conductive layer 1 may be electrically connected to a source region, a drain region and / or a gate structure of a transistor.

[0049] By way of example, the conductive layer 1 includes but is not limited to the first metal layer in the semiconductor structure.

[0050] For example, the material of the conductive layer 1 includes, but is not limited to, conductive metal; the material of the conductive layer 1 may be, for example, copper (Cu) or tungsten (W).

[0051] In some embodiments, the material of the resistor 2 includes but is not limited to resistivity material; the material of the resistor 2 may be, for example, silicon-chromium alloy (CrSi).

[0052] By way of example, the resistor 2 includes but is not limited to a film resistor 2 (Film Resistor).

[0053] It should be noted that the thin film resistor 2 (Film Resistor) has the advantages of a temperature coefficient of resistance (TCR) close to zero, low noise characteristics, good matching performance and good electrical correction capability, and can play a role in improving the electrical performance of semiconductor structures.

[0054] In the embodiment of the present application, the resistor 2 is formed between any two adjacent metal wires 11 arranged at intervals along the first direction, and the resistor 2 covers the substrate S between any two adjacent metal wires 11 and the side walls of any two adjacent metal wires 11, and exposes at least a portion of the top surface of the metal wire 11; in this way, under the premise that the resistor 2 plays a role in improving the electrical properties of the semiconductor structure, the contact hole G of the metal wire 11 is effectively avoided from contacting the resistor 2, and the problem of the resistor 2 being pierced during the formation of the contact hole G is avoided, and the process contamination problem and the performance failure problem of the resistor 2 are prevented, thereby improving the yield of the semiconductor product; and the resistor 2 in the embodiment of the present application can be prepared by a single deposition and etching process, and only one mask definition is required, which effectively simplifies the process steps, saves costs and improves production efficiency.

[0055] For example, please refer to Figure 1 , the side wall of each metal wire 11 can be a slope.

[0056] In some embodiments, the resistor 2 forms an ohmic contact with the sidewall of the metal wire 11 .

[0057] It should be noted that the ohmic contact formed between the resistor 2 and the side wall of the metal wire 11 is beneficial to reduce the size of the resistor 2 in the first direction (for example, the X direction) while ensuring the electrical connection between the resistor 2 and the metal wire 11, thereby effectively avoiding contact between the contact hole G of the metal wire 11 and the resistor 2.

[0058] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a first dielectric layer 3 and a plurality of contact structures 4. The first dielectric layer 3 is located on the side of the conductive layer 1 facing away from the substrate S; the first dielectric layer 3 at least covers the conductive layer 1 and the resistor 2; the plurality of contact structures 4 are embedded in the first dielectric layer 3, electrically connected to the top surface of each metal wire 11, and extend along a second direction (for example, a Y direction); wherein the second direction intersects with the first direction; and there is no contact between the contact structure 4 and the resistor 2.

[0059] For example, the material of the first dielectric layer 3 includes but is not limited to insulating materials; the material of the first dielectric layer 3 may be, for example, an oxide (OX), such as silicon oxide (SiO) or silicon dioxide (SiO 2 )wait.

[0060] It should be noted that the first dielectric layer 3 can be used to achieve insulation isolation between the metal wires 11 of the conductive layer 1 , and to achieve insulation isolation between the contact structures 4 .

[0061] By way of example, the material of the contact structure 4 includes, but is not limited to, a conductive material; the material of the contact structure 4 may be, for example, a conductive metal such as copper (Cu) or tungsten (W).

[0062] For example, the size of each contact structure 4 in the first direction (eg, the X direction) is smaller than the size of each metal wire 11 in the first direction (eg, the X direction).

[0063] In some embodiments, contact holes G are formed in the first dielectric layer 3 ; accordingly, a plurality of contact structures 4 are embedded in each of the contact holes G.

[0064] For example, the size of each contact hole G in the first direction (eg, the X direction) is smaller than the size of each metal wire 11 in the first direction (eg, the X direction).

[0065] In some examples, there is no overlap between the orthographic projection of the contact hole G on the substrate S along the second direction (for example, the Y direction) and the resistor 2; that is, there is no contact between the contact hole G and the resistor 2. In this way, it should be noted that the embodiment of the present application effectively avoids the contact hole G of the metal wire 11 from contacting the resistor 2, avoids the problem of the resistor 2 being cut through during the formation of the contact hole G, prevents process contamination problems and performance failure problems of the resistor 2, thereby improving the yield of semiconductor products.

[0066] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a metal contact layer 5 . The metal contact layer 5 covers the top surface of each metal wire 11 ; the contact structure 4 is electrically connected to the top surface of the metal wire 11 through the metal contact layer 5 .

[0067] It should be noted that the metal contact layer 5 can also be used to protect the underlying metal wire 11 during the etching process of the contact hole G, that is, the metal contact layer 5 can also be reused as an etching stop layer.

[0068] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a top metal layer 6 and a second dielectric layer 7. The top metal layer 6 is located on a side of each contact structure 4 away from the conductive layer 1, and the top metal layer 6 is electrically connected to each contact structure 4; the second dielectric layer 7 is located on a side of the top metal layer 6 away from the first dielectric layer 3, and the second dielectric layer 7 covers the top metal layer 6.

[0069] For example, the material of the top metal layer 6 includes, but is not limited to, a conductive material; the material of the top metal layer 6 may be, for example, copper (Cu) or tungsten (W).

[0070] In some examples, the top metal layer 6 includes a plurality of conductive structures, wherein each conductive structure may correspond one-to-one to each contact structure 4 and be electrically connected.

[0071] For example, the material of the second dielectric layer 7 includes but is not limited to insulating materials; the material of the second dielectric layer 7 may be, for example, oxide (OX), such as silicon oxide (SiO) or silicon dioxide (SiO 2 )wait.

[0072] It should be noted that the second dielectric layer 7 can be used to achieve insulation isolation between the conductive structures of the top metal layer 6 .

[0073] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a pad layer 8. The pad layer 8 includes a plurality of pads P, wherein each pad P may correspond to each conductive structure of the top conductive layer 1 one by one and be electrically connected.

[0074] It should be noted that, in some possible implementations, the resistor 2 in the semiconductor structure provided in the embodiment of the present application may also be formed above the upper electrode of the capacitor structure 9; the specific implementations are as follows:

[0075] For some examples, see Figure 2 The semiconductor structure further includes a first electrode structure 91 and a capacitor dielectric layer 92. The first electrode structure 91 is located between the substrate S and the conductive layer 1; the capacitor dielectric layer 92 is located on the side of the first electrode structure 91 away from the substrate S; wherein the conductive layer 1 is located on the side of the capacitor dielectric layer 92 away from the first electrode structure 91; and a plurality of metal wires 11 are multiplexed into a plurality of second electrode structures 93.

[0076] Please refer to Figure 2 , the semiconductor structure includes a capacitor structure 9. The capacitor structure 9 includes a second electrode structure 93, a capacitor dielectric layer 92 and a first electrode structure 91 stacked in sequence from bottom to top along a second direction (for example, the Y direction). The first electrode structure 91 is also the lower electrode of the capacitor structure 9, and the second electrode structure 93 is also the upper electrode of the capacitor structure 9.

[0077] For some examples, see Figure 2 Any two adjacent second electrode structures 93 can share the same capacitor dielectric layer 92 and the same first electrode structure 91 .

[0078] For example, the resistor 2 covers the capacitor dielectric layer 92 between any two adjacent second electrode structures 93 and the sidewalls of any two adjacent second electrode structures 93 , and exposes at least a portion of the top surface of each second electrode structure 93 .

[0079] By way of example, each contact structure 4 may correspond to each second electrode structure 93 one by one and be electrically connected.

[0080] By way of example, the capacitor structure 9 includes but is not limited to a Metal-Insulator-Metal (MIM) capacitor structure 9 .

[0081] By way of example, the material of the first capacitor structure 9 includes, but is not limited to, a conductive material; the material of the first capacitor structure 9 may be, for example, a conductive metal such as copper (Cu) or tungsten (W).

[0082] For example, the material of the capacitor dielectric layer 92 includes but is not limited to insulating material; the material of the capacitor dielectric layer 92 may also be ferroelectric material or high dielectric (Hight-K, HK for short) material, etc., which is not limited in the present application.

[0083] The present application also provides a method for manufacturing a semiconductor structure according to some embodiments, and the method for manufacturing a semiconductor structure can be used to prepare the semiconductor structures in some of the above embodiments. The method for manufacturing the semiconductor structure also has the technical advantages of the above semiconductor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0084] In some embodiments, see Figure 3 , the manufacturing method of the semiconductor structure includes the following steps S100~S400.

[0085] S100 , providing a substrate.

[0086] S200, forming a conductive layer above the substrate; the conductive layer includes a plurality of metal wires arranged at intervals along a first direction.

[0087] S300, forming a resistance material layer covering the conductive layer.

[0088] S400, at least etching the resistance material layer on the top of the metal wire so that the resistance material layer retained between any two adjacent metal wires constitutes a resistor; wherein the resistor covers the substrate between any two adjacent metal wires and the side walls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wire.

[0089] In the embodiment of the present application, a resistor is formed between any two adjacent metal wires arranged at intervals along a first direction, and the resistor covers the substrate between any two adjacent metal wires and the side walls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires; in this way, under the premise that the resistor plays a role in improving the electrical properties of the semiconductor structure, the contact hole of the metal wire and the resistor are effectively avoided from contacting, the problem of resistor penetration that may be caused during the formation of the contact hole is avoided, and the process contamination problem and the resistor performance failure problem are prevented, thereby improving the yield of the semiconductor product; and the resistor in the embodiment of the present application can be prepared and formed by a single deposition and etching process, and only requires a single mask definition, which effectively simplifies the process steps, saves costs and improves production efficiency.

[0090] In some embodiments, see Figure 4 , step S200 includes the following steps S210~S230.

[0091] S210, forming a conductive material layer above the substrate.

[0092] S220, etching the conductive material layer to form a plurality of metal conductive lines spaced apart along a first direction to obtain a conductive layer.

[0093] S230, forming a metal contact layer on a side of each metal conductive line facing away from the substrate; the metal contact layer covers the top surface of each metal conductive line.

[0094] In some embodiments, see Figure 5 , after step S400, the manufacturing method further includes the following steps S510~S550.

[0095] S510, forming a first dielectric layer on a side of the conductive layer facing away from the substrate; the first dielectric layer at least covers the conductive layer and the resistor.

[0096] S520, etching the first dielectric layer above each metal wire to form a plurality of contact holes; the contact holes expose a portion of the top surface of the metal wire and extend along a second direction, and the second direction intersects the first direction.

[0097] S530, forming a contact structure in each contact hole; a plurality of contact structures are electrically connected to the top surface of each metal wire; wherein, there is no contact between each contact structure and the resistor.

[0098] S540, forming a top metal layer on a side of each contact structure away from the conductive layer; the top metal layer is electrically connected to each contact structure.

[0099] S550, forming a second dielectric layer on a side of the top metal layer away from the first dielectric layer; the second dielectric layer covers the top metal layer.

[0100] In some embodiments, see Figure 6 , the second dielectric layer exposes the top surface of the top metal layer away from the first dielectric layer; after step S550, the manufacturing method further includes the following steps S560~S570.

[0101] S560 , forming a pad material layer on a side of the top metal layer facing away from the first dielectric layer.

[0102] S570, etching the pad material layer to form a plurality of pads spaced apart along a first direction; wherein each pad is electrically connected to a corresponding top metal layer.

[0103] In some embodiments, see Figure 7 Before step S200, the method for manufacturing the semiconductor structure further includes the following steps S610 to S620.

[0104] S610, forming a first electrode structure above the substrate.

[0105] S620, forming a capacitor dielectric layer on a side of the first electrode structure facing away from the substrate.

[0106] Accordingly, please continue to refer to Figure 7 In step S200, a conductive layer is formed on a side of the capacitor dielectric layer away from the first electrode structure; and a plurality of metal wires are reused as a plurality of second electrode structures.

[0107] It should be understood that although Figure 3~Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3~Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0108] In order to more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 8~Figure 17 Understand.

[0109] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps S100 to S400.

[0110] In step S100 , a substrate S is provided.

[0111] In step S200, refer to Figure 8 , a conductive layer 1 is formed on the substrate S; the conductive layer 1 includes a plurality of metal wires 11 arranged at intervals along a first direction.

[0112] In some embodiments, step S200 includes the following steps S210 to S230.

[0113] In step S210 , a conductive material layer is formed on the substrate S.

[0114] By way of example, the formation process of the conductive material layer includes, but is not limited to, a deposition process.

[0115] In step S220, please continue to refer to Figure 8 , etching the conductive material layer to form a plurality of metal wires 11 spaced apart along a first direction (eg, X direction), thereby obtaining a conductive layer 1 .

[0116] For example, the etching process of the conductive material layer includes but is not limited to a dry etching process; the etching process of the conductive material layer may be, for example, a photolithography process.

[0117] In step S230, please continue to refer to Figure 8 A metal contact layer 5 is formed on the side of each metal wire 11 facing away from the substrate S; the metal contact layer 5 covers the top surface of each metal wire 11.

[0118] In step S300, refer to Fig. 9 , forming a resistance material layer 21 covering the conductive layer 1.

[0119] By way of example, the formation process of the conductive material layer includes, but is not limited to, a deposition process.

[0120] For example, the material of the resistance material layer 21 includes, but is not limited to, a resistivity material; the material of the resistance material layer 21 may be, for example, a silicon-chromium alloy (CrSi).

[0121] In step S400, refer to Fig.10 , at least the resistance material layer 21 on the top of the metal wire 11 is etched so that the resistance material layer 21 retained between any two adjacent metal wires 11 constitutes a resistor 2; wherein the resistor 2 covers the substrate S between any two adjacent metal wires 11 and the side walls of any two adjacent metal wires 11, and exposes at least a portion of the top surface of the metal wire 11.

[0122] For example, the etching process of the resistance material layer 21 includes but is not limited to a dry etching process; the etching process of the resistance material layer 21 may be a photolithography process, for example.

[0123] In some embodiments, after step S400, the manufacturing method further includes the following steps S510 to S550.

[0124] In step S510, refer to Fig.11 , a first dielectric layer 3 is formed on the side of the conductive layer 1 facing away from the substrate S; the first dielectric layer 3 at least covers the conductive layer 1 and the resistor 2.

[0125] In step S520, refer to Fig.12 , etching the first dielectric layer 3 above each metal wire 11 to form a plurality of contact holes G; the contact holes G expose a portion of the top surface of the metal wire 11 and extend along a second direction, which intersects the first direction.

[0126] For example, the etching process of the first dielectric layer 3 includes but is not limited to a dry etching process; the etching process of the first dielectric layer 3 may be a photolithography process, for example.

[0127] For example, the size of each contact structure 4 in the first direction (eg, the X direction) is smaller than the size of each metal wire 11 in the first direction (eg, the X direction).

[0128] It is worth mentioning that in the embodiment of the present application, the photolithography line width of the contact hole G can be controlled by defining the photolithography mask of the contact hole G, so as to control the distance between the resistor 2 and each contact hole G in the first direction (for example, the X direction); for example, it can be made so that there is no overlap between the positive projection of the contact hole G on the substrate S along the second direction (for example, the Y direction) and the resistor 2; that is, there is no contact between the contact hole G and the resistor 2. In this way, it should be noted that the embodiment of the present application effectively avoids the contact hole G of the metal wire 11 from contacting the resistor 2, avoids the problem of the resistor 2 being cut through during the formation of the contact hole G, prevents the process contamination problem and the performance failure problem of the resistor 2, and thus improves the yield of semiconductor products.

[0129] In step S530, refer to Fig.13 , a contact structure 4 is formed in each contact hole G; multiple contact structures 4 are electrically connected to the top surface of each metal wire 11; wherein, there is no contact between each contact structure 4 and the resistor 2.

[0130] By way of example, the process of forming the contact structure 4 includes, but is not limited to, a filling process.

[0131] In step S540, refer to Fig.14 , a top metal layer 6 is formed on a side of each contact structure 4 away from the conductive layer 1 ; the top metal layer 6 is electrically connected to each contact structure 4 .

[0132] In step S550, refer to Figure 2 , a second dielectric layer 7 is formed on the side of the top metal layer 6 facing away from the first dielectric layer 3 ; the second dielectric layer 7 covers the top metal layer 6 .

[0133] In some embodiments, the second dielectric layer 7 exposes the top surface of the top metal layer 6 away from the first dielectric layer 3 ; after step S550 , the manufacturing method further includes the following steps S560 - S570 .

[0134] In step S560 , a pad P material layer is formed on a side of the top metal layer 6 facing away from the first dielectric layer 3 .

[0135] By way of example, the material of the pad P material layer includes, but is not limited to, a conductive material; the material of the pad P material layer may be, for example, a conductive metal such as copper (Cu) or tungsten (W).

[0136] In step S570, refer to Figure 2 , the pad P material layer is etched to form a plurality of pads P spaced apart along a first direction; wherein each pad P is electrically connected to a corresponding top metal layer 6 .

[0137] It should be noted that, in some possible implementations, the resistor 2 in the semiconductor structure provided in the embodiment of the present application may also be formed above the upper electrode of the capacitor structure 9; the specific implementations are as follows:

[0138] In some examples, the semiconductor structure further includes a capacitor structure 9; the capacitor structure 9 includes a first electrode structure 91, a capacitor dielectric layer 92, and a second electrode structure 93 stacked sequentially from bottom to top along a second direction (eg, the Y direction).

[0139] In some embodiments, before step S200 , the method for manufacturing a semiconductor structure further includes steps S610 - S620 .

[0140] In step S610, refer to Fig.16 , a first electrode structure 91 is formed above the substrate S.

[0141] In step S620, please continue to refer to Fig.16 A capacitor dielectric layer 92 is formed on the side of the first electrode structure 91 facing away from the substrate S.

[0142] It should be noted that, in some examples, before step S610, the following steps are also included: Fig.15 A first electrode material layer 910 , a capacitor dielectric material layer 920 , and a second electrode material layer 930 are formed on the substrate S and are sequentially stacked from bottom to top along a second direction (eg, the Y direction).

[0143] Accordingly, see Fig.16, step S610 includes etching the first electrode material layer 910, so that the retained portion of the first electrode material layer 910 corresponds to the first electrode structure 91; step S620 includes etching the capacitor dielectric material layer 920, so that the retained portion of the capacitor dielectric material layer 920 corresponds to the capacitor dielectric layer 92; step S200 includes etching the second electrode material layer 930, and the retained portion of the second electrode material layer 930 corresponds to the second electrode structure 93. Among them, the etching process of the first electrode material layer 910, the capacitor dielectric material layer 920 and the second electrode material layer 930 can be performed simultaneously, and the present disclosure does not limit this.

[0144] Accordingly, see Figure 16-17 In step S200 , the conductive layer 1 is formed on the side of the capacitor dielectric layer 92 away from the first electrode structure 91 ; and the plurality of metal wires 11 are reused as the plurality of second electrode structures 93 .

[0145] It should be noted that the structures in the subsequent steps S300 to S400 can be further prepared and formed on the capacitor structure 9 formed in steps S610 to S620 to obtain the following structure: Figure 2 The semiconductor structure shown; the specific preparation method can be found in some of the aforementioned embodiments of the present application and will not be described in detail here.

[0146] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0147] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A conductive layer, located above the substrate; the conductive layer comprises a plurality of metal wires arranged at intervals along a first direction; A resistor, located between any two adjacent metal wires; The resistor covers the substrate between any two adjacent metal wires and the sidewalls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A first electrode structure is located between the substrate and the conductive layer; a capacitor dielectric layer, located on a side of the first electrode structure facing away from the substrate; Wherein, the conductive layer is located on a side of the capacitor dielectric layer away from the first electrode structure; The plurality of metal wires are reused as a plurality of second electrode structures.

3. The semiconductor structure according to any one of claims 1 or 2, characterized in that: Also includes: A first dielectric layer, located on a side of the conductive layer away from the substrate; The first dielectric layer at least covers the conductive layer and the resistor; A plurality of contact structures, embedded in the first dielectric layer, electrically connected to the top surface of each of the metal wires, and extending along the second direction; The second direction intersects with the first direction; and there is no contact between the contact structure and the resistor.

4. The semiconductor structure according to claim 3, characterized in that: Also includes: A metal contact layer, covering the top surface of each of the metal wires; The contact structure is electrically connected to the top surface of the metal wire through the metal contact layer.

5. The semiconductor structure according to claim 3, characterized in that: Also includes: A top metal layer, located on a side of each contact structure away from the conductive layer, and electrically connected to each contact structure; The second dielectric layer is located on a side of the top metal layer away from the first dielectric layer and covers the top metal layer.

6. The semiconductor structure according to any one of claims 1 or 2, characterized in that: The resistor forms an ohmic contact with a sidewall of the metal wire.

7. The semiconductor structure according to any one of claims 1 or 2, characterized in that: The material of the resistor includes silicon-chromium alloy.

8. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a conductive layer above the substrate; The conductive layer includes a plurality of metal wires arranged at intervals along a first direction; forming a resistive material layer covering the conductive layer; At least etching the resistance material layer on the top of the metal wires, so that the resistance material layer remaining between any two adjacent metal wires constitutes a resistor; The resistor covers the substrate between any two adjacent metal wires and the sidewalls of any two adjacent metal wires, and exposes at least a portion of the top surface of the metal wires.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Before forming a conductive layer on the substrate, the manufacturing method further includes: forming a first electrode structure above the substrate; forming a capacitor dielectric layer on a side of the first electrode structure facing away from the substrate; Wherein, the conductive layer is formed on a side of the capacitor dielectric layer away from the first electrode structure; and a plurality of the metal wires are reused as a plurality of second electrode structures.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: After etching at least the resistance material layer on the top of the metal wires so that the resistance material layer remaining between any two adjacent metal wires forms a resistor, the manufacturing method further includes: forming a first dielectric layer on a side of the conductive layer away from the substrate; the first dielectric layer at least covers the conductive layer and the resistor; Etching the first dielectric layer above each of the metal wires to form a plurality of contact holes; the contact holes expose a portion of the top surface of the metal wires and extend along a second direction; the second direction intersects the first direction; A contact structure is formed in each of the contact holes; a plurality of the contact structures are electrically connected to the top surface of each of the metal wires; wherein no contact exists between each of the contact structures and the resistor; Forming a top metal layer on a side of each of the contact structures away from the conductive layer; the top metal layer is electrically connected to each of the contact structures; A second dielectric layer is formed on a side of the top metal layer away from the first dielectric layer; the second dielectric layer covers the top metal layer.

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