Ternary logic gate circuit, calculation circuit, chip and electronic equipment

Abstract

The invention provides a ternary logic gate circuit, a calculation circuit, a chip and electronic equipment. The ternary logic gate circuit provided by the invention can realize addition and subtraction of 1 to an input logic value. Based on the ternary logic gate circuit, 27 univariate functions of ternary logic are utilized, the ternary logic gate circuit is applied to the ternary logic circuit, the purpose of simplifying the structure of the ternary logic circuit can be achieved, the number of transistors in the ternary logic circuit can be reduced, the power consumption of the ternary logic circuit can be reduced, and the reliability of the ternary logic circuit is improved. And the calculation efficiency of the ternary logic circuit is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of multi-valued logic computing technology, and in particular to a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. Background Art

[0002] With the advent of the big data era, processing huge amounts of data requires chips to have higher computing performance. At present, it is more difficult to improve the computing performance of chips by simply reducing the size of transistors. Therefore, it is necessary to set up large-scale integrated circuits to achieve the purpose of improving the computing performance of chips, but large-scale integrated circuits will bring higher power consumption and interconnection complexity.

[0003] Ternary logic uses three-valued logic to increase information density. Ternary logic can surpass the computing performance of binary logic, so the computing performance of ternary logic circuits is higher than that of binary logic circuits. Ternary logic gate circuits are the basic units that constitute ternary logic circuits, so the design of ternary logic gate circuits is crucial. Summary of the invention

[0004] The embodiments of the present application provide a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided by the present application can realize addition or subtraction of a ternary input logic value.

[0005] In a first aspect, an embodiment of the present application provides a ternary logic gate circuit, which includes a first voltage module and a logic gate module. The first voltage module is used to output a first voltage, and the first voltage is used to represent a first logic value, and the first logic value is any logic value in the ternary logic value. The logic gate module is used to receive the first voltage and output a second voltage, and the second voltage is used to represent a second logic value, and the second logic value is equal to the first logic value plus 1, or the second logic value is equal to the first logic value minus 1.

[0006] The embodiment of the present application designs a ternary logic gate circuit, which can realize the addition or subtraction of an input logic value by 1. As a basic unit of a ternary logic circuit, the ternary logic gate circuit can be applied to a ternary logic circuit, which facilitates the design of a ternary logic circuit with high computing performance.

[0007] In a possible implementation, the logic gate module includes a preprocessing unit, a first processing unit, and a second processing unit, wherein the preprocessing unit is used to receive the first voltage and output a third voltage to the first processing unit, wherein the third voltage is used to represent a third logic value, and the third logic value is 0 or 2.

[0008] Exemplarily, the pre-processing unit may be a negative polarity three-value inverter NTI or a positive polarity three-value inverter PTI. For example, taking the ternary logic values ​​including 0, 1, and 2 as an example, when the first logic value is 0, a third logic value 2 may be output after NTI processing, when the first logic value is 1, a third logic value 0 may be output after NTI processing, and when the first logic value is 2, a third logic value 0 may be output after NTI processing.

[0009] For example, taking the ternary logic values ​​including 0, 1, and 2 as an example, when the first logic value is 0, the third logic value 2 can be output after PTI processing, when the first logic value is 1, the third logic value 2 can be output after NTI processing, and when the first logic value is 2, the third logic value 0 can be output after NTI processing.

[0010] The first processing unit is used to receive the first voltage and the third voltage, and output a fourth voltage to the second processing unit, wherein the fourth voltage is used to represent a fourth logic value, and the fourth logic value includes 0 or 2. The second processing unit is used to receive the fourth voltage, and output the second voltage.

[0011] In some embodiments, the preprocessing unit may be composed of at least one transistor, or the preprocessing unit may be composed of a voltage adjustment unit. After receiving the first voltage, the preprocessing unit may output a third voltage after processing the first voltage by the transistor therein. Alternatively, after receiving the first voltage, the preprocessing unit 221 may adjust the first voltage to a third voltage by the voltage adjustment unit and output the third voltage.

[0012] The structures of the first processing unit and the second processing unit may refer to the description of the preprocessing unit.

[0013] In some embodiments, the first processing unit includes a first group of transistors and a second group of transistors, the second processing unit includes a third group of transistors, the threshold voltage of the transistors in the first group of transistors is a first threshold voltage, the threshold voltage of the transistors in the second group of transistors is a second threshold voltage, and the threshold voltage of the transistors in the third group of transistors is a third threshold voltage.

[0014] Wherein, the first threshold voltage is less than or equal to the first threshold, the third threshold voltage is greater than the first threshold and less than or equal to the second threshold, the second threshold voltage is greater than the second threshold, and the first threshold is less than the second threshold. Wherein, the transistors in the first group of transistors can be called low threshold voltage transistors, the transistors in the second group of transistors can be called medium threshold voltage transistors, and the transistors in the third group of transistors can be called high threshold voltage transistors.

[0015] The first voltage module is respectively connected to the preprocessing module, some transistors in the first group of transistors, and transistors in the second group of transistors; the preprocessing module is connected to the remaining transistors in the first group of transistors; and the transistors in the third group of transistors are connected to the transistors in the first group of transistors and the transistors in the second group of transistors.

[0016] In the embodiment of the present application, transistors with different threshold voltages can be used to design the first processing unit and the second processing unit, so that the logic gate circuit can add 1 or subtract 1 from the first logic value.

[0017] The following describes the principles by which the logic gate circuit can realize adding 1 or subtracting 1 from the first logic value:

[0018] First, the logic gate circuit can realize adding 1 to the first logic value, that is, the second logic value is equal to the first logic value plus 1. In some embodiments, the ternary logic gate circuit can be called a self-decrementing ternary logic gate circuit.

[0019] The first transistor group includes: a first transistor L1, a second transistor L2 and a third transistor L3, the second transistor group includes: a fourth transistor H1 and a fifth transistor H2, and the third transistor group includes: a sixth transistor M1 and a seventh transistor M2.

[0020] Among them, the preprocessing module is a negative polarity three-value inverter NTI, the first transistor L1, the second transistor L2, the fourth transistor H1, and the sixth transistor M1 are P-type transistors, and the third transistor L3, the fifth transistor H2, and the seventh transistor M2 are N-type transistors.

[0021] The following introduces the specific structure of the self-incrementing ternary logic gate circuit:

[0022] The first voltage module is connected to the gate of the first transistor L1, the gate of the fourth transistor H1, and the gate of the fifth transistor H2 respectively, and the NTI is connected to the gate of the second transistor L2 and the gate of the third transistor L3 respectively.

[0023] The source of the first transistor L1 is connected to the second voltage module, the drain of the first transistor L1 is connected to the source of the second transistor L2, the drain of the second transistor L2 is respectively connected to the source of the third transistor L3 and the source of the sixth transistor M1, the drain of the third transistor L3 is grounded, the gate of the sixth transistor M1 is grounded, and the drain of the sixth transistor M1 is connected to the drain of the seventh transistor M2.

[0024] The source of the fourth transistor H1 is connected to the second voltage module, the drain of the fourth transistor H1 is respectively connected to the source of the fifth transistor H2 and the source of the seventh transistor M2, the drain of the fifth transistor H2 is grounded, and the gate of the seventh transistor M2 is connected to the second voltage module.

[0025] It should be understood that when the first voltage module outputs the first voltage, because the first voltage is different, the on and off conditions of the first transistor L1, the second transistor L2, the third transistor L3, the fourth transistor H1, the fifth transistor H2, the sixth transistor M1, and the seventh transistor M2 are also different, and reference can be made to Table 1 in the following embodiment. When the on and off conditions of the transistors in the ternary logic gate circuit are different, the ternary logic gate circuit can be enabled to output different second voltages in different situations, and the second logic value represented by the second voltage is equal to the first logic value plus 1.

[0026] Secondly, the ternary logic gate circuit can realize the first logic value minus 1, that is, the second logic value is equal to the first logic value minus 1. In some embodiments, the ternary logic gate circuit can be called a self-incrementing ternary logic gate circuit.

[0027] The first transistor group includes: a first transistor L1, a second transistor L2 and a third transistor L3, the second transistor group includes: a fourth transistor H1 and a fifth transistor H2, and the third transistor group includes: a sixth transistor M1 and a seventh transistor M2.

[0028] Among them, the preprocessing module is a positive polarity three-value inverter PTI, the first transistor L1, the fourth transistor H1, and the sixth transistor M1 are P-type transistors, and the second transistor L2, the third transistor L3, the fifth transistor H2, and the seventh transistor M2 are N-type transistors.

[0029] The following introduces the specific structure of the self-incrementing ternary logic gate circuit:

[0030] The first voltage module is connected to the gate of the third transistor L3, the gate of the fourth transistor H1, and the gate of the fifth transistor H2 respectively, and the PTI is connected to the gate of the first transistor L1 and the gate of the second transistor L2 respectively.

[0031] The source of the first transistor L1 is connected to the second voltage module, the drain of the first transistor L1 is connected to the source of the second transistor L2 and the source of the seventh transistor M2 respectively, the drain of the second transistor L2 is connected to the source of the third transistor L3, the drain of the third transistor L3 is grounded, the gate of the seventh transistor M2 is connected to the second voltage module, and the drain of the seventh transistor M2 is connected to the drain of the sixth transistor M1.

[0032] The source of the fourth transistor H1 is connected to the second voltage module, the drain of the fourth transistor H1 is connected to the source of the fifth transistor H2 and the source of the sixth transistor M1 respectively, the drain of the fifth transistor H2 is grounded, and the gate of the sixth transistor M1 is grounded.

[0033] In a possible implementation, the ternary logic gate circuit may further include the second voltage module as described above, wherein the second voltage module is configured to output a fifth voltage, and the sum of the first threshold voltage and the second threshold voltage is less than the fifth voltage.

[0034] It should be understood that when the first voltage module outputs the first voltage, because the first voltage is different, the on and off conditions of the first transistor L1, the second transistor L2, the third transistor L3, the fourth transistor H1, the fifth transistor H2, the sixth transistor M1, and the seventh transistor M2 are also different, and reference can be made to Table 1 in the following embodiment. When the on and off conditions of the transistors in the ternary logic gate circuit are different, the ternary logic gate circuit can be enabled to output different second voltages in different situations, and the second logic value represented by the second voltage is equal to the first logic value minus 1.

[0035] In a second aspect, an embodiment of the present application provides a summing circuit, which includes: a first ternary logic gate circuit and a second ternary logic gate circuit.

[0036] In the first ternary logic gate circuit, the second logic value is equal to the first logic value plus 1, and in the second ternary logic gate circuit, the second logic value is equal to the first logic value minus 1. The first ternary logic gate circuit and the second ternary logic gate circuit can refer to the description of the first aspect.

[0037] In a possible implementation, the summing circuit further includes: a signal processing module, a first gating tube, a second gating tube, and a third gating tube.

[0038] The signal processing module is used to connect with the first signal module, and the signal processing module is respectively connected with the first gate tube, the second gate tube, and the third gate tube. The second signal module is used to connect with the first gate tube, the first ternary logic gate circuit, and the second ternary logic gate circuit respectively, the first ternary logic gate circuit is connected with the second gate tube, and the second ternary logic gate circuit is connected with the third gate tube.

[0039] The second signal module is used to output a second signal. The first signal module is used to output a first signal. The signal processing module is used to turn on any gating tube according to the first signal to enable the summing circuit to output a first summation result of the first signal and the second signal.

[0040] In this implementation, the summation circuit provided in the embodiment of the present application can perform a summation calculation on two ternary signals and output a first summation result.

[0041] In a possible implementation, the first signal is used to represent a fifth logic value, and the second signal is used to represent a sixth logic value. When the first gate tube is turned on, the first summation result is: the sum of the fifth logic value and the sixth logic value. When the second gate tube is turned on, the first summation result is: the sum of the sixth logic value plus 1 and the fifth logic value. When the third gate tube is turned on, the first summation result is: the sum of the sixth logic value minus 1 and the fifth logic value.

[0042] In a possible implementation, the signal processing module includes: a first NTI, a second NTI, a PTI, and a NOR gate.

[0043] Among them, the first signal module is respectively connected to the first end of the first NTI and the first end of the PTI, the second end of the first NTI is respectively connected to the first selection tube and the first input end of the NOR gate, the second end of the PTI is connected to the first end of the second NTI, the second end of the second NTI is respectively connected to the second input end of the NOR gate and the third selection tube, and the output end of the NOR gate is connected to the second selection tube.

[0044] In a third aspect, an embodiment of the present application provides a half-adder circuit, which may include the summation circuit in the second aspect.

[0045] In a possible implementation, the half-adder circuit further includes: a first carry device, wherein the first signal module is used to be connected to the summing circuit and the first carry device respectively, and the second signal module is used to be connected to the summing circuit and the first carry device respectively. The first carry device is used to output a first carry result.

[0046] In this implementation, when the first signal and the second signal are summed, the half-adder circuit can not only output the first sum result of the first signal and the second signal, but also output the first carry result when the first signal and the second signal are summed, and can accurately output the sum calculation result of the first signal and the second signal.

[0047] In a fourth aspect, an embodiment of the present application provides a full-adder circuit, including the half-adder circuit in the third aspect, and the half-adder circuit can be called a first-stage half-adder circuit.

[0048] In a possible implementation, the full adder circuit further includes: a second-stage half adder circuit and a second carry, wherein the second-stage half adder circuit is configured to be connected to the third signal module.

[0049] The first-stage half-adder circuit is used to output the first summation result to the second-stage half-adder circuit and the first carry result to the second carry device. The third signal module is used to output the third signal to the second-stage half-adder circuit.

[0050] The second-stage half-adder circuit is used to output a second summation result according to the third signal and the first summation result, and to output a second carry result to the second carry device. The second carry device is used to output a third carry result according to the first carry result and the second carry result.

[0051] In this implementation, a full-adder circuit is provided, which can accurately implement the summation calculation of three ternary signals.

[0052] In a possible implementation, the second-stage half-adder circuit includes: a third ternary logic gate circuit. Wherein, in the third ternary logic gate circuit, the second logic value is equal to the first logic value plus 1. In other words, the third ternary logic gate circuit may be a self-incrementing ternary logic gate circuit, and the third ternary logic gate circuit may refer to the description in the first aspect.

[0053] In a possible implementation, the second-stage half-adder circuit includes: a positive polarity buffer PB, a negative polarity buffer NB, a fourth gate transistor, a fifth gate transistor, an AND gate, and a third ternary logic gate circuit.

[0054] The third signal module is used to be connected to the input end of the PB and the fourth gate tube respectively, the output end of the PB is connected to the fifth gate tube and the second input end of the AND gate respectively, and the quad gate tube is connected to the fifth gate tube. The first-stage half-adder circuit is connected to the third ternary logic gate circuit and the input end of the NB respectively, the third ternary logic gate circuit is connected to the fifth gate tube, and the output end of the NB is connected to the first input end of the AND gate.

[0055] The third signal is used to turn on the fourth gate tube or the fifth gate tube to enable the full-adder circuit to output the second summation result.

[0056] The embodiment of the present application provides a full-adder circuit. A summation circuit can be designed based on a self-incrementing logic gate circuit and a self-decrementing logic gate circuit, and a half-adder circuit can be designed based on the summation circuit. Based on the first-stage half-adder circuit, a full-adder circuit that can sum three ternary signals is designed, with a small number of transistors, low power consumption, and high computing efficiency.

[0057] In a fifth aspect, an embodiment of the present application provides a multiplication circuit, which may include the summation circuit in the second aspect and the half-addition circuit in the third aspect.

[0058] In a possible implementation, the multiplication circuit further includes: a multiplier and an approximate multiplier. The multiplier is used to output a first multiplication result. The approximate multiplier is used to output a second multiplication result. The summation circuit and the half-addition circuit are used to output a third multiplication result according to the first multiplication result and the second multiplication result.

[0059] In this implementation, the idea of ​​approximate multiplication calculation can be used to set an approximate multiplier in the multiplication circuit. The approximate multiplication calculation can achieve higher computing performance and lower power consumption at the cost of a smaller calculation error.

[0060] Here, a 2trit*2trit multiplication circuit is taken as an example, the approximate multiplier includes a first approximate multiplier, a second approximate multiplier, and a third approximate multiplier, and the half-adder circuit includes a first half-adder circuit and a second half-adder circuit.

[0061] Wherein, the first approximate multiplier is used to output a first sub-multiplication result.

[0062] The second approximate multiplier is used to output a second sub-multiplication result to the first half-adder circuit. The third approximate multiplier is used to output a third sub-multiplication result to the first half-adder circuit. The first half-adder circuit is used to output a fourth sub-multiplication result according to the second sub-multiplication result and the third sub-multiplication result, and output a fifth sub-multiplication result to the second half-adder circuit.

[0063] The multiplier is further configured to output the first multiplication result to the second half-adder circuit. The second half-adder circuit is configured to output a sixth sub-multiplication result according to the fifth sub-multiplication result and the first multiplication result, and output a seventh sub-multiplication result to the summing circuit.

[0064] The summing circuit is used to output an eighth sub-multiplication result according to the first multiplication result and the seventh sub-multiplication result.

[0065] In summary, the third multiplication result includes: the first sub-multiplication result, the fourth sub-multiplication result, the sixth sub-multiplication result and the eighth sub-multiplication result.

[0066] It should be understood that the summation circuit and half-addition circuit in the embodiments of the present application can also be applied to 6trit*6trit ternary multiplication circuits, and can even be applied to circuit designs of larger and arbitrary scales, all of which fall within the protection scope of the embodiments of the present application.

[0067] In a sixth aspect, an embodiment of the present application provides a calculation circuit, which is a ternary logic calculation circuit. The ternary logic calculation circuit may include at least one of the following: the summation circuit of the second aspect, the half-addition circuit of the third aspect, the full-addition circuit of the fourth aspect, and the multiplication circuit of the fifth aspect.

[0068] In the seventh aspect, an embodiment of the present application provides a chip, which may include any one of the following circuits: the ternary logic gate circuit of the first aspect, the summation circuit of the second aspect, the half-addition circuit of the third aspect, the full-addition circuit of the fourth aspect, and the multiplication circuit of the fifth aspect.

[0069] In an eighth aspect, an embodiment of the present application provides a chip, which may include at least one of the following circuits: the summation circuit of the second aspect, the half-addition circuit of the third aspect, the full-addition circuit of the fourth aspect, and the multiplication circuit of the fifth aspect.

[0070] In a ninth aspect, an embodiment of the present application provides an electronic device, which may include: the chip in the seventh aspect or the chip in the eighth aspect.

[0071] The beneficial effects of the possible implementation methods of the sixth to ninth aspects mentioned above can be found in the relevant descriptions of the beneficial effects in the first to fifth aspects mentioned above, and will not be elaborated here.

[0072] The embodiment of the present application provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit may include a first voltage module and a logic gate module, wherein the first voltage module is used to output a first voltage, the first voltage is used to represent a first logic value, and the first logic value is any logic value in the ternary logic value. The logic gate module is used to receive the first voltage and output a second voltage, the second voltage is used to represent a second logic value, the second logic value is equal to the first logic value plus 1, or the second logic value is equal to the first logic value minus 1. The ternary logic gate circuit provided by the present application can realize the addition and subtraction of the input logic value, and based on the ternary logic gate circuit, using 27 single variable functions of the ternary logic, the ternary logic gate circuit is applied to the ternary logic circuit, which can achieve the purpose of simplifying the structure of the ternary logic circuit, can reduce the number of transistors in the ternary logic circuit, reduce the power consumption of the ternary logic circuit, and improve the calculation efficiency of the ternary logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1A is a schematic diagram of a ternary logic circuit;

[0074] Figure 1B A schematic diagram for designing another ternary logic circuit;

[0075] Figure 2A A schematic diagram of a ternary logic gate circuit provided in an embodiment of the present application;

[0076] Figure 2B A schematic diagram of a ternary logic gate circuit provided in an embodiment of the present application;

[0077] Figure 3 A schematic diagram of a self-incrementing logic gate circuit provided in an embodiment of the present application;

[0078] Figure 4 A schematic diagram of a self-decrementing logic gate circuit provided in an embodiment of the present application;

[0079] Figure 5 A schematic diagram of a summing circuit provided in an embodiment of the present application;

[0080] Figure 6 A schematic diagram of a half-adder circuit provided in an embodiment of the present application;

[0081] Figure 7 A schematic diagram of a full-adder circuit provided in an embodiment of the present application;

[0082] Figure 8 A schematic diagram of a second-stage half-adder circuit in a full-adder circuit provided in an embodiment of the present application;

[0083] Fig. 9 A schematic diagram of a positive polarity buffer and a negative polarity buffer provided in an embodiment of the present application;

[0084] Fig.10 A schematic diagram of a second carry provided in an embodiment of the present application;

[0085] Fig.11 A schematic diagram comparing an existing ternary multiplication circuit and a ternary multiplication circuit provided in an embodiment of the present application;

[0086] Fig.12 This is a schematic diagram of ternary approximate multiplication;

[0087] Fig.13 A schematic diagram of a ternary multiplication circuit provided in an embodiment of the present application;

[0088] Fig.14 Another schematic diagram of a ternary multiplication circuit provided in an embodiment of the present application;

[0089] Fig.15 Another schematic diagram comparing an existing ternary multiplication circuit and the ternary multiplication circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0090] With the rapid development of technologies such as artificial intelligence, automation, and intelligent driving, the data generated is also growing explosively. With the advent of the big data era, processing huge amounts of data requires chips to have higher computing performance. On the one hand, the size of transistors can be reduced, the number of transistors integrated on the chip can be increased, and the computing performance of the chip can be improved. However, when the size of transistors is reduced to a certain extent, it becomes difficult to further reduce the size of transistors. On the other hand, large-scale integrated circuits can be set up to achieve the purpose of improving the computing performance of the chip, but large-scale integrated circuits will bring higher power consumption and interconnection complexity, and will also cause data processing delays.

[0091] The logic circuits currently integrated in chips are binary logic circuits. Compared with binary logic, multi-valued logic (MVL) uses three-value, four-value or even larger-value logic to improve information density, which helps reduce the interconnection complexity of the chip. Circuit design implemented using multi-valued logic has advantages in improving information density, reducing chip area, and improving the computing power of integrated circuits. Therefore, it is currently possible to design multi-valued logic circuits based on multi-valued logic to improve the computing performance of chips.

[0092] Among them, in multi-valued logic, the theoretical efficiency value of ternary logic is the highest, so deploying ternary logic circuits on a chip can improve the computing performance of the chip. Accordingly, the design of ternary logic circuits is crucial. In some embodiments, the ternary logic circuit can also be called a ternary circuit or a ternary logic calculation circuit.

[0093] In some embodiments, the decoder 11 and the binary circuit 12 can be deployed on the chip. Taking the chip implementing ternary addition calculation as an example, refer to Figure 1A For example, the decoder 11 may include a decoder A and a decoder B, and the chip may receive input 1 and input 2, and perform sum calculation on input 1 and input 2. Input 1 includes A0, A1, and A2, and input 2 includes B0, B1, and B2.

[0094] Among them, after the chip receives input 1 and input 2, decoder A can convert input 1 into a binary logic value, decoder B can convert input 2 into a binary logic value, and binary circuit 12 can add the binary logic value converted by decoder A and the binary logic value converted by decoder B to output the result.

[0095] Figure 1A Although the scheme in can realize ternary logic addition calculation, the interconnection complexity of the circuit is much higher than that of the binary logic circuit with the same function, and the calculation efficiency is low.

[0096] In some embodiments, a ternary logic circuit can be directly deployed according to the truth table of ternary logic. The solution may include the following steps:

[0097] Step 1, develop a truth table for ternary logic.

[0098] Take ternary addition calculation as an example, Figure 1B The truth table of the ternary logic addition is shown in . It should be understood that -1, 0 and 1 are used to represent the ternary logic values ​​in Table 1, and the "-" in Table 1 can represent -1, and the "+" can represent +1.

[0099] After the ternary logic values ​​are added two by two, Figure 1B Table 2 in FIG. 1 can be understood as a pull upswitching map, which shows the partial results of adding logical values ​​to the sum. Figure 1B Table 3 in FIG. 1 can be understood as a pull down switching map, which shows the partial results where the summed result is a decrease in logic value.

[0100] Step 2, optimize the expression to determine the minimum number of transistors and the lowest delay in the ternary logic circuit.

[0101] Step 3: Select the best sum of products (SOP).

[0102] Step 4: Transistor mapping to obtain a ternary logic circuit.

[0103] After the transistor mapping in Table 2, the circuit with increased logic value can be obtained as follows Figure 1B As shown in the circuit 1 in Table 3, after the transistor mapping, the circuit with reduced logic value can be obtained as Figure 1B It should be understood that, taking the addition calculation of ternary signal A and ternary signal B as an example, in circuit 1 and circuit 2, A represents ternary signal A, B represents ternary signal B, and A N Indicates that the ternary signal A is processed by the negative ternary inverter (NTI) and then output. P It indicates that the ternary signal A is processed by the positive ternary inverter (PTI) and then output. N Indicates that the ternary signal B is output after NTI processing, B P It indicates that the ternary signal B is output after being processed by PTI.

[0104] Although this scheme can realize a ternary logic addition circuit, the design of a ternary logic circuit based on the truth table of ternary logic has the disadvantages of complex structure, large number of transistors, large circuit delay and power consumption, and low computing performance. The specific details of this scheme can be referred to the content of the prior art "A logic synthesis methodology for low-power ternary logic circuits".

[0105] In summary, it is very important to design a ternary logic circuit with a simple structure and a small number of transistors. As the basic unit of the ternary logic circuit, the design of the ternary logic gate circuit is very important. The current ternary logic gate circuits are all based on the addition and multiplication of the input signals, and the ternary logic gate circuits are directly designed (such as Figure 1B As shown in FIG. 1 , there is no design solution for the ternary logic gate circuit. It should be understood that when the structure of the ternary logic circuit is simple and the number of transistors is small, the circuit delay of the ternary logic circuit is small, the power consumption is small, and the computing performance is high.

[0106] It should be understood that in circuit design, the single variable function f(x) is a means of realizing digital functions and is widely used. In three-valued logic, the variable x of the single variable function f(x) has three values: 0, 1, and 2, that is, x∈{0,1,2}. It should be noted that in the following embodiments, the logic values ​​in the three-valued logic include "0, 1, and 2" as an example.

[0107] The output value of the single variable function f(x) is different for different values ​​of x. When x=0, the output value of f(x) is C0, C0=f(0); when x=1, the output value of f(x) is C1, C1=f(1); when x=2, the output value of f(x) is C2, C2=f(2). C0∈{0,1,2}, C1∈{0,1,2}, C2∈{0,1,2}. According to the design principle of multi-valued logic circuits, three-valued logic single variable functions include 3 3 =27 kinds. The output values ​​C0, C1 and C2 of these single variable functions at x=0, x=1 and x=2 are arranged in ascending order according to the size of the ternary three-digit numbers C0, C1 and C2, namely f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25 and f26.

[0108] Among them, f0={0,0,0}, f1={0,0,1}, f2={0,0,2}, f3={0,1,0}, f4={0,1,1}, f5={0,1,2}, f6={0,2,0}, f7={0,2,1}, f8={0,2,2}, f9={1,0,0}, f10={1,0,1}, f11={1,0,2}, f12={1,1,0}, f13={1,1, 1}, f14={1,1,2}, f15={1,2,0}, f16={1,2,1}, f17={1,2,2}, f18={2,0,0}, f19={2,0,1}, f20= {2,0,2}, f21={2,1,0}, f22={2,1,1}, f23={2,1,2}, f24={2,2,0}, f25={2,2,1}, f26={2,2,2}.

[0109] Based on the ternary logic single variable function, any input and output can be represented by the ternary logic single variable function, so the embodiment of the present application designs a ternary logic gate circuit, which is used to implement the addition and subtraction of the input logic value. Based on the ternary logic gate circuit, the embodiment of the present application uses 27 single variable functions of ternary logic and applies the ternary logic gate circuit to the ternary logic circuit on a large scale, which can achieve the purpose of simplifying the structure of the ternary logic circuit, reduce the number of transistors in the ternary logic circuit, reduce the power consumption of the ternary logic circuit, and improve the calculation efficiency of the ternary logic circuit.

[0110] The following is a description of the ternary logic gate circuit, ternary logic calculation circuit (calculation circuit), chip and electronic device provided in the embodiments of the present application in conjunction with specific embodiments. The following embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0111] The present application embodiment provides a ternary logic gate circuit, referring to Figure 2A The ternary logic gate circuit 20 includes: a first voltage module 21 and a logic gate module 22 .

[0112] Among them, the first voltage module 21 is used to output a first voltage. Specifically, the first voltage module 21 is used to output a first voltage to the logic gate module 22. The first voltage is used to represent a first logic value, and the first logic value is any logic value in a ternary logic value. Exemplarily, the first logic value is any of the following: 0, 1, 2. In some embodiments, the first logic value can be any of the following: -1, 0, 1. In the embodiment of the present application, the ternary logic value includes "0, 1, 2" as an example for explanation.

[0113] In some embodiments, the mapping relationship between the first voltage and the first logic value can be preset. For example, when the first voltage is a value A, the first voltage represents a first logic value of 0, when the first voltage is a value B, the first voltage represents a first logic value of 1, and when the first voltage is a value C, the first voltage represents a first logic value of 2. For example, when the first voltage is 0V (value A), the first voltage represents a first logic value of 0, when the first voltage is 0.5V (value B), the first voltage represents a first logic value of 1, and when the first voltage is 1V, the first voltage represents a first logic value of 2.

[0114] In some embodiments, the first voltage may also be regarded as the first level. Exemplarily, a mapping relationship between the first level and the first logic value may be preset. For example, a low level represents a first logic value of 0, a medium level represents a first logic value of 1, and a high level represents a first logic value of 2. The low level, the medium level, and the high level may be preconfigured.

[0115] The logic gate module 22 is used to receive the first voltage from the first voltage module 21 and output a second voltage. The second voltage is used to represent a second logic value, and the second logic value is equal to the first logic value plus 1, or the second logic value is equal to the first logic value minus 1. In other words, in the embodiment of the present application, the logic gate module 22 can realize adding 1 or subtracting 1 to the first logic value.

[0116] In some embodiments, the logic gate module 22 may be composed of a plurality of transistors. For example, when the logic gate module 22 receives a first voltage, the first transistor among the plurality of transistors may be controlled to be turned on, enabling the logic gate module 22 to output a second voltage, and the second logic value represented by the second voltage is equal to the first logic value plus 1. For example, when the logic gate module 22 receives a first voltage, the second transistor among the plurality of transistors may be controlled to be turned on, enabling the logic gate module 22 to output a second voltage, and the second logic value represented by the second voltage is equal to the first logic value minus 1. The first transistor may include some transistors among the plurality of transistors, the second transistor may include some transistors among the plurality of transistors, and the first transistor is different from the second transistor.

[0117] In some embodiments, the logic gate module 22 may include a first voltage adjustment unit and a second voltage adjustment unit. Exemplarily, for example, when the logic gate module 22 receives a first voltage, the first voltage adjustment unit may be turned on and the second voltage adjustment unit may be turned off, and the first voltage adjustment unit may adjust the first voltage to a second voltage, and the second logic value represented by the second voltage is equal to the first logic value plus 1. Exemplarily, for example, when the logic gate module 22 receives a first voltage, the second voltage adjustment unit may be turned on and the first voltage adjustment unit may be turned off, and the second voltage adjustment unit is used to adjust the first voltage to a second voltage, and the second logic value represented by the second voltage is equal to the first logic value minus 1. In some embodiments, the first voltage adjustment unit may be composed of a capacitor and / or a resistor, and the second voltage adjustment unit may be composed of a capacitor and / or a resistor.

[0118] The ternary logic gate circuit provided in the embodiment of the present application can realize the addition or subtraction of the input first logic value, that is, the ternary logic gate circuit can realize the self-increment or self-decrement of the logic value. Among them, the self-increment can represent the first logic value plus 1, and the self-decrement can represent the first logic value minus 1.

[0119] In some embodiments, reference Figure 2B The logic gate module 22 includes: a pre-processing unit 221 , a first processing unit 222 , and a second processing unit 223 .

[0120] The first voltage module 21 is used to output the first voltage to the preprocessing unit 221 and the first processing unit 222. Accordingly, the preprocessing unit 221 can receive the first voltage from the first voltage module 21, and the first processing unit 222 can receive the first voltage from the first voltage module 21.

[0121] After receiving the first voltage, the pre-processing unit 221 may output a third voltage to the first processing unit 222. The third voltage is used to represent a third logic value, and the third logic value is 0 or 2.

[0122] In some embodiments, the preprocessing unit 221 may be composed of at least one transistor, or the preprocessing unit 221 may be composed of a voltage adjustment unit. After receiving the first voltage, the preprocessing unit 221 may output a third voltage after processing the first voltage by the transistor therein. Alternatively, after receiving the first voltage, the preprocessing unit 221 may adjust the first voltage to a third voltage by the voltage adjustment unit and output the third voltage.

[0123] The first processing unit 222 may receive the first voltage from the first voltage module 21 and the third voltage from the pre-processing unit 221. The first processing unit 222 may output a fourth voltage to the second processing unit 223. The fourth voltage is used to represent a fourth logic value, and the fourth logic value is 0 or 2.

[0124] In some embodiments, the first processing unit 222 may be composed of at least one transistor, or the first processing unit 222 may be composed of a voltage adjustment unit. After receiving the first voltage and the third voltage, the first processing unit 222 may output a fourth voltage after processing the first voltage and the third voltage by the transistors therein. Alternatively, after receiving the first voltage and the third voltage, the voltage adjustment unit of the first processing unit 222 may adjust the voltage to the fourth voltage and output the fourth voltage.

[0125] The second processing unit 223 can receive the fourth voltage from the first processing unit 222 and output the second voltage.

[0126] In some embodiments, the second processing unit 223 may be composed of at least one transistor, or the second processing unit 223 may be composed of a voltage adjustment unit. After receiving the fourth voltage, the second processing unit 223 may output the second voltage after processing the fourth voltage by the transistor therein. Alternatively, after receiving the fourth voltage, the voltage adjustment unit may adjust the fourth voltage to the second voltage and output the second voltage.

[0127] In the embodiment of the present application, a pre-processing unit 221 , a first processing unit 222 , and a second processing unit 223 are provided in the logic gate module 22 , so as to achieve the purpose of adding 1 or subtracting 1 to the first logic value.

[0128] In the embodiment of the present application, 27 single-variable functions of three-valued logic are used to design a ternary logic gate circuit. In order to further solve the problems of a large number of transistors and high power consumption in the ternary logic circuit in the prior art, the first processing unit 222 and the second processing unit 223 in the embodiment of the present application can also be composed of transistors. This facilitates a clear comparison with the current ternary logic gate circuit. The ternary logic circuit provided in the embodiment of the present application has a small number of transistors, low power consumption, and high computing performance.

[0129] In some embodiments, the first processing unit 222 includes: a first group of transistors and a second group of transistors. The second processing unit 223 includes a third group of transistors. In some embodiments, the first group of transistors may include at least one transistor, the second group of transistors may include at least one transistor, and the third group of transistors may include at least one transistor.

[0130] The first voltage module 21 is connected to the preprocessing module 221, some transistors in the first group of transistors, and transistors in the second group of transistors, respectively. In this way, the first voltage module 21 can output the first voltage to the preprocessing module 221 and the first processing unit 222 (e.g., some transistors in the first group of transistors, and transistors in the second group of transistors), respectively.

[0131] The preprocessing module 221 is connected to the remaining transistors in the first group of transistors, and the transistors in the third group of transistors are connected to the transistors in the first group of transistors and the transistors in the second group of transistors. In this way, when the preprocessing module 221 outputs the third voltage, it can output the third voltage to the first processing unit 222 (for example, the remaining transistors in the first group of transistors). The first processing unit 222 can output the fourth voltage to the second processing unit 223 (for example, the third group of transistors).

[0132] In some embodiments, the first group of transistors, the second group of transistors, and the third group of transistors may be transistors of the same or different types, such as insulated gate bipolar transistors (IGBT), metal-oxide-semiconductor field effect transistors (MOS), etc.

[0133] In some embodiments, the transistors in the first group of transistors, the second group of transistors, and the third group of transistors may be carbon nanotube field effect transistors (CNTFETs). In the embodiments of the present application, in the ternary logic gate circuit, the power consumption of the ternary logic gate circuit may be further reduced by avoiding the use of devices with high power consumption such as resistors and using CNTFETs instead.

[0134] The threshold voltage (Vth) of CNTFET is related to the diameter of CNT, and the diameter of CNT depends on the chirality vector. Therefore, by changing the diameter or chirality vector of CNT, the threshold voltage of CNTFET can be controlled. It should be understood that the threshold voltage of a transistor refers to: the voltage that enables the transistor to turn on. Among them, when the voltage difference between the gate and the source (or drain) of the transistor is greater than or equal to the threshold voltage of the transistor, the transistor is turned on, and when the voltage difference between the gate and the source (or drain) of the transistor is less than the threshold voltage of the transistor, the transistor is turned off (or in a cut-off state).

[0135] In some embodiments, the threshold voltages of transistors in the first group of transistors, the second group of transistors, and the third group of transistors may be the same.

[0136] In some embodiments, the threshold voltages of transistors in the first group of transistors, the second group of transistors, and the third group of transistors may be different. Exemplarily, the threshold voltage of transistors in the first group of transistors is a first threshold voltage, the threshold voltage of transistors in the second group of transistors is a second threshold voltage, and the threshold voltage of transistors in the third group of transistors 2223 is a third threshold voltage. The first threshold voltage is less than or equal to the first threshold, the third threshold voltage is greater than the first threshold and less than or equal to the second threshold, and the first threshold is less than the second threshold. Exemplarily, for example, the first threshold may be 0.35V, and the second threshold may be 0.5V. The first threshold voltage may be set to 0.2V-0.3V, the third threshold voltage may be set to 0.4V, and the second threshold voltage may be set to 0.6V-0.7V.

[0137] In some embodiments, the transistors in the first group of transistors can be called low threshold voltage (low Vthreshold, LVT) transistors, the transistors in the second group of transistors can be called high threshold voltage (high V threshold, HVT) transistors, and the transistors in the third group of transistors 2221 can be called middle threshold voltage (middle V threshold) transistors.

[0138] In the embodiments of the present application, there is no restriction on the specific values ​​of the first threshold voltage, the second threshold voltage, and the third threshold voltage. The first threshold voltage, the second threshold voltage, and the third threshold voltage may be related to the voltage output by the second voltage module. The first threshold voltage, the second threshold voltage, the third threshold voltage, and the second voltage module may refer to the description in the following embodiments.

[0139] The following describes the principle that a ternary logic gate circuit can realize the addition of 1 to a first logic value or the subtraction of 1 to a first logic value with reference to a specific example:

[0140] Example 1: The ternary logic gate circuit can realize the first logic value plus 1, that is, the second logic value is equal to the first logic value plus 1.

[0141] In some embodiments, the pre-processing module 221 is a negative ternary inverter (NTI). The first group of transistors includes: a first transistor L1, a second transistor L2 and a third transistor L3, the second group of transistors includes: a fourth transistor H1 and a fifth transistor H2, and the third group of transistors includes: a sixth transistor M1 and a seventh transistor M2.

[0142] In some embodiments, the first group of transistors, the second group of transistors, and the third group of transistors may be transistors of the same or different polarities, and the polarities may include N-type and P-type. In some embodiments, the first transistor L1, the second transistor L2, the fourth transistor H1, and the sixth transistor M1 are P-type transistors, and the third transistor L3, the fifth transistor H2, and the seventh transistor M2 are N-type transistors.

[0143] In some embodiments, the ternary logic gate circuit may further include a second voltage module, which may provide a fifth voltage (V DD ).

[0144] In some embodiments, the first voltage module 21 and the second voltage module may not be included in the ternary logic gate circuit, wherein the ternary logic gate circuit may receive the first voltage from the first voltage module 21 and the fifth voltage from the second voltage module.

[0145] Reference Figure 3In a, the first voltage module 21 is connected to the gate of the first transistor L1, the gate of the fourth transistor H1, and the gate of the fifth transistor H2, respectively, and NTI is connected to the gate of the second transistor L2 and the gate of the third transistor L3, respectively. The source of the first transistor L1 is connected to the second voltage module, the drain of the first transistor L1 is connected to the source of the second transistor L2, the drain of the second transistor L2 is connected to the source of the third transistor L3 and the source of the sixth transistor M1, respectively, and the drain of the third transistor L3 is grounded. The gate of the sixth transistor M1 is grounded, and the drain of the sixth transistor M1 is connected to the drain of the seventh transistor M2.

[0146] The source of the fourth transistor H1 is connected to the second voltage module, the drain of the fourth transistor H1 is connected to the source of the fifth transistor H2 and the source of the seventh transistor M2 respectively, the drain of the fifth transistor H2 is grounded, and the gate of the seventh transistor M2 is connected to the second voltage module.

[0147] It should be understood that Figure 3 In a, GND indicates grounding, in indicates output, out indicates output, and V DD Represents the second voltage module.

[0148] In the embodiment of the present application, the second voltage module can provide the fifth voltage (V DD ), and the ground voltage is V GND , it can be understood that the highest voltage of the input logic gate module 22 is V DD , the minimum voltage is V GND In order to reflect that the first voltage output by the first voltage module represents any logic value in the ternary logic value, in some embodiments, the first voltage can be set to be equal to V DD When , the first voltage represents the first logic value 2. The first voltage can be set equal to The first voltage represents a first logic value 1. The first voltage can be set equal to V GND When , the first voltage represents a first logic value of 0.

[0149] When the first voltage is equal to V DD When the first voltage passes through NTI, the third voltage V GND (such as 0V), the third voltage represents a third logic value of 0. When the first voltage is equal to When the first voltage passes through NTI, the third voltage V GND (such as 0V), the third voltage represents a third logic value of 0. When the first voltage is equal to V GND When the first voltage passes through NTI, the third voltage V DD(eg, 1V), the third voltage represents a third logic value of 2. In summary, NTI is used to receive the first voltage and output a third voltage, the third voltage value represents a third logic value of 0 or 2.

[0150] Reference Figure 3 b, NTI can be composed of two transistors connected in parallel, the two transistors are an eighth transistor H3 and a ninth transistor L4. The threshold voltage of the eighth transistor H3 is greater than the second threshold, and the threshold voltage of the ninth transistor L4 can be less than or equal to the first threshold. The eighth transistor H3 is a P-type transistor, and the ninth transistor L4 is an N-type transistor. It should be understood that Figure 3 The connection between NTI and the second voltage module is not shown in a.

[0151] The first voltage module 21 is connected to the gate of the eighth transistor H3 and the gate of the ninth transistor L4 respectively, the source of the eighth transistor H3 is connected to the second voltage module, the drain of the eighth transistor H3 is connected to the source of the ninth transistor L4, and the drain of the ninth transistor L4 is grounded. The source of the ninth transistor L4 is connected to the gate of the second transistor L2 and the gate of the third transistor L3 respectively.

[0152] In some embodiments, Figure 3 The ternary logic gate circuit shown in a in can be called a self-incrementing logic gate circuit, or a first ternary logic gate circuit. The self-incrementing logic gate circuit can realize that the second logic value is equal to the first logic value plus 1. Among them, if the first voltage indicates that the first logic value is 0, the ternary logic gate circuit outputs the second logic value as 1. If the first voltage indicates that the first logic value is 1, the ternary logic gate circuit outputs the second logic value as 2. If the first voltage indicates that the first logic value is 2, the ternary logic gate circuit outputs the second logic value as 0.

[0153] In some embodiments, the self-increment logic gate circuit can be simplified as follows: Figure 3 In the more complex ternary logic circuits (such as summation circuits and half-addition circuits) provided in the following embodiments, c can be used. Figure 3 The simplified schematic diagram shown in c in Figure 1 represents a self-incrementing logic gate circuit.

[0154] In some embodiments, the fifth voltage may be 0.9V-1.8V, or even a value greater than 1.8V.

[0155] In some embodiments, the first threshold voltage may be set to 0.2 V-0.3 V, the third threshold voltage may be set to 0.4 V, and the second threshold voltage may be set to 0.6 V-0.7 V. In some embodiments, the sum of the first threshold voltage and the second threshold voltage may be less than the fifth voltage.

[0156] Combine the following Figure 3 , introduces the principle that the second logic value is equal to the first logic value plus 1. In the following example, V DD is 1V, V GND Take 0V as an example for explanation.

[0157] First, when the first voltage is equal to V GND When , the first voltage represents a first logic value of 0.

[0158] For the first transistor L1, the gate voltage of the first transistor L1 is V GND , the voltage at the source of the first transistor L1 is V DD , the voltage difference between the gate and source of the first transistor L1 is V GND -V DD (eg, -1V), and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 (eg, 1V) is greater than the first threshold voltage of the first transistor L1, so the first transistor L1 is turned on.

[0159] When the first transistor L1 is turned on, the voltage at the source of the second transistor L2 is equal to V DD , the first voltage (V GND ) through NTI, a third voltage V can be output DD , so the gate voltage of the second transistor L2 is V DD The voltage difference between the gate and the source of the second transistor L2 is 0V, and because the second transistor L2 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the second transistor L2 is less than the first threshold voltage of the second transistor L2, so the second transistor L2 is turned off.

[0160] Similarly, for the third transistor L3, the first voltage (V GND ) through NTI, a third voltage V can be output DD , the gate voltage of the third transistor L3 is V DD The drain of the third transistor L3 is grounded, and the voltage difference between the gate and drain of the third transistor L3 is V DD (eg, 1V), and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and the drain of the third transistor L3 (eg, 1V) is greater than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned on.

[0161] When the third transistor L3 is turned on, the voltage at the source of the sixth transistor M1 is equal to V DD , because the gate of the sixth transistor M1 is grounded, the voltage difference between the gate and the source of the sixth transistor M1 is V GND -V DD(eg, -1V), and because the sixth transistor M1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the sixth transistor M1 (eg, 1V) is greater than the third threshold voltage of the sixth transistor M1, and thus the sixth transistor M1 is turned on.

[0162] Similarly, for the fourth transistor H1, the gate voltage of the fourth transistor H1 is V GND , the voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and source of the fourth transistor H1 is V GND -V DD (eg, -1V), and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 (eg, 1V) is greater than the second threshold voltage of the fourth transistor H1, so the fourth transistor H1 is turned on.

[0163] The voltage at the source of the fifth transistor H2 is equal to V GND , because the gate voltage of the fifth transistor H2 is V GND Therefore, the voltage difference between the gate and the source of the fifth transistor H2 is 0, and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 is less than the second threshold voltage of the fifth transistor H2, so the fifth transistor H2 is turned off.

[0164] When the fourth transistor H1 is turned on, the voltage at the source of the seventh transistor M2 is equal to V GND , because the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , the voltage difference between the gate and source of the seventh transistor M2 is V DD -V GND (eg 1V), and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 is greater than the third threshold voltage of the seventh transistor M2, so the seventh transistor M2 is turned on.

[0165] When the sixth transistor M1 and the seventh transistor M2 are turned on, a second voltage The second voltage represents a second logic value 1. Specifically, when the sixth transistor M1 and the seventh transistor M2 are both turned on, the voltage output by the ternary logic gate circuit is equivalent to the voltage divided by the series resistor of the sixth transistor M1 and the seventh transistor M2, that is, the voltage output by the ternary logic gate circuit is V out =R M2 / (R M1 +R M2 )×V DD , at this time R M1 and R M2 are almost equal, so the ternary logic gate circuit outputs Among them, R M1 is the resistance of the sixth transistor M1, R M2 is the resistance of the seventh transistor M2.

[0166] In summary, when the first voltage is equal to V GND When , the first voltage represents the first logic value 0, the first transistor L1 in the ternary logic gate circuit is turned on, the second transistor L2 is turned off, the third transistor L3 is turned on, the fourth transistor H1 is turned on, the fifth transistor H2 is turned off, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on. The first group of transistors (the first transistor L1, the second transistor L2, and the third transistor L3) can output V to the third group of transistors (for example, the sixth transistor M1). DD , V DD In addition, the second group of transistors (the fourth transistor H1 and the fifth transistor H2) can output V to the third group of transistors (eg, the seventh transistor M2). GND , V GND Indicates a logic value of 0. Accordingly, the first group of transistors and the second group of transistors are regarded as a first processing unit, and the first processing unit can output a fourth voltage indicating a fourth logic value, and the fourth logic value includes 0 and 2.

[0167] Second, when the first voltage is equal to When , the first voltage represents a first logic value 1.

[0168] For the first transistor L1, the voltage of the gate of the first transistor L1 is The voltage at the source of the first transistor L1 is V DD , the voltage difference between the gate and source of the first transistor L1 is (eg, -0.5V), and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 (eg, 0.5V) is greater than the first threshold voltage of the first transistor L1, and the first transistor L1 is turned on.

[0169] When the first transistor L1 is turned on, the voltage at the source of the second transistor L2 is equal to V DD , the first voltage After NTI, the third voltage V GND , so the gate voltage of the second transistor L2 is V GND The voltage difference between the gate and source of the second transistor L2 is V GND -V DD (eg -1V), and because the second transistor L2 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the second transistor L2 (eg 1V) is greater than the first threshold voltage of the second transistor L2, so the second transistor L2 is turned on.

[0170] For the third transistor L3, the first voltage After NTI, the third voltage V can be output GND , the gate voltage of the third transistor L3 is V GND The drain of the third transistor L3 is grounded, the voltage difference between the gate and the drain of the third transistor L3 is 0V, and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and the drain of the third transistor L3 is less than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned off.

[0171] When the second transistor L2 is turned on, the voltage at the source of the sixth transistor M1 is equal to V DD , because the gate of the sixth transistor M1 is grounded, the voltage difference between the gate and the source of the sixth transistor M1 is 0-V DD (eg, -1V), and because the sixth transistor M1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the sixth transistor M1 (eg, 1V) is greater than the third threshold voltage of the sixth transistor M1, and thus the sixth transistor M1 is turned on.

[0172] Similarly, for the fourth transistor H1, the voltage of the gate of the fourth transistor H1 is The voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and source of the fourth transistor H1 is (e.g. -0.5V), and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 (e.g. 0.5V) is less than the second threshold voltage of the fourth transistor H1 (e.g. 0.6V-0.7V), so the fourth transistor H1 is turned off.

[0173] Similarly, the voltage at the drain of the fifth transistor H2 is equal to V GND , because the gate voltage of the fifth transistor H2 is Therefore, the voltage difference between the gate and drain of the fifth transistor H2 is (eg, 0.5V), and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 (eg, 0.5V) is less than the second threshold voltage of the fifth transistor H2 (eg, 0.6V-0.7V), and thus the fifth transistor H2 is turned off.

[0174] When the fourth transistor H2 and the fifth transistor H2 are both turned off, the voltage of the source of the seventh transistor M2 is equal to 0V. Since the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , the voltage difference between the gate and source of the seventh transistor M2 is V DD(eg 1V), and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 is greater than the third threshold voltage of the seventh transistor M2, so the seventh transistor M2 is turned on.

[0175] According to the same analysis idea, when the sixth transistor M1 and the seventh transistor M2 are turned on, the second voltage V DD , the second voltage represents a second logic value 2.

[0176] In summary, when the first voltage is equal to When , the first voltage represents the first logic value 1, the first transistor L1 in the ternary logic gate circuit is turned on, the second transistor L2 is turned on, the third transistor L3 is turned off, the fourth transistor H1 is turned off, the fifth transistor H2 is turned off, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on. The first group of transistors (the first transistor L1, the second transistor L2, and the third transistor L3) can output V to the third group of transistors (for example, the sixth transistor M1). DD , V DD In addition, the second group of transistors (the fourth transistor H1 and the fifth transistor H2) can output V to the third group of transistors (eg, the seventh transistor M2). GND , V GND Indicates a logic value of 0. Accordingly, the first group of transistors and the second group of transistors are regarded as a first processing unit, and the first processing unit can output a fourth voltage indicating a fourth logic value, and the fourth logic value includes 0 and 2.

[0177] Third, when the first voltage is equal to V DD When , the first voltage represents a first logic value of 2.

[0178] For the first transistor L1, the gate voltage of the first transistor L1 is V DD , the voltage at the source of the first transistor L1 is V DD , the voltage difference between the gate and the source of the first transistor L1 is 0, and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 is less than the first threshold voltage of the first transistor L1, and the first transistor L1 is turned off.

[0179] For the third transistor L3, the first voltage (V DD ) through NTI, a third voltage V can be output GND , the gate voltage of the third transistor L3 is V GNDThe drain of the third transistor L3 is grounded, the voltage difference between the gate and source of the third transistor L3 is 0, and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and source of the third transistor L3 is less than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned off.

[0180] For the second transistor L2, when the first transistor L1 and the third transistor L3 are both turned off, the second transistor L2 has no effect on the ternary logic gate circuit. At this time, the voltage output by the ternary logic gate circuit depends on the fifth transistor H2 and the seventh transistor M2. GND Output, realizing the function of adding 1 to the first logic value.

[0181] For the fourth transistor H1, the voltage of the gate of the fourth transistor H1 is V DD , the voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and the source of the fourth transistor H1 is 0V, and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 is less than the second threshold voltage of the fourth transistor H1, so the fourth transistor H1 is turned off.

[0182] The voltage at the drain of the fifth transistor H2 is equal to V GND , the gate voltage of the fifth transistor H2 is V DD , so the voltage difference between the gate and source of the fifth transistor H2 is V DD -V GND (eg, 1V), and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 is greater than the second threshold voltage of the fifth transistor H2, and thus the fifth transistor H2 is turned on.

[0183] When the fifth transistor H2 is turned on, the voltage at the source of the seventh transistor M2 is equal to V GND , because the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , the voltage difference between the gate and source of the seventh transistor M2 is V DD (eg 1V), and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 is greater than the third threshold voltage of the seventh transistor M2, so the seventh transistor M2 is turned on.

[0184] According to the same analysis idea, when the sixth transistor M1 and the seventh transistor M2 are turned on, the second voltage V GND, the second voltage represents the second logic value 0. Specifically, because the first transistor L1 and the third transistor L3 are turned off, the second transistor L2 and the sixth transistor M1 are isolated from the circuit and have no effect on the ternary logic gate circuit. At this time, the output of the ternary logic gate circuit depends on H2 and M2. GND Output, realizing the function of adding 1 to the first logic value.

[0185] In summary, when the first voltage is equal to V DD When , the first voltage represents the first logic value 2, the first transistor L1 in the ternary logic gate circuit is turned off, the second transistor L2 is turned on, the third transistor L3 is turned off, the fourth transistor H1 is turned off, the fifth transistor H2 is turned on, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on. The first group of transistors (the first transistor L1, the second transistor L2, and the third transistor L3) can output V to the third group of transistors (for example, the sixth transistor M1). DD , V DD In addition, the second group of transistors (the fourth transistor H1 and the fifth transistor H2) can output V to the third group of transistors (eg, the seventh transistor M2). GND , V GND Indicates a logic value of 0. Accordingly, the first group of transistors and the second group of transistors are regarded as a first processing unit, and the first processing unit can output a fourth voltage indicating a fourth logic value, and the fourth logic value includes 0 and 2.

[0186] In summary, refer to Figure 3 d, when the first input voltage is V GND =0V, that is, when the first logic value is 0, the output second voltage is That is, the second logic value is 1. When the input first voltage is That is, when the first logic value is 1, the output second voltage is V DD =1V, that is, the second logic value is 2. When the input first voltage is V DD =1V, that is, when the first logic value is 2, the output second voltage is V GND =0V, that is, the second logic value is 0.

[0187] In summary, Table 1 shows that when the first voltage is V GND , and V DD When the first transistor L1, the second transistor L2, the third transistor L3, the fourth transistor H1, the fifth transistor H2, the sixth transistor M1, and the seventh transistor M2 are turned on and off.

[0188] Table 1

[0189]

[0190] Among them, ON in Table 1 means that the transistor is turned on, and OFF means that the transistor is turned off.

[0191] It should be understood that the embodiments of the present application analyze the situations in which each transistor is turned off and on at different inputs. Based on the situations in which each transistor is turned off and on, the ternary gate circuit can output different second voltages (i.e., different outputs), and the second logic value is equal to the first logic value plus 1. It should be noted that when a transistor is turned off, the adjacent transistor is isolated from the circuit and has no effect on the output of the ternary logic gate circuit. When analyzing the output of the ternary gate circuit, reference can be made to Figure 3 A specific analysis is given of the ternary logic gate circuit shown in a in FIG.

[0192] Example 2: The ternary logic gate circuit can realize the first logic value minus 1, that is, the second logic value is equal to the first logic value minus 1.

[0193] In some embodiments, the pre-processing module 221 is a positive ternary inverter (PTI). The first group of transistors includes: a first transistor L1, a second transistor L2 and a third transistor L3, the second group of transistors includes: a fourth transistor H1 and a fifth transistor H2, and the third group of transistors includes: a sixth transistor M1 and a seventh transistor M2.

[0194] In some embodiments, the first group of transistors, the second group of transistors, and the third group of transistors may be transistors of the same or different polarities, and the polarities may include N-type and P-type. In some embodiments, the first transistor L1, the fourth transistor H1, and the sixth transistor M1 are P-type transistors, and the second transistor L2, the third transistor L3, the fifth transistor H2, and the seventh transistor M2 are N-type transistors.

[0195] In some embodiments, the ternary logic gate circuit may further include a second voltage module, which may provide a fifth voltage (V DD ).

[0196] In some embodiments, the first voltage module 21 and the second voltage module may not be included in the ternary logic gate circuit, wherein the ternary logic gate circuit may receive the first voltage from the first voltage module 21 and the fifth voltage from the second voltage module.

[0197] Reference Figure 4In a, the first voltage module 21 is connected to the gate of the third transistor L3, the gate of the fourth transistor H1, and the gate of the fifth transistor H2 respectively, and PTI is connected to the gate of the first transistor L1 and the gate of the second transistor L2 respectively. The source of the first transistor L1 is connected to the second voltage module, and the drain of the first transistor L1 is connected to the source of the second transistor L2 and the source of the seventh transistor M2 respectively. The drain of the second transistor L2 is connected to the source of the third transistor L3, and the drain of the third transistor L3 is grounded. The gate of the seventh transistor M2 is connected to the second voltage module, and the drain of the seventh transistor M2 is connected to the drain of the sixth transistor M1.

[0198] The source of the fourth transistor H1 is connected to the second voltage module, the drain of the fourth transistor H1 is connected to the source of the fifth transistor H2 and the source of the sixth transistor M1 respectively, the drain of the fifth transistor H2 is grounded, and the gate of the sixth transistor M1 is grounded.

[0199] It should be understood that Figure 4 In a, GND represents grounding.

[0200] In some embodiments, the first voltage may be set equal to V DD When , the first voltage represents the first logic value 2. The first voltage can be set equal to The first voltage represents a first logic value 1. The first voltage can be set equal to V GND When , the first voltage represents a first logic value of 0.

[0201] When the first voltage is equal to V DD When the first voltage passes through PTI, the third voltage V GND , the third voltage represents a third logic value of 0. When the first voltage is equal to When the first voltage passes through PTI, the third voltage V DD , the third voltage represents a third logic value 2. When the first voltage is equal to V GND When the first voltage passes through NTI, the third voltage V DD , the third voltage represents a third logic value of 2. In summary, PTI is used to receive the first voltage and output a third voltage, and the third voltage value represents a third logic value of 0 or 2.

[0202] Reference Figure 4 In b, PTI can be formed by two transistors connected in parallel, the two transistors are the tenth transistor L5 and the eleventh transistor H4. The threshold voltage of the eleventh transistor H4 is greater than the second threshold, and the threshold voltage of the tenth transistor L5 is less than the first threshold. The tenth transistor L5 is a P-type transistor, and the eleventh transistor H4 is an N-type transistor.

[0203] The first voltage module 21 is connected to the gate of the tenth transistor L5 and the gate of the eleventh transistor H4 respectively, the source of the tenth transistor L5 is connected to the second voltage module, the drain of the tenth transistor L5 is connected to the source of the eleventh transistor H4, and the drain of the eleventh transistor H4 is grounded. The source of the eleventh transistor H4 is connected to the gate of the first transistor L1 and the gate of the second transistor L2 respectively.

[0204] In some embodiments, Figure 4 The ternary logic gate circuit shown in a in can be called a self-decrementing logic gate circuit, or a second ternary logic gate circuit, which can realize that the second logic value is equal to the first logic value minus 1. Among them, if the first voltage represents that the first logic value is 0, the ternary logic gate circuit outputs the second logic value as 2. If the first voltage represents that the first logic value is 1, the ternary logic gate circuit outputs the second logic value as 0. If the first voltage represents that the first logic value is 2, the ternary logic gate circuit outputs the second logic value as 1.

[0205] In some embodiments, the self-increment logic gate circuit can be simplified as follows: Figure 4 As shown in c, in the more complex ternary logic circuit (such as summation circuit, half-addition circuit) provided in the following embodiments, it can be used Figure 4 The simplified schematic diagram shown in b in FIG. 1 represents a self-incrementing logic gate circuit.

[0206] In some embodiments, the fifth voltage may be 0.9V-1.8V, or even a value greater than 1.8V.

[0207] In some embodiments, the first threshold voltage may be set to 0.2 V-0.3 V, the third threshold voltage may be set to 0.4 V, and the second threshold voltage may be set to 0.6 V-0.7 V. In some embodiments, the sum of the first threshold voltage and the second threshold voltage may be less than the fifth voltage.

[0208] Based on the same analytical ideas in "Part 1" to "Part 3", the following is combined with Figure 4 The self-decrementing logic gate circuit shown in a in the figure introduces the principle that the second logic value is equal to the first logic value minus 1:

[0209] Fourth, when the first voltage is equal to V GND When , the first voltage represents a first logic value of 0.

[0210] For the first transistor L1, the first voltage (V GND ) After PTI, a third voltage V DD , the gate voltage of the first transistor L1 is V DD , the voltage at the source of the first transistor L1 is V DD, the voltage difference between the gate and the source of the first transistor L1 is 0, and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 is less than the first threshold voltage of the first transistor L1, and the first transistor L1 is turned off.

[0211] For the third transistor L3, the gate voltage of the third transistor L3 is V GND , the drain of the third transistor L3 is grounded, the voltage difference between the gate and the drain of the third transistor L3 is 0, and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and the drain of the third transistor L3 is less than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned off.

[0212] When the first transistor L1 is turned on, the source voltage of the second transistor L2 is 0. For the second transistor L2, the first voltage (V GND ) After PTI, a third voltage V DD , the gate voltage of the second transistor L2 is V DD , the voltage difference between the gate and source of the second transistor L2 is V DD , and because the second transistor L2 is an N-type transistor, the voltage difference between the gate and the source of the second transistor L2 is greater than the first threshold voltage of the second transistor L2, and the second transistor L2 is turned on.

[0213] When the second transistor L2 is turned on, the voltage at the source of the seventh transistor M2 is equal to V GND , because the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 (V DD -V GND ), which is greater than the third threshold voltage of the seventh transistor M2, and the seventh transistor M2 is turned on.

[0214] Similarly, for the fourth transistor H1, the gate voltage of the fourth transistor H1 is V GND , the voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and source of the fourth transistor H1 is V GND -V DD (eg, -1V), and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 (eg, 1V) is greater than the second threshold voltage of the fourth transistor H1, so the fourth transistor H1 is turned on.

[0215] When the fourth transistor H1 is turned on, the voltage at the source of the fifth transistor H2 is equal to V GND, because the gate voltage of the fifth transistor H2 is V GND Therefore, the voltage difference between the gate and the source of the fifth transistor H2 is 0V, and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 is less than the second threshold voltage of the fifth transistor H2, so the fifth transistor H2 is turned off.

[0216] When the fourth transistor H1 is turned on, the voltage at the source of the sixth transistor M1 is equal to V DD , because the gate of the sixth transistor M1 is grounded, the voltage of the gate of the sixth transistor M1 is V GND , the voltage difference between the gate and source of the sixth transistor M1 is V DD -V GND , and because the sixth transistor M1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the sixth transistor M1 is greater than the third threshold voltage of the sixth transistor M1, so the sixth transistor M1 is turned on.

[0217] When the sixth transistor M1 and the seventh transistor M2 are turned on, the second voltage V DD , the second voltage represents a second logic value 2.

[0218] In summary, when the first voltage is equal to V GND When , the first voltage represents the first logic value 0, the first transistor L1 in the ternary logic gate circuit is turned off, the second transistor L2 is turned on, the third transistor L3 is turned off, the fourth transistor H1 is turned on, the fifth transistor H2 is turned off, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on. Among them, at this time, only the fourth transistor H1 and the sixth transistor M1 play a role in the circuit, and V DD It is transmitted to the output end, so the first input logic value is 0 and the second output logic value is 2, realizing the -1 function.

[0219] Fifth, when the first voltage is equal to When , the first voltage represents a first logic value 1.

[0220] For the first transistor L1, the first voltage After PTI, the third voltage V DD , the gate voltage of the first transistor L1 is V DD , the voltage at the source of the first transistor L1 is V DD , the voltage difference between the gate and the source of the first transistor L1 is 0, and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 is less than the first threshold voltage of the first transistor L1, and the first transistor L1 is turned off.

[0221] For the third transistor L3, the gate of the third transistor L3 is The voltage at the drain of the third transistor L3 is V GND , the voltage difference between the gate and drain of the third transistor L3 is (eg 0.5V), and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and the drain of the third transistor L3 is greater than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned on.

[0222] When the third transistor L3 is turned on, the source voltage of the second transistor L2 is 0V, and the first voltage After PTI, the third voltage V DD , the gate voltage of the second transistor L2 is V DD , the voltage difference between the gate and source of the second transistor L2 is And because the second transistor L2 is an N-type transistor, the voltage difference between the gate and the source of the second transistor L2 is greater than the first threshold voltage of the second transistor L2, and the second transistor L2 is turned on.

[0223] When the second transistor L2 is turned on, the voltage at the source of the seventh transistor M2 is equal to Because the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 is greater than the third threshold voltage of the seventh transistor M2, and the seventh transistor M2 is turned on.

[0224] Similarly, for the fourth transistor H1, the voltage of the gate of the fourth transistor H1 is The voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and source of the fourth transistor H1 is (e.g. -0.5V), and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 (e.g. 0.5V) is less than the second threshold voltage of the fourth transistor H1 (e.g. 0.6V-0.7V), so the fourth transistor H1 is turned off.

[0225] Similarly, for the fifth transistor H2, the voltage of the gate of the fifth transistor H2 is The voltage at the drain of the fifth transistor H2 is equal to V GND , the voltage difference between the gate and drain of the fifth transistor H2 is (eg, 0.5V), and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 (eg, 0.5V) is less than the second threshold voltage of the fifth transistor H2 (eg, 0.6V-0.7V), and thus the fifth transistor H2 is turned off.

[0226] When the fourth transistor H1 and the fifth transistor are both turned off, the sixth transistor M1 is isolated outside the ternary logic gate circuit and does not affect the output of the ternary logic gate circuit.

[0227] When the sixth transistor M1 and the seventh transistor M2 are turned on, the third transistor L3, the second transistor L2, and the seventh transistor M2 are in action in the ternary logic gate circuit, and the input is The output is 0V, which plays the role of turning the first logic value -1. In the embodiment of the present application, when the first voltage is When the ternary logic gate circuit can output the second voltage V GND , the second voltage represents a second logic value of 0.

[0228] In summary, when the first voltage is equal to When the first voltage represents the first logic value 1, the first transistor L1 in the ternary logic gate circuit is turned off, the second transistor L2 is turned on, the third transistor L3 is turned on, the fourth transistor H1 is turned off, the fifth transistor H2 is turned off, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on.

[0229] Sixth, when the first voltage is equal to V DD When , the first voltage represents a first logic value of 2.

[0230] For the first transistor L1, the first voltage (V DD ) After PTI, a third voltage V GND , the gate voltage of the first transistor L1 is V GND , the voltage at the source of the first transistor L1 is V DD , the voltage difference between the gate and source of the first transistor L1 is V GND -V DD (eg, -1V), and because the first transistor L1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the first transistor L1 (eg, 1V) is greater than the first threshold voltage of the first transistor L1, and the first transistor L1 is turned on.

[0231] For the third transistor L3, the gate voltage of the third transistor L3 is V DD , the drain of the third transistor L3 is grounded, and the voltage difference between the gate and the drain of the third transistor L3 is V DD , and because the third transistor L3 is an N-type transistor, the voltage difference between the gate and the source of the third transistor L3 is greater than the first threshold voltage of the third transistor L3, so the third transistor L3 is turned on.

[0232] When the first transistor L1 and the third transistor L3 are both turned on, the source voltage of the second transistor L2 is V GND, for the second transistor L2, the first voltage (V DD ) After PTI, a third voltage V GND , the gate voltage of the second transistor L2 is V GND , the voltage difference between the gate and the source of the second transistor L2 is 0V, and because the second transistor L2 is an N-type transistor, the voltage difference between the gate and the source of the second transistor L2 is less than the first threshold voltage of the second transistor L2, and the second transistor L2 is turned off.

[0233] Wherein, after the second transistor L2 is turned off, the third transistor L3 is isolated and does not affect the output of the ternary gate circuit.

[0234] When the first transistor L1 is turned on, the voltage at the source of the seventh transistor M2 is equal to V GND , because the gate of the seventh transistor M2 is connected to the second voltage module, the voltage of the gate of the seventh transistor M2 is V DD , and because the seventh transistor M2 is an N-type transistor, the voltage difference between the gate and the source of the seventh transistor M2 is greater than the third threshold voltage of the seventh transistor M2, and the seventh transistor M2 is turned on.

[0235] Similarly, for the fourth transistor H1, the gate voltage of the fourth transistor H1 is V DD , the voltage at the source of the fourth transistor H1 is V DD , the voltage difference between the gate and the source of the fourth transistor H1 is 0V, and because the fourth transistor H1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the fourth transistor H1 is less than the second threshold voltage of the fourth transistor H1, so the fourth transistor H1 is turned off.

[0236] The gate voltage of the fifth transistor H2 is V DD , the voltage at the drain of the fifth transistor H2 is equal to V GND , because the voltage difference between the gate and drain of the fifth transistor H2 is V DD -V GND (eg, 1V), and because the fifth transistor H2 is an N-type transistor, the voltage difference between the gate and the source of the fifth transistor H2 is greater than the second threshold voltage of the fifth transistor H2, and thus the fifth transistor H2 is turned on.

[0237] When the fifth transistor H3 is turned on, the voltage at the source of the sixth transistor M1 is equal to V DD , because the gate of the sixth transistor M1 is grounded, the voltage of the gate of the sixth transistor M1 is V GND , the voltage difference between the gate and source of the sixth transistor M1 is V GND -V DD(eg -1V), and because the sixth transistor M1 is a P-type transistor, the absolute value of the voltage difference between the gate and the source of the sixth transistor M1 (1V) is greater than the third threshold voltage of the sixth transistor M1, so the sixth transistor M1 is turned on.

[0238] According to the same analysis idea, when the sixth transistor M1 and the seventh transistor M2 are turned on, the second voltage The second voltage represents a second logic value 1.

[0239] In summary, when the first voltage is equal to V DD When the first voltage represents the first logic value 2, the first transistor L1 in the ternary logic gate circuit is turned on, the second transistor L2 is turned off, the third transistor L3 is turned on, the fourth transistor H1 is turned off, the fifth transistor H2 is turned on, the sixth transistor M1 is turned on, and the seventh transistor M2 is turned on.

[0240] In summary, refer to Figure 4 d, when the first input voltage is V GND =0V, that is, when the first logic value is 0, the output second voltage is V DD , that is, the second logic value is 2. When the input first voltage is That is, when the first logic value is 1, the output second voltage is V GND =0V, that is, the second logic value is 0. When the input first voltage is V DD =1V, that is, when the first logic value is 2, the output second voltage is That is, the second logic value is 1.

[0241] In summary, Table 2 shows that when the first voltage is V GND , and V DD When the first transistor L1, the second transistor L2, the third transistor L3, the fourth transistor H1, the fifth transistor H2, the sixth transistor M1, and the seventh transistor M2 are turned on and off.

[0242] Table 2

[0243]

[0244] Among them, ON in Table 2 means that the transistor is turned on, and OFF means that the transistor is turned off.

[0245] It should be understood that the embodiments of the present application analyze the situations in which each transistor is turned off and on at different inputs. Based on the situations in which each transistor is turned off and on, the ternary gate circuit can output different second voltages (i.e., different outputs), and the second logic value is equal to the first logic value minus 1. It should be noted that when a transistor is turned off, the adjacent transistor is isolated from the circuit and has no effect on the output of the ternary logic gate circuit. When analyzing the output of the ternary gate circuit, reference can be made to Figure 4 A specific analysis is given of the ternary logic gate circuit shown in a in FIG.

[0246] In summary, the embodiment of the present application can provide a self-increment logic gate circuit, which can realize the addition of 1 to the input ternary logic value. In addition, the embodiment of the present application also provides a self-decrement logic gate circuit, which can realize the subtraction of 1 from the input ternary logic value.

[0247] Based on the ternary logic gate circuit provided in the embodiment of the present application, a summing circuit is designed by using the ternary logic gate circuit in the embodiment of the present application, and the summing circuit is used to perform sum calculation on two signals. Wherein, both signals are ternary signals. In some embodiments, the summing circuit can be called a summer.

[0248] In some embodiments, the summing circuit may include: a first ternary logic gate circuit and a second ternary logic gate circuit. In the first ternary logic gate circuit, the second logic value is equal to the first logic value plus 1, and in the second ternary logic gate circuit, the second logic value is equal to the first logic value minus 1. The first ternary logic gate circuit can be understood as a self-incrementing logic gate circuit, and the second ternary logic gate circuit can be understood as a self-decrementing logic gate circuit.

[0249] Combine the following Figure 5 , introduces the summing circuit provided in the embodiment of the present application:

[0250] The first signal module is used to connect to the summing circuit, and the second signal module is used to connect to the summing circuit. The first signal module can output a first signal to the summing circuit, and the second signal module can output a second signal to the summing circuit. The first signal and the second signal are both ternary signals. The summing circuit can perform sum calculation on the first signal and the second signal and output a first summation result.

[0251] Reference Figure 5 In some embodiments, the summing circuit 50 may include: a signal processing module 51, a first ternary logic gate circuit 52, a second ternary logic gate circuit 53, a first gating tube 54, a second gating tube 55, and a third gating tube 56. In some embodiments, the gating tube HIA may be referred to as a transmission gate.

[0252] In some embodiments, summing circuit 50 may include a first signal module and a second signal module.

[0253] The signal processing module 51 is used to connect with the first signal module, and the signal processing module 51 is respectively connected with the first gate tube 54, the second gate tube 55, and the third gate tube 56. The second signal module is respectively connected with the first gate tube 54, the first ternary logic gate circuit 52, and the second ternary logic gate circuit 53. The first ternary logic gate circuit 52 is connected with the second gate tube 55, and the second ternary logic gate circuit 53 is connected with the third gate tube 56.

[0254] The second signal module is used to output a second signal. When the second signal passes through the first ternary logic gate circuit 52, the first ternary logic gate circuit 52 can add 1 to the logic value corresponding to the second signal. When the second signal passes through the second ternary logic gate circuit 53, the second ternary logic gate circuit 53 can subtract 1 from the logic value corresponding to the second signal. When the second signal does not pass through the first ternary logic gate circuit 52 and the second ternary logic gate circuit 53, the logic value corresponding to the second signal can be output.

[0255] The first signal module is used to output the first signal. The signal processing module 51 is used to turn on any gate tube according to the first signal to enable the summing circuit to output the first summation result of the first signal and the second signal.

[0256] The first signal and the second signal are both ternary signals, for example, the first signal is used to represent the fifth logic value, and the second signal is used to represent the sixth logic value. In some embodiments, the first signal module can output the first signal in the form of an output voltage or a level, and the second signal module can also output the second signal in the form of an output voltage or a level, and the description of the first voltage module outputting the first voltage can be referred to.

[0257] In some embodiments, when the signal processing module 51 turns on the first gate tube 54 according to the first signal, the first summation result is: the sum of the fifth logic value and the sixth logic value. When the signal processing module 51 turns on the second gate tube 55 according to the first signal, the first summation result is: the sum of the sixth logic value plus 1 and the fifth logic value. When the signal processing module 51 turns on the third gate tube 56 according to the first signal, the first summation result is: the sum of the sixth logic value minus 1 and the fifth logic value. In this way, the summing circuit 50 can output the first summation result of the first signal and the second signal.

[0258] In some embodiments, reference Figure 5 The signal processing module 51 may include: a first NTI 511 , a second NTI 512 , a PTI 513 , and a NOR gate 514 .

[0259] The first signal module is connected to the first end of the first NTI 511 and the first end of the PTI 513 respectively, the second end of the first NTI 511 is connected to the first selection tube 54 and the first input end of the NOR gate 514 respectively, the second end of the PTI 513 is connected to the first end of the second NTI 512, the second end of the second NTI 512 is connected to the second input end of the NOR gate 514 and the third selection tube 56 respectively, and the output end of the NOR gate 514 is connected to the second selection tube 55. In some embodiments, the first end of the NTI can be regarded as the input end of the NTI, the second end of the NTI can be regarded as the output end of the NTI, the first end of the PTI can be regarded as the input end of the PTI, and the second end of the PTI can be regarded as the output end of the PTI.

[0260] The following takes the first signal being a ternary signal A and the second signal being a ternary signal B as an example to explain how the summing circuit 50 outputs the first summation result SUM AB The process:

[0261] When the ternary signal A passes through the first NTI 511, the first NTI 511 can output the A0 signal. When the ternary signal A passes through the PTI 513 and the second NTI 512, the second NTI 512 can output the A2 signal. When the A0 signal and the A2 signal pass through the NOR gate 514, the NOR gate 514 can output the A1 signal.

[0262] The A0 signal is used to turn off or turn on the first gate tube 54. The A1 signal is used to turn off or turn on the second gate tube 55. The A2 signal is used to turn off or turn on the third gate tube 56.

[0263] In some embodiments, the gate tube is composed of two transistors with opposite polarities. Specifically, the gate tube is composed of an N-type transistor and a P-type transistor connected back to back. The back-to-back connection of the N-type transistor and the P-type transistor can be understood as: the source of the N-type transistor is connected to the drain of the P-type transistor, the drain of the N-type transistor is connected to the source of the P-type transistor, or the source of the N-type transistor is connected to the source of the P-type transistor, and the drain of the N-type transistor is connected to the drain of the P-type transistor.

[0264] Taking the ternary signal A representing the fifth logic value 2 as an example, the ternary signal A can output an A2 signal through the PTI 513 and the second NTI 512, and the A2 signal represents the logic value 2. The A2 signal can turn on the third selection tube, so that the summing circuit can output the first summation result of "the sum of the sixth logic value minus 1 and the fifth logic value".

[0265] Taking the ternary signal A representing the fifth logic value 1 as an example, the A1 signal output by the NOR gate 514 can turn on the second selection tube, so that the summing circuit can output the first summing result of "the sum of the sixth logic value plus 1 and the fifth logic value".

[0266] Taking the ternary signal A representing the fifth logic value 0 as an example, the ternary signal A can output the A0 signal through the first NTI 511, and the A0 signal represents the logic value 2. The A0 signal can turn on the first selection tube, so that the summing circuit can output the first summation result of "the sum of the fifth logic value and the sixth logic value".

[0267] An embodiment of the present application provides a summing circuit, which can perform a summing calculation on a ternary signal A and a ternary signal B and output a first summing result.

[0268] In the above summation circuit, the summation calculation of the ternary signal A and the ternary signal B can be realized, but based on the calculation principle of the ternary summation, there is a carry when the summation calculation of the ternary signal A and the ternary signal B is performed. In order to ensure the accuracy of the summation calculation, the embodiment of the present application provides a half-adder circuit based on the summation circuit. The half-adder circuit adds a carry device on the basis of the summation circuit, and can more accurately perform the summation calculation of the ternary signal A and the ternary signal B.

[0269] In some embodiments, the half-adder circuit includes the summing circuit 50 in the above embodiments. In some embodiments, the half-adder circuit may be referred to as a half adder.

[0270] In some embodiments, reference Figure 6 The half-adder circuit 60 may include: a summing circuit 50 and a first carry 61. The first signal module is used to connect to the summing circuit 50 and the first carry 61 respectively, and the second signal module is used to connect to the summing circuit 50 and the first carry 61 respectively.

[0271] The structure of the first carry 61 can be the same as that of the carry in the binary logic circuit, which can be referred to as Figure 6 In the enlarged view of the first carry 61, A n It indicates that the first signal is output to the first carry device 61 after being processed by NTI. P It indicates that the first signal is output to the first carry device 61 after being processed by PTI. n It means that the second signal is output to the first carry device 61 after being processed by NTI, B P It indicates that the second signal is output to the first carry device 61 after being processed by PTI.

[0272] The summing circuit 50 is used to output a first summation result of the first signal and the second signal. Figure 6 SUM AB In some embodiments, SUM AB It can also be called the sum of the half adder circuit 60 (sum of halfadder).

[0273] A first carry device is used to output a first carry result of summing the first signal and the second signal, Figure 6 China-Israel Carry AB In some embodiments, Carry AB It may also be referred to as the carry of half adder circuit 60 .

[0274] An embodiment of the present application provides a half-adder circuit, which, when performing a sum calculation on a first signal and a second signal, can not only output a first sum result of the first signal and the second signal, but also output a first carry result when performing the sum calculation on the first signal and the second signal, and can accurately output the sum calculation result of the first signal and the second signal.

[0275] Based on the summing circuit 50 and the half-adding circuit 60 provided in the above embodiment, the embodiment of the present application provides a full-adding circuit, which may include the half-adding circuit 60 in the above embodiment. The full-adding circuit is used to implement the summing calculation of three ternary signals. For a ternary full-adding circuit, as with binary calculation, the ternary full-adding circuit may include three input signals: such as ternary signal A, ternary signal B, and ternary signal C. The output of the ternary full-adding circuit is: the sum signal SUM ABC And the carry signal Carry ABC In some embodiments, the full-addition circuit may be referred to as a full adder.

[0276] In some embodiments, reference Figure 7 The full adder circuit 70 may include: a first-stage half adder circuit 60, a second-stage half adder circuit 71, and a second carry device 72. The second-stage half adder circuit 71 is used to connect to the third signal module.

[0277] In some embodiments, the full adder circuit 70 may include a third signal module. In some embodiments, because the first-stage half adder circuit 60 may include a first signal module and a second signal module, the full adder circuit 70 may include a first signal module, a second signal module, and a third signal module.

[0278] The structure of the first-stage half-adder circuit 60 can be referred to Figure 6As shown, the first-stage half-adder circuit 60 is used to output a first summation result (such as SUM AB ), and output the first carry result (Carry AB ).

[0279] The third signal module is used to output a third signal to the second-stage half-adder circuit 71. The third signal is a ternary signal. For example, Figure 7 In the example, the third signal is taken as the ternary signal C.

[0280] In some embodiments, the second-stage half-adder circuit 71 is used to perform a sum calculation on the first summation result and the third signal, output a second summation result, and output the second carry result to the second carry device 72. The second summation result is the result of summing the first summation result and the third signal. Figure 7 The second summation result is expressed as SUM ABC The second carry result is the carry result when the first summation result and the third signal are summed. Figure 7 The second carry result is represented as Carry ABC .

[0281] In some embodiments, the structure of the second-stage half-adder circuit 71 may be the same as that of the first-stage half-adder circuit 60, and may refer to Figure 6 shown.

[0282] In some embodiments, in the second-stage half adder, since the carry after the sum of the first signal and the second signal can only be a logic value of 0 or a logic value of 1, and a logic value of 2 will not appear, in the second-stage half adder, the calculation path only needs to perform a +0 operation (such as using a buffer) or a +1 operation (such as using a self-increment logic gate circuit), without using a self-decrement logic gate circuit.

[0283] In some embodiments, the second-stage half-adder circuit 71 may include a third ternary logic gate circuit, in which the second logic value output by the third ternary logic gate circuit is equal to the first logic value plus 1. In other words, the third ternary logic gate circuit is a self-incrementing logic gate circuit.

[0284] Reference Figure 8 The second-stage half-adder circuit 71 may include: a third ternary logic gate circuit 711, a positive buffer (PB) 712, a negative buffer (NB) 713, a fourth gate tube 714, a fifth gate tube 715, and an AND gate 716.

[0285] The third signal module is used to connect to the input end of PB 712 and the fourth gate tube 714 respectively, and the output end of PB 712 is connected to the fifth gate tube 715 and the second input end of AND gate 716 respectively. The fourth gate tube 714 is connected to the fifth gate tube 715.

[0286] The first-stage half-adder circuit 60 is connected to the input terminals of the third ternary logic gate circuit 711 and NB 713 respectively. The third ternary logic gate circuit 711 is connected to the fifth selection transistor 715 . The output terminal of NB 713 is connected to the first input terminal of the AND gate 716 .

[0287] In the embodiment of the present application, the first summation result output by the first-stage half-adder circuit 60 may be processed by the third ternary logic gate circuit 711 and then output a signal, or the first summation result output by the first-stage half-adder circuit 60 may be processed by the NB 713 and then output a signal.

[0288] Here is a brief description of the structure and function of PB 712 and NB 713:

[0289] Fig. 9 Figure a shows a structure of PB 712. Fig. 9 In a, PB 712 can be composed of two transistors, which are: a twelfth transistor L6 and a thirteenth transistor L7. The voltage threshold of the twelfth transistor L6 is less than the first threshold, and the voltage threshold of the thirteenth transistor L7 is less than the first threshold. The twelfth transistor L6 is a P-type transistor, and the thirteenth transistor L7 is an N-type transistor.

[0290] In some embodiments, the second-stage half-adder circuit 71 further includes: a third NTI. A third signal module is used to be connected to a first end of the third NTI, and a second end of the third NTI is connected to an input end of the PB 712. It can be understood that the third signal module can output a third signal, and the third signal is output to the PB 712 after being processed by the third NTI.

[0291] In PB 712, the second end of the third NTI is connected to the gate of the twelfth transistor L6 and the gate of the thirteenth transistor L7 respectively, the source of the twelfth transistor L6 is connected to the second voltage module, the drain of the twelfth transistor L6 is connected to the source of the thirteenth transistor L7, and the drain of the thirteenth transistor L7 is grounded. In addition, the source of the thirteenth transistor L7 can be connected to the second input terminals of the fifth selection tube 715 and the AND gate 716 respectively.

[0292] When the input PB 712 is a logic value of 0, the PB 712 may output a logic value of 0, when the input PB 712 is a logic value of 1, the PB 712 may output a logic value of 2, and when the input PB 712 is a logic value of 2, the PB 712 may output a logic value of 2.

[0293] Fig. 9 Figure b shows a structure of NB 713. Fig. 9 In b, NB 713 may be composed of two transistors, which are respectively a fourteenth transistor L8 and a fifteenth transistor L9. The voltage threshold of the fourteenth transistor L8 is less than the first threshold, and the voltage threshold of the fifteenth transistor L9 is less than the first threshold. The fourteenth transistor L8 is a P-type transistor, and the fifteenth transistor L9 is an N-type transistor.

[0294] In some embodiments, the second-stage half-adder circuit 71 further includes: a second PTI. A third signal module is used to be connected to a first end of the second PTI, and a second end of the second PTI is connected to an input end of the NB 713. It can be understood that the third signal module can output a third signal, and the third signal is output to the NB 713 after being processed by the PTI.

[0295] In NB 713, the second end of the second PTI is connected to the gate of the fourteenth transistor L8 and the gate of the fifteenth transistor L9 respectively, the source of the fourteenth transistor L8 is connected to the second voltage module, the drain of the fourteenth transistor L8 is connected to the source of the fifteenth transistor L9, and the drain of the fifteenth transistor L9 is grounded. In addition, the source of the fifteenth transistor L9 can be connected to the first input terminal of the AND gate 716.

[0296] When the input NB 713 is a logic value of 0, NB 713 may output a logic value of 0; when the input NB 713 is a logic value of 1, NB 713 may output a logic value of 0; and when the input NB 713 is a logic value of 2, NB 713 may output a logic value of 2.

[0297] The third signal output by the third signal module is used to turn on the fourth selection tube 714 or the fifth selection tube 715 to enable the full-adder circuit 70 to output the second summation result.

[0298] Take the first summation result as SUM AB For example, when the third signal represents a logic value of 1, the third signal outputs a logic value of 2 through PB 712, which can turn on the fifth gate tube 715, and the fifth gate tube 715 can output SUM AB +1, the second summation result SUM ABC =SUM AB +1+C, C represents the logical value represented by the ternary signal C.

[0299] Take the first summation result as SUM AB For example, when the third signal represents a logic value of 0, the third signal outputs a logic value of 0 through PB 712, the fourth gate tube 714 can be turned on, the fifth gate tube 715 is turned off, and the second summation result SUM ABC =SUM AB +C, C represents the logical value represented by the ternary signal C.

[0300] exist Figure 7 In the embodiment, the second carry device 72 is used to carry the first carry result AB and the second carry result ABC , output the third carry result Carry.

[0301] In some embodiments, the second carry 72 may have the same structure as the first carry 71 .

[0302] In some embodiments, the structure of the second carry 72 can refer to Fig.10 As shown. Fig.10 A n Indicates the first carry result Carry AB After NTI processing, it is output to the second carry device 72, A P Indicates the first carry result Carry AB After PTI processing, it is output to the second carry device 72. n Indicates the second carry result Carry ABC After NTI processing, it is output to the second carry device 72, B P Indicates the second carry result Carry ABC After PTI processing, it is output to the second carry 72. Out represents the output (Carry) of the second carry, half V DD Indicates V DD / 2.

[0303] like Fig.10 As shown, the second carry device 72 is composed of a plurality of low voltage threshold transistors of different polarities, wherein the voltage threshold of the P-type transistor may be, for example, -0.323V, and the voltage threshold of the N-type transistor may be, for example, 0.323V.

[0304] In the embodiment of the present application, a summing circuit can be designed based on a self-increasing logic gate circuit and a self-decrementing logic gate circuit, and a half-adding circuit can be designed based on the summing circuit. Based on the first-stage half-adding circuit, a full-adding circuit that can sum three ternary signals is designed, with a small number of transistors, low power consumption, and high computing efficiency.

[0305] In some embodiments, the present application also provides a multiplication circuit, which includes the summing circuit 50 in the above embodiment and the half-adding circuit 60 in the above embodiment. The summing circuit 50 and the half-adding circuit 60 provided in the embodiment of the present application are applied to a larger-scale ternary multiplication circuit, and the number of transistors in the ternary multiplication circuit is small, the power consumption is small, and the calculation efficiency is high.

[0306] Take the 2trit*2trit multiplication circuit as an example, Fig.11 A in Figure 1 shows an existing ternary multiplication circuit. Fig.11 In a, the current ternary multiplication circuit needs to use four multipliers TMul, two summing circuits, and two full adder circuits. If the summing circuit and the full adder circuit use the summing circuit and the full adder circuit in the current prior art, the number of transistors in the multiplication circuit is large and the calculation efficiency is low.

[0307] In some embodiments, Fig.11 In a, the summing circuit 50 and the full adding circuit 70 provided in the embodiment of the present application can be used, which can reduce the number of transistors in the multiplication circuit to a certain extent and improve the calculation efficiency of the multiplication circuit. It should be understood that Fig.11 In the a, Tsum (ternary Sum) represents the summation circuit, TFA (ternary full adder) represents the full adder circuit, and TMul represents the 1trit multiplier.

[0308] In some embodiments, in order to further reduce the number of transistors in the multiplication circuit, the present application embodiment can use the idea of ​​approximate multiplication calculation, which can exchange higher computing performance and lower power consumption at the cost of smaller calculation error. The basic scheme of ternary approximate calculation multiplication is as follows: Fig.12 As shown, refer to Fig.12 , it can be seen that the carry C of the 1trit ternary multiplication calculation is 1 only when both input A and input B are 2, and the carry in all other cases is 0. If this approximation scheme is used to approximate the case of input A=B=2, the carry can be ignored in all cases in the circuit.

[0309] In some embodiments, the multiplication circuit may include: a summing circuit 50, a half-adding circuit 60, a multiplier, and an approximate multiplier. In the embodiments of the present application, based on the idea of ​​approximate multiplication calculation, some multipliers in the current ternary multiplication circuit may be replaced with approximate multipliers, which can reduce the number of transistors in the multiplication circuit.

[0310] The multiplier is used to output a first multiplication result. The approximate multiplier is used to output a second multiplication result, which can be understood as a multiplication result obtained by approximate multiplication calculation. The summation circuit and the half-addition circuit are used to output a third multiplication result according to the first multiplication result and the second multiplication result.

[0311] In order to facilitate comparison with the current ternary multiplication circuit, take the 2trit*2trit multiplication circuit as an example. Fig.11 Graph b in the figure shows the multiplication circuit provided in an embodiment of the present application.

[0312] Reference Fig.11 In b, the multiplication circuit 1100 may include: a multiplier 1101, a first approximate multiplier 1102, a second approximate multiplier 1103, a third approximate multiplier 1104, a summing circuit 60, a first half adding circuit 50, and a second half adding circuit 50.

[0313] It should be understood that the structures of the first half adder circuit 50 and the second half adder circuit 50 are the same, and reference may be made to the description of the half adder circuit 50 in the above embodiment. Fig.11 In b, the inputs include "A0 and B0", "A1 and B0", "A0 and B1", and "A1 and B1" respectively, and A0, B0, A1, and B1 are all ternary signals. In some embodiments, "A0 and B0" may be referred to as the first group of ternary signals, "A1 and B0" may be referred to as the second group of ternary signals, "A0 and B1" may be referred to as the third group of ternary signals, and "A1 and B1" may be referred to as the fourth group of ternary signals.

[0314] in addition, Fig.11 In b, Tsum (ternary Sum) represents the summing circuit 60, THA 1 (ternary half adder) represents the first half adder circuit 50, THA 2 represents the second half adder circuit 50, TMul represents the 1trit multiplier, ATMul 1 represents the first approximate multiplier, ATMul 2 represents the second approximate multiplier, and ATMul 3 represents the third approximate multiplier.

[0315] Among them, the first approximate multiplier ATMul 1 can perform multiplication calculation on the first group of ternary signals and output a first sub-multiplication result, such as P0.

[0316] The second approximate multiplier ATMul 2 can perform multiplication calculation on the second group of ternary signals and output the second sub-multiplication result to the first half adder circuit THA1. The third approximate multiplier ATMul 3 can perform multiplication calculation on the third group of ternary signals and output the third sub-multiplication result to the first half adder circuit THA1. The first half adder circuit THA1 can output a fourth sub-multiplication result P1 according to the second sub-multiplication result and the third sub-multiplication result, and output a fifth sub-multiplication result to the second half adder circuit THA2.

[0317] The multiplier TMul can perform multiplication calculation on the fourth group of ternary signals and output the first multiplication result to the second half adder circuit THA2. The second half adder circuit THA2 is used to output the sixth sub-multiplication result P2 according to the fifth sub-multiplication result and the first multiplication result, and output the seventh sub-multiplication result to the summing circuit Tsum.

[0318] The summing circuit Tsum is used to output an eighth sub-multiplication result P2 according to the first multiplication result and the seventh sub-multiplication result.

[0319] Among them, for the third multiplication result output by the summing circuit and the half-adding circuit, the third multiplication result may include: a first sub-multiplication result, a fourth sub-multiplication result, a sixth sub-multiplication result and an eighth sub-multiplication result.

[0320] The multiplication circuit provided in the embodiment of the present application can be applied to any scenario requiring ternary multiplication calculation.

[0321] In some embodiments, because the multiplication circuit in the embodiment of the present application is based on the idea of ​​approximate multiplication, the multiplication circuit provided by the embodiment of the present application can be used in scenarios where precise calculation is not required (such as artificial intelligence neural network algorithms). Among them, the multiplication circuit provided by the embodiment of the present application based on approximate multiplication calculation can effectively reduce the complexity of the circuit and realize new high-efficiency and low-power algorithm acceleration applications.

[0322] In some embodiments, in order to reduce the calculation error of the multiplication circuit, an additional compensation unit may be added to the multiplication circuit. Fig.13 As shown in b in FIG. 1 , the multiplication circuit may include a first compensation unit, and the first compensation unit may implement a +6 operation. Fig.13 As shown in c in FIG. , the multiplication circuit may include a second compensation unit, and the second compensation unit may implement a +9 operation. It should be understood that Fig.13 The a in the table shows Fig.11 The multiplication circuit shown in b is Fig.13 ATMul 1, ATMul2, ATMul 3, TFA 1, and TFA 2 are not marked in the Fig.11 As shown in b.

[0323] in addition, Fig.13 The relative error and absolute error of each multiplication circuit when performing multiplication calculation are marked.

[0324] In the embodiment of the present application, an additional compensation unit is added to the multiplication circuit to implement the +6 or +9 operation, which can effectively reduce the calculation error of the multiplication circuit, and its hardware cost is only the addition of a new addition module. Because the "+9" operation is equivalent to the P2 bit +1 in the ternary system, and the "+6" operation is equivalent to the P1 bit +2 in the ternary system, the first compensation unit and the second compensation unit can be implemented by a summation circuit or a full addition circuit.

[0325] In some embodiments, multiple 2trit*2trit ternary multiplication circuits may be cascaded to further expand the multiplication circuit to realize a larger-scale multiplication circuit. For example, a 6trit*6trit ternary multiplication circuit is taken as an example in the embodiments of the present application.

[0326] Reference Fig.14 For the 6trit ternary input signals A and B, we group A and B into 2 bits, and we can get A[5:4], A[3:2], A[1:0], and B[5:4], B[3:2], B[1:0] respectively. By performing multiplication operations with 2trit as the basic unit, we can get multiple groups of partial products such as P00=A[1:0]*B[1:0], P01=A[3:2]*B[1:0], P10=A[1:0]*B[3:2], etc., and then sum these partial products in a weighted manner (the summation process uses the exact calculation mode), and we can get the approximate calculation result of the 6trit*6trit ternary multiplication.

[0327] It should be understood that the 6trit*6trit ternary multiplication circuit is taken as an example in the embodiment of the present application. It can be imagined that the multiplication circuit provided in the embodiment of the present application can be applied to circuit designs of larger scale and arbitrary scale, and all belong to the protection scope of the embodiment of the present application.

[0328] For example, if A is 379 and B is 537 in decimal, then A×B=203523. If A and B are expressed in ternary, A can be expressed as 112001 and B can be expressed as 201220.

[0329] Fig.15 A in Figure 1 shows the current multiplication circuit (such as Fig.11 a) The process of calculating A×B, Fig.15 b in the figure shows a multiplication circuit provided by an embodiment of the present application (eg Fig.11 In the process of calculating A×B in b), the multiplication result obtained by the multiplication circuit provided in the embodiment of the present application multiplies A and B has a small error.

[0330] In some embodiments, the present application provides a chip, which may include any of the following: a first ternary logic gate circuit, a second ternary logic gate circuit, a summing circuit 50, a half-adding circuit 60, a full-adding circuit 70, and a multiplication circuit 1100. In some embodiments, the chip may be referred to as a first chip.

[0331] In some embodiments, the present application provides a chip, which may include at least one of the following: a summing circuit 50, a half-adding circuit 60, a full-adding circuit 70, and a multiplication circuit 1100. In some embodiments, the chip may be referred to as a second chip.

[0332] In some embodiments, an embodiment of the present application provides an electronic device, which may include a first chip or a second chip.

[0333] The electronic device in the embodiments of the present application may be a mobile phone, a portable android device (PAD tablet), a personal digital assistant (PDA), a handheld device with a wireless communication function, a computing device, a vehicle-mounted device or a wearable device, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in a smart home, etc. The form of the electronic device in the embodiments of the present application is not specifically limited.

[0334] It should be noted that the data involved in this application (including but not limited to data used for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0335] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0336] The term "plurality" in this article refers to two or more than two. The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship; in the formula, the character " / " indicates that the previous and next associated objects are in a "division" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0337] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0338] It can be understood that in the embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Claims

1. A ternary logic gate circuit, characterized in that: It includes a first voltage module and a logic gate module; The first voltage module is used to output a first voltage, where the first voltage is used to represent a first logic value, where the first logic value is any logic value in a ternary logic value; The logic gate module is used to receive the first voltage and output a second voltage, where the second voltage is used to represent a second logic value, where the second logic value is equal to the first logic value plus 1, or the second logic value is equal to the first logic value minus 1.

2. The ternary logic gate circuit according to claim 1, characterized in that: The logic gate module includes a pre-processing unit, a first processing unit, and a second processing unit; The pre-processing unit is used to receive the first voltage and output a third voltage to the first processing unit, wherein the third voltage is used to represent a third logic value, and the third logic value is 0 or 2; The first processing unit is used to receive the first voltage and the third voltage, and output a fourth voltage to the second processing unit, wherein the fourth voltage is used to represent a fourth logic value, and the fourth logic value includes 0 or 2; The second processing unit is used for receiving the fourth voltage and outputting the second voltage.

3. The ternary logic gate circuit according to claim 2, characterized in that: The first processing unit includes a first group of transistors and a second group of transistors, the second processing unit includes a third group of transistors, the threshold voltage of the transistors in the first group of transistors is a first threshold voltage, the threshold voltage of the transistors in the second group of transistors is a second threshold voltage, and the threshold voltage of the transistors in the third group of transistors is a third threshold voltage; The first threshold voltage is less than or equal to a first threshold, the third threshold voltage is greater than the first threshold and less than or equal to a second threshold, the second threshold voltage is greater than the second threshold, and the first threshold is less than the second threshold; The first voltage module is respectively connected to the preprocessing module, some transistors in the first group of transistors, and transistors in the second group of transistors; the preprocessing module is connected to the remaining transistors in the first group of transistors; and the transistors in the third group of transistors are connected to the transistors in the first group of transistors and the transistors in the second group of transistors.

4. The ternary logic gate circuit according to claim 3, characterized in that: The first group of transistors includes: a first transistor, a second transistor and a third transistor, the second group of transistors includes: a fourth transistor and a fifth transistor, and the third group of transistors includes: a sixth transistor and a seventh transistor.

5. The ternary logic gate circuit according to claim 4, characterized in that: The preprocessing module is a negative polarity three-value inverter NTI, the first transistor, the second transistor, the fourth transistor, and the sixth transistor are P-type transistors, and the third transistor, the fifth transistor, and the seventh transistor are N-type transistors; The first voltage module is connected to the gate of the first transistor, the gate of the fourth transistor, and the gate of the fifth transistor respectively, and the NTI is connected to the gate of the second transistor and the gate of the third transistor respectively; The source of the first transistor is connected to the second voltage module, the drain of the first transistor is connected to the source of the second transistor, the drain of the second transistor is connected to the source of the third transistor and the source of the sixth transistor respectively, the drain of the third transistor is grounded, the gate of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the drain of the seventh transistor; The source of the fourth transistor is connected to the second voltage module, the drain of the fourth transistor is connected to the source of the fifth transistor and the source of the seventh transistor respectively, the drain of the fifth transistor is grounded, and the gate of the seventh transistor is connected to the second voltage module; The second voltage module is used to output a fifth voltage, and the sum of the first threshold voltage and the second threshold voltage is less than the fifth voltage; The second logic value is equal to the first logic value plus 1.

6. The ternary logic gate circuit according to claim 4, characterized in that: The preprocessing module is a positive polarity three-value inverter PTI, the first transistor, the fourth transistor, and the sixth transistor are P-type transistors, and the second transistor, the third transistor, the fifth transistor, and the seventh transistor are N-type transistors; The first voltage module is connected to the gate of the third transistor, the gate of the fourth transistor, and the gate of the fifth transistor respectively, and the PTI is connected to the gate of the first transistor and the gate of the second transistor respectively; The source of the first transistor is connected to the second voltage module, the drain of the first transistor is connected to the source of the second transistor and the source of the seventh transistor respectively, the drain of the second transistor is connected to the source of the third transistor, the drain of the third transistor is grounded, the gate of the seventh transistor is connected to the second voltage module, and the drain of the seventh transistor is connected to the drain of the sixth transistor; The source of the fourth transistor is connected to the second voltage module, the drain of the fourth transistor is connected to the source of the fifth transistor and the source of the sixth transistor respectively, the drain of the fifth transistor is grounded, and the gate of the sixth transistor is grounded; The second voltage module is used to output a fifth voltage, and the sum of the first threshold voltage and the second threshold voltage is less than the fifth voltage; The second logic value is equal to the first logic value minus 1.

7. A summing circuit, characterized in that: include: A first ternary logic gate circuit as described in any one of claims 1-5, and a second ternary logic gate circuit as described in any one of claims 1-4 or 6, wherein in the first ternary logic gate circuit, the second logic value is equal to the first logic value plus 1, and in the second ternary logic gate circuit, the second logic value is equal to the first logic value minus 1.

8. The summing circuit according to claim 7, characterized in that: Also includes: A signal processing module, a first gating tube, a second gating tube, and a third gating tube; The signal processing module is used to connect with the first signal module, and the signal processing module is connected with the first gating tube, the second gating tube, and the third gating tube respectively; The second signal module is used to be connected to the first gating tube, the first ternary logic gate circuit, and the second ternary logic gate circuit respectively, the first ternary logic gate circuit is connected to the second gating tube, and the second ternary logic gate circuit is connected to the third gating tube; The second signal module is used to output a second signal; The first signal module is used to output a first signal; The signal processing module is used to turn on any one of the gating tubes according to the first signal, so as to enable the summing circuit to output a first summation result of the first signal and the second signal.

9. The summing circuit according to claim 8, characterized in that: The first signal is used to represent a fifth logic value, and the second signal is used to represent a sixth logic value; When the first gating tube is turned on, the first summation result is: the sum of the fifth logic value and the sixth logic value; When the second gate tube is turned on, the first summation result is: the sum of the sixth logic value plus 1 and the fifth logic value; When the third gate tube is turned on, the first summation result is: the sum of the sixth logic value minus 1 and the fifth logic value.

10. The summing circuit according to claim 8 or 9, characterized in that: The signal processing module includes: a first negative polarity three-value inverter NTI, a second NTI, a positive polarity three-value inverter PTI, and a NOR gate; The first signal module is respectively connected to the first end of the first NTI and the first end of the PTI, the second end of the first NTI is respectively connected to the first selection tube and the first input end of the NOR gate, the second end of the PTI is connected to the first end of the second NTI, the second end of the second NTI is respectively connected to the second input end of the NOR gate and the third selection tube, and the output end of the NOR gate is connected to the second selection tube.

11. A half-adder circuit, characterized in that: include: A summing circuit as claimed in any one of claims 7 to 10.

12. The half-adder circuit according to claim 11, characterized in that: Also includes: First carry device; A first signal module, used to be connected to the summing circuit and the first carry device respectively; a second signal module, used to be connected to the summing circuit and the first carry device respectively; The first carry device is used to output a first carry result.

13. A full-adder circuit, characterized in that: include: The half adder circuit according to claim 11 or 12, wherein the half adder circuit is used as a first-stage half adder circuit.

14. The full-adder circuit according to claim 13, characterized in that: Also includes: A second-stage half-adder circuit and a second carry device, wherein the second-stage half-adder circuit is used to be connected to a third signal module; The first-stage half-adder circuit is used to output a first summation result to the second-stage half-adder circuit, and output a first carry result to the second carry device; The third signal module is used to output a third signal to the second-stage half-adder circuit: The second-stage half-adder circuit is used to output a second summation result according to the third signal and the first summation result, and output a second carry result to the second carry device; The second carry device is used to output a third carry result according to the first carry result and the second carry result.

15. The full-adder circuit according to claim 14, characterized in that: The second-stage half-adder circuit comprises: a third ternary logic gate circuit as claimed in any one of claims 1 to 5, in which the second logic value is equal to the first logic value plus 1.

16. The full-adder circuit according to claim 15, characterized in that: The second-stage half-adder circuit includes: a positive polarity buffer PB, a negative polarity buffer NB, a fourth gate tube, a fifth gate tube, an AND gate, and a third ternary logic gate circuit; The third signal module is used to be connected to the input end of the PB and the fourth gate tube respectively, the output end of the PB is connected to the fifth gate tube and the second input end of the AND gate respectively, and the fourth gate tube is connected to the fifth gate tube; The first-stage half-adder circuit is connected to the third ternary logic gate circuit and the input end of the NB respectively, the third ternary logic gate circuit is connected to the fifth gate tube, and the output end of the NB is connected to the first input end of the AND gate; The third signal is used to turn on the fourth gate tube or the fifth gate tube to enable the full-adder circuit to output the second summation result.

17. A multiplication circuit, characterized in that: include: The summing circuit according to any one of claims 7 to 10, and the half-adder circuit according to claim 11 or 12.

18. The multiplication circuit according to claim 17, characterized in that: Also includes: Multipliers and approximate multipliers; The multiplier is used to output a first multiplication result; The approximate multiplier is used to output the second multiplication result; The summation circuit and the half-addition circuit are used to output a third multiplication result according to the first multiplication result and the second multiplication result.

19. The multiplication circuit according to claim 18, characterized in that: The approximate multiplier includes a first approximate multiplier, a second approximate multiplier, and a third approximate multiplier, and the half-adder circuit includes a first half-adder circuit and a second half-adder circuit; The first approximate multiplier is used to output a first sub-multiplication result; The second approximate multiplier is used to output a second sub-multiplication result to the first half-adder circuit; The third approximate multiplier is used to output a third sub-multiplication result to the first half-adder circuit; The first half-adder circuit is used to output a fourth sub-multiplication result according to the second sub-multiplication result and the third sub-multiplication result, and output a fifth sub-multiplication result to the second half-adder circuit; The multiplier is further configured to output the first multiplication result to the second half-adder circuit; The second half-adder circuit is used to output a sixth sub-multiplication result according to the fifth sub-multiplication result and the first multiplication result, and output a seventh sub-multiplication result to the summing circuit; The summing circuit is used to output an eighth sub-multiplication result according to the first multiplication result and the seventh sub-multiplication result; The third multiplication result includes: the first sub-multiplication result, the fourth sub-multiplication result, the sixth sub-multiplication result and the eighth sub-multiplication result.

20. A chip, characterized in that: include: A circuit as claimed in any one of claims 1 to 19.

21. A chip, characterized in that: include: At least one of the following: A summation circuit as claimed in any one of claims 7 to 10, a half-adder circuit as claimed in claim 11 or 12, a full-adder circuit as claimed in any one of claims 13 to 16, a multiplication circuit as claimed in any one of claims 17 to 19.

22. An electronic device, characterized in that: include: A chip as claimed in claim 20 or 21.

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