Large-scale photon chip packaging structure, packaging test method and system

Abstract

The invention relates to the technical field of semiconductor device packaging, in particular to a packaging structure, a packaging test method and a packaging test system of a large-scale photon chip. The upper surface of the substrate is connected with a chip layer through a first bonding structure, the chip layer comprises a plurality of optical chips, adjacent first and second side edges of the optical chips are relatively parallel to corresponding side edges of the other two adjacent optical chips, and a first gluing area is formed by filling a gluing material between the two oppositely arranged side edges; the outward side edge of the photon chip is bonded with a bonding material which extends to form a second bonding area, and the silicon adapter plate is arranged corresponding to the first connecting area of the optical chip; and a first wiring layer is arranged between the lower surface of the silicon adapter plate and the cementing layer. The splicing structure provided by the invention can reduce the preparation difficulty of large-scale optical chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a packaging structure, a packaging test method and a system for a large-scale photonic chip. Background Art

[0002] The technology of large-scale integrated circuits has been very mature and has reached the nanometer level. The integration of its mainstream technology CMOS doubles approximately every 18 months according to Moore's Law. The increase in integration makes the chip more and more powerful. However, with the continuous reduction of device feature size, especially after entering the nanometer scale, this one-dimensional development model of integrated circuits faces a series of physical limitation challenges. These challenges come from the physical limits of basic physical laws, as well as from the physical limitations of materials, technologies, devices and systems. Moreover, the emergence of new information technologies represented by "cloud computing", "Internet of Things" and "big data" has made the demand for high-speed, low-power data processing and transmission technologies more urgent. The explosive growth of communication capacity has promoted the development of photonic technology. It is generally believed that silicon-based photonic devices and integration technologies based on silicon materials have outstanding advantages such as low power consumption, high speed and compact structure, and will become the key technology to solve the bottlenecks of power consumption, speed and volume faced by information networks. Among them, light has dominated network transmission with its unique speed, bandwidth and low power consumption advantages, that is, photonic chips play a vital role in the preparation process of semiconductor devices.

[0003] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively, and lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging. This also places increasing demands on the scale of photonic chips.

[0004] However, due to the maximum exposure area of ​​the ultraviolet lithography equipment in the foundry, the design size of silicon-based photonic chips is generally not larger than 2-3cm, which limits the larger-scale integration of silicon-based photonic devices. For example, in the actual preparation process, once the design size of the photonic chip is larger, multiple lithography equipment needs to be spliced ​​to complete the lithography of large-scale photonic chips.

[0005] Patent application CN115629445A also discloses a write field splicing structure and process for large-scale silicon-based photonic chip design. The processing scheme adopted is to process a certain area with the largest exposure area first during wafer processing, so as to manufacture a certain part of the chip first, and then process another part next to the chip, so as to realize the processing of large chips. In other words, it is essentially to process a large chip by dividing it into multiple exposures, and this multiple exposure leads to a long production cycle, high precision requirements for processing alignment, etc., and relatively low yield (failure of any part will lead to failure of the entire large chip).

[0006] In summary, for large-scale photonic chips, traditional lithography solutions are not only more difficult to process, but also have very limited maximum processing size. Summary of the invention

[0007] The object of the present invention is to provide a packaging structure, packaging test method and system for a large-scale photonic chip, which can partially solve or alleviate the above-mentioned deficiencies in the prior art and reduce the processing difficulty in the photolithography process.

[0008] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: A first aspect of the present invention is to provide a packaging structure of a large-scale photonic chip, comprising: substrate; The upper surface of the substrate is connected to a chip layer via a first bonding structure, and the chip layer includes: at least one group of photonic chips; wherein the group of photonic chips includes: A first photonic chip, a second photonic chip, a third photonic chip and a fourth photonic chip are arranged adjacent to each other, and the adjacent first side edge and the second side edge of any one of the photonic chips are arranged parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first bonding material to form a first bonding area; The side edge of the photonic chip facing outward is bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edge to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer that wraps the photonic chip, wherein the photonic chip is provided with a first connection area and a second connection area, and the first connection area is provided with a plurality of first conductive bumps, and the second connection area is provided with a photosensitive area, and the optical fiber array is coupled with the photosensitive area; A silicon adapter plate, wherein the silicon adapter plate is arranged corresponding to the first connection area; an optical fiber array, the optical fiber array being arranged corresponding to the second connection area; Wherein, a first wiring layer is arranged on the lower surface of the silicon adapter board, between the optical fiber array and the adhesive layer, a plurality of first wiring channels are arranged on the first wiring layer, and a plurality of lead-out channels are arranged on the adhesive layer corresponding to the first conductive bumps, respectively, and the first wiring channels are used to lead out the first conductive bumps through the lead-out channels and connect them to the silicon adapter board; At least one type of electronic chip is disposed on the upper surface of the silicon adapter plate via a second bonding structure, wherein the type of electronic chip is indirectly communicatively connected with the group of photonic chips via the silicon adapter plate.

[0009] In some embodiments, the first width is in the range of 0.1 mm-0.5 mm.

[0010] In some embodiments, a second wiring layer is disposed on the second surface of the adhesive layer, a plurality of second wiring channels are disposed on the second wiring layer, and the second wiring channels are connected to the first bonding structure.

[0011] In some embodiments, at least one second-class electronic chip is further disposed on the silicon adapter board, and the second-class electronic chip includes: a high-bandwidth memory chip, and the second-class electronic chip is disposed on the side of the first-class electronic chip.

[0012] In some embodiments, the optical fiber array is vertically coupled to the photosensitive area.

[0013] The present invention also provides a packaging and testing method for a large-scale photonic chip, comprising the steps of: S100, providing a splicing layer, the splicing layer comprising: a first photonic chip, a second photonic chip, a third photonic chip and a fourth photonic chip arranged adjacent to each other, and the adjacent first side edge and the second side edge of any one of the photonic chips are arranged in parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first adhesive material to form a first adhesive area; the outwardly arranged side edge of the photonic chip is bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edge to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer that wraps the photonic chip; S101, obtaining a deformation curve L of the splicing layer, wherein the deformation curve L is used to reflect the degree of bending deformation of the splicing layer on a plane; S102, obtaining at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L; at least one of the first curve segments L1 can respectively cover at least a portion of two adjacent photonic chips, and the lengths covered by the first curve segments L1 on the two adjacent photonic chips are the same or similar; at least one of the second curve segments L2 can cover one photonic chip and a second bonding area adjacent to the corresponding photonic chip; S103, determining whether the deformation curve L satisfies a preset first splicing rule. If so, it is considered that the splicing layer satisfies a first splicing requirement; wherein the first splicing rule requires that a first curvature of at least one of the first curve segments L1 is less than a preset first curvature threshold, and a second curvature of at least one of the second curve segments L2 is less than a preset second curvature threshold.

[0014] In some embodiments, the first splicing rule further requires that a first difference between the first curvature and the second curvature is less than a set first curvature difference threshold.

[0015] In some embodiments, the first splicing rule further requires that a second difference between at least two second curvatures corresponding to at least two of the second curve segments L2 is less than a set second curvature difference threshold; and the corresponding at least two second curve segments L2 are located at symmetrical positions on the splicing layer.

[0016] In some embodiments, when there are multiple first curve segments L1, the first curvature of the multiple first curve segments L1 is the average curvature of the multiple first curve segments; and / or, when there are multiple second curve segments L2, the second curvature of the multiple second curve segments L2 is the average curvature of the multiple second curve segments L2.

[0017] The present invention also provides a packaging and testing system for large-scale photonic chips, the packaging and testing system is used to test a splicing layer, wherein the splicing layer includes: a first photonic chip, a second photonic chip, a third photonic chip and a fourth photonic chip arranged adjacent to each other, and the adjacent first side edge and the second side edge of any one of the photonic chips are arranged in parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first adhesive material to form a first adhesive area; the side edge of the photonic chip arranged outward is bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edge to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer for wrapping the photonic chip; correspondingly, the packaging and testing system includes: A first acquisition module, used for acquiring a deformation curve L of the splicing layer, wherein the deformation curve L is used for reflecting the degree of bending deformation of the splicing layer on a plane; A second acquisition module is used to acquire at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L; and at least one of the first curve segments L1 can respectively cover at least a portion of two adjacent photonic chips, and the lengths covered by the first curve segments on the two adjacent photonic chips are the same or similar; and at least one of the second curve segments L2 can cover one photonic chip and a second bonding area adjacent to the corresponding photonic chip; The splicing rule judgment module is used to judge whether the deformation curve L satisfies a preset first splicing rule. If so, it is considered that the splicing layer meets the first splicing requirement; wherein, the first splicing rule requires that the first curvature of at least one of the first curve segments L1 is less than a preset first curvature threshold, and the second curvature of at least one of the second curve segments L2 is less than a preset second curvature threshold.

[0018] Beneficial technical effects: Different from the splicing route of traditional lithography equipment, the present invention chooses to start from the packaging end and proposes a stress-balanced splicing packaging process. Specifically, the present invention proposes a multi-chip packaging process combining a splicing layer and a silicon adapter plate. Among them, multiple photonic chips are arranged horizontally with a certain gap, and the photonic chip is provided with a connection partition division to realize the overall connection of a large silicon adapter plate in each adjacent area of ​​multiple photonic chips, so that on the one hand, the signals between multiple photonic chips can be collected and summarized later; at the same time, the indirect connection between the splicing layer and various types of electronic chips (such as ASCI chips, HBM chips) is realized through the silicon adapter plate, which can improve the splicing strength of the splicing layer to a certain extent, and on the other hand, it can also balance the stress applied by various types of electronic chips on the splicing layer to improve the balance of stress in various places in the splicing layer. In addition, by evenly and symmetrically coupling and setting an optical fiber array on the edge of the splicing layer (i.e., the back of the photonic chip), the stress problem of the splicing layer at the edge (such as bending due to stress at the edge) can be further alleviated.

[0019] Furthermore, the present invention also proposes a testing method for the splicing process of the splicing layer. Specifically, the method is through the dispersed arrangement of multiple curve segments on the splicing layer, and different curve segments can be arranged with emphasis on different areas (specifically, they can cover the connection between different photonic chips and the bonding area). Then, through the overall curvature evaluation of the dispersed multiple curve segments, and the evaluation between the curvature differences, the stress balance of the splicing layer formed by multiple chips can be comprehensively evaluated. In particular, through the preferred distribution design of the position of the curve segments, such as the first curve segment and the second curve segment can achieve coverage of the edge and center areas, as well as coverage of the chip and the bonding area (i.e., coverage of the double area), the stress balance of the splicing layer can be effectively evaluated through the collaborative analysis of local data. Finally, it is ensured that the currently obtained splicing layer can further meet the processing requirements of subsequent packaging operations.

[0020] In other words, the present invention preferably conducts a collaborative evaluation of the stress balance of the splicing layer by two aspects, namely, the degree of local bending at multiple points of the splicing layer and the difference between the degree of bending deformation of each chip. When the first splicing rule is met, it is considered that the degree of bending deformation of the splicing layer is relatively small, the strength is relatively reliable, and the degree of deformation of each chip is relatively uniform (that is, the overall surface flatness of the splicing layer is relatively uniform), and it also has a certain fault tolerance for subsequent packaging processes. For example, when the silicon adapter plate or substrate continues to be bonded to the splicing layer, a certain interaction force will be generated between its different bonding positions, and the present invention can ensure the overall flatness of the surface of the splicing layer to a certain extent by differentially evaluating the degree of deformation of each chip, thereby alleviating or reducing the difference in interaction force at different bonding positions to a certain extent, thereby reducing defects such as cracks that may be caused by uneven force during the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0022] Figure 1 is a schematic structural diagram of an exemplary packaging structure of the present invention; Figure 2 Schematic diagram of the cross-sectional structure of a packaging structure in two directions in an exemplary embodiment of the present invention; Figure 3is a schematic structural diagram of a chip layer in an exemplary embodiment of the present invention; Figure 4 A schematic diagram of the distribution of test points on a chip layer in an exemplary embodiment of the present invention; Figure 5 It is a schematic diagram of collecting bending deformation values ​​in an exemplary embodiment of the present invention; Figure 6 A schematic diagram of the process steps of a testing method in an exemplary embodiment of the present invention; Figure 7 It is a schematic diagram of the module structure of a test system in an exemplary embodiment of the present invention.

[0023] Summary of reference numerals: Chip layer 01, first photonic chip 011, second photonic chip 012, third photonic chip 013, fourth photonic chip 014, first connection area 11, second connection area 12, first side 01a, second side 01b, bonding layer 02, first bonding area 021, second bonding area 022, type II electronic chip 03, substrate 04, silicon adapter board 05, optical fiber array 06, type I electronic chip 07, first wiring layer 08, second wiring layer 09. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0026] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0027] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0030] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0031] In this specification, some embodiments may be disclosed in a format of being in a range. It should be understood that this description of "being in a range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within this range, such as 1, 2, 3, 4, 5 and 6. Regardless of the breadth of the range, the above rules apply.

[0032] In this article, "approximately parallel" means that the angle between two lines / planes is approximately zero, such as approximately 1°, approximately 2°, approximately 3°, etc. For example, in the actual packaging process, due to process precision, there may be a certain deviation between the two adjacent sides of two photonic chips, so that the two sides are not absolutely parallel, but the angle formed is very small and falls within the tolerable error range, so the two are considered to be approximately parallel and meet the packaging requirements.

[0033] As used herein, a "layer" refers to a portion of a material that includes an area having a certain thickness. A layer may extend over the entire upper or lower structure, or may have an extent that is less than the extent of the upper or lower structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, and its thickness may be less than the thickness of the continuous structure. For example, a layer may be located between the upper or lower surface of a continuous structure, or between any pair of horizontal planes therebetween. A layer may have one or more layers horizontally, vertically, and / or above, over, and / or below it. A layer may include multiple layers.

[0034] In this article, "bonding material" refers to a material that can be connected to a photonic chip (or optical chip, or optical computing chip) to indirectly connect multiple photonic chips into a large photonic chip (or large chip). In this article, bonding material can also be referred to as connecting material or splicing material.

[0035] Herein, “covered length” refers to the length of a curve segment (or curve), and specifically, refers to the length of the area of ​​the surface of the splicing layer that the curve segment is used to react to (or simulate).

[0036] The "scale" of a photonic chip in this article refers to the size of the photon computing array on the mask plate under a conventional wafer area (such as an 8-inch or 12-inch wafer), usually expressed in the form of X1*X2, where X1 represents the number of rows in the photon computing array and X2 represents the number of columns in the photon computing array. Generally, a photon computing array in a photonic chip (or optical chip, optical computing chip) greater than or equal to 64*64 is considered large-scale, or called a high-dimensional matrix optical chip.

[0037] In traditional processing technology, due to the limitation of the exposure area of ​​lithography equipment, if a high-dimensional matrix optical chip is to be prepared, it is usually necessary to splice the lithography equipment to achieve a larger exposure area and obtain a high-dimensional matrix optical chip. However, the processing difficulty of this splicing method of lithography equipment is very high, and the maximum processing size is still limited by the maximum exposure area of ​​the lithography equipment, which makes it difficult to cope with the requirements for higher-dimensional matrices of photonic chips under the explosive growth of global data traffic.

[0038] In this regard, the present invention starts from the packaging end and proposes a stress-balanced splicing packaging process, so that multiple small-scale photonic chips can be spliced ​​into a large-scale photonic chip in the packaging structure for use, and the large chip obtained by splicing has the characteristics of stress balance, which can meet the subsequent further packaging requirements. This stress-balanced splicing packaging process can reduce the requirements of photonic devices with high-dimensional matrix requirements for preparation processes such as lithography.

[0039] Embodiment 1 See also Figure 1As shown, the present invention provides a packaging structure of a large-scale photonic chip, comprising: substrate04; The upper surface of the substrate 04 is connected to a chip layer 01 via a first bonding structure, and the chip layer 01 includes: at least one group of photonic chips; Among them, a group of photonic chips includes: multiple photonic chips, and the multiple photonic chips are spliced ​​using a stress-balanced splicing solution to form a stably connected chip layer and adhesive layer.

[0040] Specifically, the group of photonic chips includes: The first photonic chip 011, the second photonic chip 012, the third photonic chip 013 and the fourth photonic chip 014 are arranged adjacent to each other, and the adjacent first side edge 01a and the second side edge 01b (such as Figure 3 The side edges of the two adjacent photonic chips are arranged in parallel or approximately in parallel with the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two side edges that are arranged opposite to each other (i.e., the two photonic chips are arranged adjacent to each other, or are arranged parallel or approximately in parallel), and the gap space is filled with a first bonding material to form a first bonding area 021; wherein the multiple photonic chips are arranged adjacent to each other in a symmetrical relationship; The outwardly disposed side edge of the photonic chip is bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edge to form a second adhesive area 022 with a second width (wherein the second width may refer to the distance between the outwardly disposed side edge of the photonic chip and the outer edge of the second adhesive area), the first adhesive area and the second adhesive area are connected to form an adhesive layer 02 for wrapping the photonic chip, preferably, the adhesive layer can evenly cover multiple side surfaces of the photonic chip, and a lead-out channel is reserved on the adhesive layer; For example, a photonic chip can be approximately regarded as a hexahedral structure, and its front, back, and four sides can all be covered by adhesive materials. In this article, the adhesive layer and the chip layer are also collectively referred to as: splicing layer.

[0041] The photonic chip is provided with a first connection area 11 and a second connection area 12, and the first connection area is provided with a plurality of first conductive bumps, the second connection area is provided with a photosensitive area, and the optical fiber array is coupled with the photosensitive area; A silicon adapter plate 05, wherein the silicon adapter plate 05 is arranged corresponding to the first connection area; preferably, a large silicon adapter plate is used to connect the multiple spliced ​​photonic chips as a whole; An optical fiber array 06, the optical fiber array being arranged corresponding to the second connection area; A first wiring layer 08 is provided between the lower surface of the silicon adapter plate 05 and the adhesive layer, and a first wiring layer may also be provided between the optical fiber array and the adhesive layer, a plurality of first wiring channels are provided on the first wiring layer, and a plurality of lead-out channels are provided on the adhesive layer corresponding to the first conductive bumps, respectively, and the first wiring channels are used to lead out the first conductive bumps through the lead-out channels and connect them to the silicon adapter plate 05; At least one type-one electronic chip 07 is disposed on the upper surface of the silicon adapter board 05 via a second bonding structure, wherein the type-one electronic chip 07 is communicatively connected with the group of photonic chips via the silicon adapter board.

[0042] In some embodiments, the electronic chip 07 may be an ASIC chip (Application Specific Integrated Circuit). In this document, the electronic chip is also referred to as an electric chip.

[0043] In some embodiments, at least one type II electronic chip 03 , such as a high bandwidth memory chip, ie, an HBM chip, is further disposed on the silicon adapter board, and the high bandwidth memory chip is disposed on the side of the type I electronic chip 07 .

[0044] In this embodiment, multiple photonic chips are arranged horizontally with a certain gap, and the photonic chips are divided into connection zones to realize the overall connection of a large silicon adapter board in each adjacent area of ​​the multiple photonic chips. On the one hand, the signals between the multiple photonic chips can be collected and aggregated later; at the same time, the indirect connection between the splicing layer and various types of electronic chips (such as ASCI chips, HBM chips) is realized through the silicon adapter board. On the one hand, it can improve the splicing strength of the splicing layer to a certain extent, and on the other hand, it can also balance the stress applied by various types of electronic chips on the splicing layer to improve the balance of stress in various places in the splicing layer. In addition, by evenly and symmetrically coupling and setting the optical fiber array on the edge of the splicing layer (i.e., the back of the photonic chip), the stress problem of the splicing layer at the edge (such as bending due to stress at the edge) can be further alleviated.

[0045] In summary, the stress-balanced chip distribution and connection setting proposed in this embodiment can meet the splicing requirements of large-scale photonic chips to ensure the working stability and reliability of the splicing solution.

[0046] Preferably, in some embodiments, the optical fiber array is vertically coupled to the photosensitive area.

[0047] In this embodiment, the photosensitive area (or fiber coupling port) is only set on the back side of the chip (specifically the second connection area 12), which can take into account the requirements of underfill and molding of the package, as well as the transmission of optical signals. In addition, by symmetrically setting the fiber arrays at the edges of the four photonic chips extending out of the silicon adapter plate, the edge stress problem increased during the splicing process can be alleviated to a certain extent.

[0048] For example, in some embodiments, the scale of a photonic chip is X1*X2, and correspondingly, the scale of a photonic chip (ie, a large chip) formed by splicing four photonic chips is (X1+X1)*(X2+X2).

[0049] For example, in some embodiments, for an ultra-large-scale photonic chip (such as a 128*128 photonic chip), multiple groups of photonic chips can be spliced ​​together.

[0050] For example, in some embodiments, the size of the silicon adapter plate 05 can be about 3 cm by 3 cm, and the multiple small photonic chips connected thereto can be about several millimeters by several millimeters. By reducing the processing area of ​​the photonic chip, the difficulty of the processing technology of the photonic chip can also be reduced.

[0051] In some embodiments, the first adhesive material and the second adhesive material can be one or more of the following: epoxy resin, polyethylene, polypropylene, etc.

[0052] In some embodiments, the first and second bonding areas disposed on the photonic chip may be integrally formed, and correspondingly, the first and second bonding materials may also be the same material.

[0053] In some embodiments, the first width ranges from 0.1 mm to 0.5 mm. In this embodiment, by limiting the first width, on the one hand, the splicing strength of the splicing layer can be improved (such as reducing defects of the splicing layer), and on the other hand, the wiring difficulty can be reduced.

[0054] In some embodiments, see Figure 2 As shown, a second wiring layer 09 is disposed on the second surface of the adhesive layer, a plurality of second wiring channels are disposed on the second wiring layer, and the second wiring channels are connected to the first bonding structure.

[0055] In some embodiments, the substrate may also be electrically connected to the mainboard via socket or BGA soldering.

[0056] In some embodiments, the bonding structure can be implemented by using processes such as die bonding (or die attach) and / or wire bonding.

[0057] For example, in some embodiments, the bonding structure may be a conductive structure such as a convex ball or a bump formed on the surface to be connected. Correspondingly, by applying the flip chip technology, the surface of the chip can be directly connected to the substrate or carrier through the bump.

[0058] In some embodiments, after the splicing layer is connected to the substrate, the silicon adapter board, and the electronic chip to form a multi-layer structure, the multi-layer structure can also be packaged, such as by using a molding process (i.e., a plastic encapsulation process) to further grow a third connecting material (also referred to as a third adhesive material) on the outside of the multi-layer structure to encapsulate the multi-layer structure as a whole.

[0059] In some embodiments, the third connection material may be one or more of the following: epoxy resin, polyethylene, polypropylene.

[0060] Embodiment 2 In the process of preparing the packaging structure, the splicing layer (whose structure is as follows) can be completed separately first. Figure 3 The splicing layer is then connected as a whole to the substrate, silicon adapter plate and optical fiber array respectively.

[0061] Furthermore, in order to ensure that the splicing layer has sufficient working stability during the splicing process and the subsequent packaging process, the present invention also proposes a packaging test method for the splicing layer obtained by the stress-balanced splicing packaging process.

[0062] See also Figure 6 As shown, the present invention also provides a packaging and testing method for a large-scale photonic chip, comprising the steps of: S100, provides a splicing layer (or a group of photonic chips connected by a glue layer), see Figure 3 As shown, the splicing layer includes: a chip layer and a bonding layer, wherein the chip layer includes: a first photonic chip 011, a second photonic chip 012, a third photonic chip 013 and a fourth photonic chip 014 that are adjacently arranged, and the adjacent first side edges 01a and the second side edges 01b of any one of the photonic chips are arranged in parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first bonding material to form a first bonding area; the outwardly arranged side edges of the photonic chip are bonded with a second bonding material, and the second bonding material extends in a direction away from the side edges to form a second bonding area with a second width, and the first bonding area and the second bonding area are connected to form a bonding layer that wraps the photonic chip.

[0063] S101 , obtaining a deformation curve L of the splicing layer, where the deformation curve L is used to reflect the degree of bending deformation of the splicing layer on a plane.

[0064] S102, obtaining at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L. Preferably, the first curve segment and the second curve segment cover different areas on the splicing layer.

[0065] Preferably, see Figure 4 As shown, the outer surface of the splicing layer (such as the upper surface or the lower surface) is divided into a center surface and an edge surface in sequence along the direction from the center to the outside. Correspondingly, the first curve segment L1 can be a curve corresponding to the center surface, and the second curve segment L2 can be a curve corresponding to the edge surface.

[0066] Preferably, see Figure 4 As shown, the second curve segment L2 can cover the second gluing area disposed at the edge of the photonic chip.

[0067] Preferably, the first curve segment L1 can evenly cover two adjacent photonic chips. Specifically, the first curve segment L1 can respectively cover two adjacent photonic chips 02, and the corresponding covered lengths on the two adjacent photonic chips are the same or similar.

[0068] For example, in some embodiments, "similar" means that the difference ratio between the two lengths does not exceed 5% at most, or the difference ratio does not exceed 10%. Wherein, the difference ratio = |first length-second length| / reference length, and the reference length is the first length or the second length. Wherein, the first length refers to the length covered by the first curve segment on one of the photonic chips (or the overlapping length with one photonic chip), and the second length refers to the length covered by the first curve segment on another photonic chip arranged adjacent thereto.

[0069] Preferably, the first curved line segment L1 can cover a first bonding area formed between the two photonic chips.

[0070] S103, determining whether the deformation curve L satisfies a first splicing rule. If so, it is considered that the splicing layer satisfies a first splicing requirement; wherein the first splicing rule requires that a first curvature of at least one first curve segment L1 is less than a first curvature threshold, and a second curvature of at least one second curve segment L2 is less than a second curvature threshold.

[0071] Specifically, when S103 determines that the splicing layer satisfies the first splicing rule, it is considered that the quality of the splicing layer is relatively reliable and meets the subsequent packaging requirements. In other words, if the first splicing rule is met, it can be considered that the defects of the splicing layer are relatively reduced, and the performance can be improved through limited repair (such as re-gluing) to meet the subsequent packaging requirements.

[0072] On the contrary, when the splicing layer does not meet the first splicing rule, it is preliminarily considered that the stress defect of the splicing layer is large, and it is not recommended to continue the packaging operation.

[0073] In some embodiments, when there are multiple first curve segments, correspondingly, the curvatures of the multiple first curve segments L1 may be an average value of the curvatures of the multiple first curve segments.

[0074] Likewise, in some embodiments, when there are multiple second curve segments, correspondingly, the curvatures of the multiple second curve segments L2 may be an average value of the curvatures of the multiple second curve segments.

[0075] Furthermore, in some embodiments, the first splicing rule further requires that a first difference between the first curvature and the second curvature is smaller than a set first curvature difference threshold.

[0076] Furthermore, in some embodiments, at least two second curve segments are located at symmetrical positions on the splicing layer. Correspondingly, the first splicing rule further requires that a second difference between at least two second curvatures corresponding to the at least two second curve segments (such as the difference between any two second curvatures) is less than a set second curvature difference threshold.

[0077] In this embodiment, preferably, by detecting the dispersed sampling areas (i.e., multiple curve segments) in the splicing layer, the stress balance of the splicing layer can be collaboratively evaluated by comprehensively evaluating the degree of local bending deformation at multiple points and the difference in the degree of bending deformation at different local positions. When the first splicing rule is met, it is considered that the degree of bending deformation of the splicing layer is relatively small, the strength is relatively reliable, and the degree of deformation of each chip is relatively uniform (i.e., the overall surface flatness of the splicing layer is relatively uniform), and there is a certain fault tolerance for the subsequent packaging process. For example, when the silicon adapter or substrate is continued to be bonded to the splicing layer, a certain interaction force will be generated between its different bonding positions, and the present invention can ensure the overall flatness of the surface of the splicing layer to a certain extent by differentially evaluating the degree of deformation of each chip, thereby alleviating or reducing the difference in interaction force at different bonding positions to a certain extent, thereby reducing defects such as cracks that may be caused by uneven force during the packaging process.

[0078] Preferably, for the splicing layer composed of multi-photonic chip blocks, this embodiment performs collaborative calculations on the local bending degree and degree difference of the core area, thereby performing an overall evaluation of the splicing strength of multiple photonic chips at the connection points and their own strength performance (such as at least local warping data on a chip) through the data of a finite number of dispersed curve segments, thereby ensuring the stress balance of the splicing process.

[0079] Furthermore, in some embodiments, before S103, the method further includes the steps of: It is determined whether the deformation curve L satisfies the second splicing rule. If yes, S103 is executed. If no, it is considered that the splicing strength of the splicing layer is unqualified. The second splicing rule requires that the curvature of the deformation curve L is less than a set third curvature threshold.

[0080] In this embodiment, it is preferred that the core local area of ​​the deformation curve L will be re-verified only after it meets the second splicing rule. Therefore, by evaluating the overall curvature and local curvature of the deformation curve L in steps, the reliability of the verification process can be improved on the basis of controlling the amount of data processing in the verification process.

[0081] See also Figure 5 As shown, the deformation curve L can be obtained by converting the side shape of the splicing layer. For example, in some embodiments, the deformation curve L is a curve segment formed by the cross section of the upper surface of the splicing layer. For another example, in some embodiments, the deformation curve L can be a curve segment formed by the cross section of the lower surface of the splicing layer.

[0082] In some embodiments, curvature refers to the degree to which a layer (such as a spliced ​​layer) deforms when subjected to force (for example, different points in the layer sense different amounts of stress due to uneven shrinkage / deformation).

[0083] In some embodiments, the curvature of the splicing layer can be measured by laser interferometry. The object to be measured (such as the splicing layer) is placed on a laser interferometer measurement platform, and the height change of the surface of the object to be measured is measured using a laser interferometer. The warping (or curvature) of the object to be measured is calculated based on the change in the interference fringes.

[0084] Alternatively, in some other embodiments, an image measuring instrument may be used to measure the warpage of the spliced ​​layer at at least one position. The image measuring instrument is a high-precision measuring device that can obtain the warpage of the object by photographing and analyzing the surface of the object to be measured.

[0085] See also Figure 5 As shown, Figure 5FIG. 1 shows a schematic cross-sectional structure diagram of a splicing layer composed of four photonic chips 01. In some embodiments, Figure 4 The two photonic chips arranged on the left and right are respectively divided into different curve segments. For example, the left part of the left photonic chip and the second bonding area connected to it can be correspondingly divided into the second curve segment L2; and the adjacent parts of the left and right photonic chips and the first bonding area arranged in the middle can be divided into the first curve segment L1.

[0086] Of course, in other embodiments, when the specifications or quantity of the photonic chips change, the setting position or setting quantity of the curve segments can be adaptively adjusted according to application requirements.

[0087] Preferably, four photonic chips are arranged in a group of photonic chips, and the four photonic chips are of the same size. Of course, in other embodiments, according to different size requirements, other numbers of photonic chips may be arranged in a group of photonic chips, such as two or more, and the sizes of different photonic chips may also be slightly different, as long as the spliced ​​photonic chips can achieve the overall size requirements and the formed bonding layer can meet the stress test standards.

[0088] In some embodiments, the deformation curve can be simulated through a simulation process.

[0089] Alternatively, in some embodiments, the deformation curve may also be obtained by testing the splicing layer actually processed. For example, in some embodiments, before the splicing layer is actually mass-produced, a small amount of pre-production may be performed to evaluate the quality of the pre-produced splicing layer.

[0090] In some embodiments, the above one or more thresholds may be adaptively set by the user in combination with actual process conditions or process standards.

[0091] Embodiment 3 The present invention also provides a packaging and testing system 1000 for large-scale photonic chips, wherein the packaging and testing system is used to test a splicing layer, wherein the splicing layer includes: a first photonic chip 011, a second photonic chip 012, a third photonic chip 013 and a fourth photonic chip 014 arranged adjacent to each other, and the adjacent first side edges 01a and the second side edges 01b of any one of the photonic chips are arranged parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first adhesive material to form a first adhesive area; the side edges of the photonic chip arranged outwardly are bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edges to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer that wraps the photonic chip; correspondingly, see Figure 7 As shown, the packaging test system includes: A first acquisition module 1001 is used to acquire a deformation curve L of the splicing layer, where the deformation curve L is used to reflect the degree of bending deformation of the splicing layer on a plane; The second acquisition module 1002 is used to acquire at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L; and at least one of the first curve segments L1 can respectively cover at least a portion of two adjacent photonic chips, and the lengths covered by the first curve segments on the two adjacent photonic chips are the same or similar; and at least one of the second curve segments L2 can cover one photonic chip and a second bonding area adjacent to the corresponding photonic chip; The splicing rule judgment module 1003 is used to judge whether the deformation curve L satisfies a preset first splicing rule. If so, it is considered that the splicing layer meets the first splicing requirement; wherein, the first splicing rule requires that the first curvature of at least one of the first curve segments L1 is less than a preset first curvature threshold, and the second curvature of at least one of the second curve segments L2 is less than a preset second curvature threshold.

[0092] It can be understood that the packaging test system in this embodiment can implement any of the above-mentioned packaging test methods or steps, which will not be described in detail here.

[0093] In some embodiments, the side facing outward refers to a side that is not adjacent to (or opposite to) other photonic chips.

[0094] It should be noted that the packaging solution in the present invention can also be applied to the splicing of electronic chips. That is, the photonic chip can be replaced by an electronic chip. Of course, the specific setting of parameters such as the type of connection material and the bending threshold can also be adaptively set as the type of electronic chip changes.

[0095] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0096] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0097] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A packaging structure for a large-scale photonic chip, characterized in that: include: substrate(04); The upper surface of the substrate (04) is connected to a chip layer via a first bonding structure, and the chip layer comprises: at least one group of photonic chips; wherein the group of photonic chips comprises: A first photonic chip (011), a second photonic chip (012), a third photonic chip (013), and a fourth photonic chip (014) are arranged adjacent to each other, and the adjacent first side edge (01a) and the second side edge (01b) of any one of the photonic chips are arranged parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first bonding material to form a first bonding area; A second adhesive material is bonded to the outwardly disposed side edge of the photonic chip, and the second adhesive material extends in a direction away from the side edge to form a second adhesive area of ​​a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer that wraps the photonic chip, wherein a first connection area (11) and a second connection area (12) are provided on the photonic chip, and the first connection area is provided with a plurality of first conductive bumps, and the second connection area is provided with a photosensitive area; A silicon adapter plate (05), the silicon adapter plate (05) being arranged corresponding to the first connection area; an optical fiber array (06), the optical fiber array being arranged corresponding to the second connection area and coupled to the photosensitive area; Wherein, a first wiring layer (08) is arranged on the lower surface of the silicon adapter plate (05), between the optical fiber array and the adhesive layer, a plurality of first wiring channels are arranged on the first wiring layer, and a plurality of lead-out channels are arranged on the adhesive layer corresponding to the first conductive bumps, respectively, and the first wiring channels are used to lead out the first conductive bumps through the lead-out channels and connect them to the silicon adapter plate (05); At least one type of electronic chip (07) is arranged on the upper surface of the silicon adapter plate (05) via a second bonding structure, wherein the type of electronic chip (07) is indirectly communicatively connected with the group of photonic chips via the silicon adapter plate.

2. The packaging structure according to claim 1, characterized in that: The first width ranges from 0.1 mm to 0.5 mm.

3. The packaging structure according to claim 1, characterized in that: A second wiring layer (09) is provided on the second surface of the adhesive layer, a plurality of second wiring channels are provided on the second wiring layer, and the second wiring channels are connected to the first bonding structure.

4. The packaging structure according to claim 1, characterized in that: At least one second-class electronic chip is also arranged on the silicon adapter board, the second-class electronic chip includes: a high-bandwidth memory chip, and the second-class electronic chip is arranged on the side of the first-class electronic chip (07).

5. The packaging structure according to claim 1, characterized in that: The optical fiber array is vertically coupled to the photosensitive area.

6. A packaging and testing method for large-scale photonic chips, characterized in that: Includes steps: S100, providing a splicing layer, the splicing layer comprising: a first photonic chip (011), a second photonic chip (012), a third photonic chip (013) and a fourth photonic chip (014) arranged adjacent to each other, and the adjacent first side edges (01a) and the second side edges (01b) of any one of the photonic chips are arranged parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first adhesive material to form a first adhesive area; the side edges of the photonic chips arranged outward are bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edges to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer that wraps the photonic chip; S101, obtaining a deformation curve L of the splicing layer, wherein the deformation curve L is used to reflect the degree of bending deformation of the splicing layer on a plane; S102, obtaining at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L; at least one of the first curve segments L1 can respectively cover at least a portion of two adjacent photonic chips, and the lengths covered by the first curve segments L1 on the two adjacent photonic chips are the same or similar; at least one of the second curve segments L2 can cover one photonic chip and a second bonding area adjacent to the corresponding photonic chip; S103, determining whether the deformation curve L satisfies a preset first splicing rule. If so, it is considered that the splicing layer satisfies a first splicing requirement; wherein the first splicing rule requires that a first curvature of at least one of the first curve segments L1 is less than a preset first curvature threshold, and a second curvature of at least one of the second curve segments L2 is less than a preset second curvature threshold.

7. The packaging test method according to claim 6, characterized in that: The first splicing rule further requires that a first difference between the first curvature and the second curvature is smaller than a set first curvature difference threshold.

8. The packaging test method according to claim 6 or 7, characterized in that: The first splicing rule also requires that a second difference between at least two second curvatures corresponding to at least two of the second curve segments L2 is smaller than a set second curvature difference threshold; and the corresponding at least two second curve segments L2 are located at symmetrical positions on the splicing layer.

9. The packaging test method according to claim 6 or 7, characterized in that: When there are multiple first curve segments L1, the first curvature of the multiple first curve segments L1 is the average curvature of the multiple first curve segments; and / or, when there are multiple second curve segments L2, the second curvature of the multiple second curve segments L2 is the average curvature of the multiple second curve segments L2.

10. A large-scale photonic chip packaging and testing system, characterized in that: The packaging and testing system is used to test a splicing layer, wherein the splicing layer comprises: a first photonic chip (011), a second photonic chip (012), a third photonic chip (013) and a fourth photonic chip (014) arranged adjacent to each other, and the adjacent first side edges (01a) and the second side edges (01b) of any one of the photonic chips are arranged parallel or approximately parallel to the side edges corresponding to the other two adjacent photonic chips, and a gap space with a first width is formed between the two oppositely arranged side edges, and the gap space is filled with a first adhesive material to form a first adhesive area; the side edges of the photonic chips arranged outward are bonded with a second adhesive material, and the second adhesive material extends in a direction away from the side edges to form a second adhesive area with a second width, and the first adhesive area and the second adhesive area are connected to form an adhesive layer for wrapping the photonic chip; correspondingly, the packaging and testing system comprises: A first acquisition module, used for acquiring a deformation curve L of the splicing layer, wherein the deformation curve L is used for reflecting the degree of bending deformation of the splicing layer on a plane; A second acquisition module is used to acquire at least one first curve segment L1 and at least one second curve segment L2 in the deformation curve L; and at least one of the first curve segments L1 can respectively cover at least a portion of two adjacent photonic chips, and the lengths covered by the first curve segments on the two adjacent photonic chips are the same or similar; and at least one of the second curve segments L2 can cover one photonic chip and a second bonding area adjacent to the corresponding photonic chip; The splicing rule judgment module is used to judge whether the deformation curve L satisfies a preset first splicing rule. If so, it is considered that the splicing layer meets the first splicing requirement; wherein, the first splicing rule requires that the first curvature of at least one of the first curve segments L1 is less than a preset first curvature threshold, and the second curvature of at least one of the second curve segments L2 is less than a preset second curvature threshold.

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