Chip packaging method, chip packaging structure and electronic equipment

Abstract

The invention discloses a chip packaging method, a chip packaging structure and electronic equipment. The packaging method comprises the steps that underfill glue is arranged on the first surface, and solidified glue can cover the solder balls; removing part of the solidified colloid to expose at least part of the solder balls; and mounting the chip on the substrate through the solder balls, and carrying out plastic packaging on the mounted product. According to the chip packaging method provided by the invention, the risk of generating holes after plastic packaging can be avoided, and the yield of products is improved.

Description

Technical Field

[0001] The present application relates to the technical field of product packaging, and more specifically, to a chip packaging method, a packaging structure and an electronic device. Background Art

[0002] The existing chip packaging method has a capacity limit in the plastic encapsulation process. When the size of the solder balls on the chip and the adjacent distance are small, holes are likely to appear near the solder balls after the plastic encapsulation material is filled, causing the chip after plastic encapsulation to be prone to short circuits and other problems, reducing the product yield.

[0003] In view of this, it is urgent to develop a chip packaging method that is less likely to have voids. Summary of the invention

[0004] One purpose of the present application is to provide a new technical solution for a chip packaging method, a packaging structure and an electronic device.

[0005] According to a first aspect of the present application, a chip packaging method is provided, wherein a plurality of solder balls are arranged at intervals on a first surface of the chip, and the packaging method comprises:

[0006] Setting an underfill on the first surface, and making the cured colloid cover each of the solder balls;

[0007] removing part of the solidified colloid to expose at least part of each solder ball;

[0008] The chip is mounted on the substrate through the solder balls, and the mounted product is plastic-sealed.

[0009] Optionally, the step of enabling the cured colloid to cover each of the solder balls comprises:

[0010] In the height direction of the solder balls, the height of the colloid is greater than the height of each of the solder balls; and the colloid fills the gaps between the solder balls.

[0011] Optionally, in the height direction of the solder balls, the height of the colloid exceeds the height of each solder ball by 80 um to 100 um.

[0012] Optionally, removing part of the cured glue includes: removing it by laser.

[0013] Optionally, exposing at least a portion of each solder ball includes:

[0014] A hole is opened at a position corresponding to the top of each solder ball, and the cross-sectional area of ​​each solder ball at the depth of the hole is made to account for 50% to 80% of the maximum cross-sectional area of ​​each solder ball.

[0015] Optionally, when the chip is mounted on a substrate, the solidified colloid is melted and wraps each of the solder balls.

[0016] Optionally, the chip is mounted on the substrate by SMT.

[0017] Optionally, the height of each solder ball is less than 50 um, and the distance between two adjacent solder balls is less than 70 um.

[0018] According to a second aspect of the present application, a packaging structure is provided, which is manufactured using the packaging method described in the first aspect.

[0019] According to a third aspect of the present application, an electronic device is provided, comprising: the packaging structure described in the second aspect.

[0020] According to one embodiment of the present application, during the packaging process, the present application first sets the bottom filling glue on the first surface of the chip, and then performs the mounting and plastic sealing process, thereby effectively solving the problem of holes in the product after plastic sealing, thereby improving the yield of the product. At the same time, there is no need to reserve glue dispensing positions around the chip, thereby improving the packaging density of the product.

[0021] Other features and advantages of the present application will become apparent from the following detailed description of exemplary embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0023] Figure 1 It is a schematic diagram of the structure of the chip provided in this application.

[0024] Figure 2 yes Figure 1 Side view of.

[0025] Figure 3 This is a schematic diagram of a chip with an underfill disposed on the first surface provided by the present application.

[0026] Figure 4 yes Figure 3 Side view of.

[0027] Figure 5 This is a schematic diagram of the chip provided in the present application after some colloids are removed.

[0028] Figure 6 yes Figure 5 A partial enlarged view of point C in the middle.

[0029] Figure 7 yes Figure 5 Side view of.

[0030] Figure 8 It is a schematic diagram of the chip and substrate mounting process provided by this application.

[0031] Fig. 9 This is a schematic diagram of a packaging structure provided by this application.

[0032] Description of reference numerals:

[0033] 1. Chip; 11. Wafer; 12. Solder ball; 13. Colloid; 2. Substrate; 3. Electronic component; 4. Package. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0035] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.

[0036] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0037] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0038] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0039] like Figures 1 to 9 As shown, according to the first aspect of the present application, a packaging method for a chip 1 is provided, wherein a plurality of solder balls 12 are spaced apart on a first surface of the chip 1, and the packaging method comprises: setting an underfill on the first surface, and allowing the cured colloid 13 to cover each solder ball 12; removing part of the cured colloid 13 to expose at least part of the area of ​​each solder ball 12; mounting the chip 1 on a substrate 2 through each solder ball 12, and plastic-sealing the mounted product.

[0040] Specifically, in the present embodiment, the chip 1 packaging method provided by first setting the bottom filler and then performing mounting and plastic sealing can not only fill the gaps between the solder balls 12 with the colloid 13, but also reduce the risk of holes in the packaged product after plastic sealing, and improve the yield of the packaged product. In addition, compared with the existing bottom filler method, it avoids the need to reserve a glue point on the substrate 2, improves the packaging density of the packaged product, and is conducive to the miniaturization of the product.

[0041] In the above embodiment, the chip 1 is usually a wafer 11, and the wafer 11 is composed of a plurality of crystal grains, each crystal grain is provided with an array of solder balls 12, and the solder balls 12 are used to be soldered with the substrate 2 during the mounting process. As the gaps between some solder balls 12 are small, the method of first filling the bottom with glue and then mounting the chip with plastic sealing is adopted, which greatly reduces the occurrence of plastic sealing holes near the solder balls 12 and avoids the problem of short circuit between the subsequent solder balls 12. Figure 1 and Figure 2 Wherein, an underfill is provided on the first surface of the chip 1 , that is, an underfill is provided on the side surface having the solder balls 12 .

[0042] In the actual process, the bottom filler is a material that uses chemical glue (the main component is epoxy resin) to fill the bottom of the chip 1 in the BGA (ball grid array) packaging mode. Its application principle is to use capillary action to make the glue flow quickly into the bottom of the BGA chip 1 and fill the gap over a large area, thereby achieving the purpose of reinforcement. The setting of the bottom filler can significantly improve the connection strength between the subsequent chip 1 and the substrate 2, enhance the overall mechanical structure strength, and thus improve the vibration and impact resistance of the chip 1. After the bottom filler fills the gaps between the solder balls 12, it can fully protect the bottom circuit part from electrical energy, play a role in waterproofing, dustproofing and corrosion resistance, and improve the overall reliability of the packaged product. In addition, the use of the bottom filler can also alleviate the stress concentration problem caused by the mismatch of thermal expansion coefficients between different materials in the subsequent packaging process of the chip 1, and protect the chip 1 from damage by thermal stress.

[0043] In this embodiment, after the underfill is set, the colloid 13 after solidification can cover each solder ball 12, so as to ensure that in the subsequent mounting process, the colloid 13 can fill the gaps between the solder balls 12 and between the chip 1 and the substrate 2 after melting, so as to ensure the reliability of the underfill. Figure 3 and Figure 4 The underfill has good process operability and is easy to implement on the production line, thus reducing production costs.

[0044] Furthermore, after the cured colloid 13 covers the solder balls 12, at least a portion of each solder ball 12 is exposed by removing part of the colloid 13, so that the solder balls 12 can be subsequently soldered to the substrate 2 to form the basic structure of the packaged product. Specifically, which part of the colloid 13 is removed and how much of the colloid 13 is removed is appropriate so that the exposed portion of each solder ball 12 can be firmly connected to the substrate 2. For example, a portion of the colloid 13 on the top of the solder ball 12 is removed to expose the top of each solder ball 12. Figures 5 to 7 In addition, the colloid 13 can be removed by mechanical grooving, laser ablation or other methods, which are not limited in the present application.

[0045] Then, the chip 1 is mounted on the substrate 2 by welding the solder balls 12 with the solder paste on the substrate 2 to form a mounted product. In this process, other electronic components 3 can also be mounted at the same time. Figure 8 The specific requirements of the packaged product are determined, and this application does not impose any restrictions on this. In addition, during the mounting process, since the solder balls 12 need to be melted and soldered, the bottom filler around each solder ball 12 will usually melt and flow, and then fill the holes and gaps between the chip 1 and the substrate 2, so that the chip 1 and the substrate 2 form a reliable and firm connection. The mounting process can be referred to Figure 8 Finally, the mounted product is plastic-sealed to form a package body 4 covering the outside of the chip 1, so as to achieve the plastic sealing and protection of the entire chip 1 and produce a packaged product with specific functions. Fig. 9 .

[0046] The above-mentioned packaging method provided in the present application improves the problem of holes generated after plastic packaging, and since there is no need to reserve a glue dispensing position, the packaging density can be increased by 20%, while improving the product yield and the purpose of miniaturization design, and does not require complicated processes to implement, and is suitable for mass production.

[0047] Alternatively, if Figure 3 and Figure 4 As shown, the cured colloid 13 can cover each solder ball 12 including: in the height direction of the solder ball 12 , the height of the colloid 13 is greater than the height of each solder ball 12 ; and the colloid 13 fills the gaps between the solder balls 12 .

[0048] Specifically, in the present embodiment, the colloid 13 after the bottom filling glue is cured covers each solder ball 12, and it is necessary to ensure that it completely covers the solder ball 12 in the height direction of the solder ball 12, and fill the gaps between the solder balls 12, so as to avoid the problem of subsequent holes caused by insufficient glue or uneven glue filling during thermal mounting, which may cause the glue to fail to fully fill the gap between the substrate 2 and the chip 1, thereby further ensuring the packaging yield of the packaged product.

[0049] Alternatively, if Figure 4As shown, in the height direction of the solder balls 12 , the height of the colloid 13 exceeds the height of each solder ball 12 by 80 um to 100 um.

[0050] Specifically, in this embodiment, in the height direction of the solder ball 12, the colloid 13 exceeds the solder ball by 1280um to 100um (refer to Figure 4 The size of a in the figure is 85um, 90um, 95um, etc., so that in the subsequent mounting process, the amount of the colloid 13 after melting can fully fill the gaps between the solder balls 12 and the gaps between the chip 1 and the substrate 2, and will not overflow to other positions of the substrate 2 due to excessive glue, affecting the function of the packaged product. In addition, setting the size of the colloid 13 exceeding the solder ball 12 to no more than 100um is also conducive to the subsequent removal of the glue, avoiding the difficulty of removal due to excessively thick glue, and ensuring the convenience of the process.

[0051] Optionally, refer to Figures 5 to 7 , remove part of the glue after curing, including: removing by laser method.

[0052] Specifically, in this embodiment, laser is used to remove part of the glue after curing. On the one hand, based on the high energy and local focusing characteristics of the laser beam, the glue can be quickly heated and evaporated, thereby improving the removal efficiency. In addition, the focusing characteristics of the laser beam make the removal process very precise, and only remove the local glue without damaging the surrounding materials. For example, the melting temperature of the solder ball 12 is usually higher than the evaporation temperature of the glue. The use of laser removal can not only achieve the purpose of removing the glue near the solder ball 12, exposing part of the solder ball 12, but also ensure that the solder ball 12 is not damaged by the laser, so as to ensure that the reliability of welding with the substrate 2 can be improved in the subsequent mounting process.

[0053] Furthermore, the laser method of removing glue does not produce pollutants such as waste gas and waste liquid. It is also a contactless operation method, which reduces the risk of workers being exposed to harmful substances and improves the environmental protection and safety of the process.

[0054] In actual operation, a hole can be made at the glue on the top of the solder ball 12 by laser to expose the top area of ​​each solder ball 12, and the depth and size of the hole can be precisely controlled. For example, the shape of the hole can be set to a hole with a trapezoidal cross-section that is large on the outside and small on the inside, so as to facilitate the subsequent positioning of the welding point on the substrate 2. In addition, the wafer 11 of the chip 1 is composed of a plurality of grains. The position of the hole when making the hole can be positioned by positioning it in the non-glue-coated area around the chip 1, or it can be positioned according to the boundary between the grains, so that each solder ball 12 has at least a part of its area exposed on the outside.

[0055] Alternatively, if Figures 5 to 7As shown, at least a portion of each solder ball 12 is exposed, including: opening a hole at a position corresponding to the top of each solder ball 12, and making the cross-sectional area of ​​each solder ball 12 at the depth of the hole account for 50% to 80% of the maximum cross-sectional area of ​​each solder ball 12.

[0056] Specifically, in the present embodiment, the hole depth refers to the hole depth in the height direction of the solder ball 12. In practical applications, if the hole is too deep, too much glue will be removed, which may easily lead to insufficient amount of glue to fill the gap near the solder ball 12 after melting during mounting, and there is still a risk of holes after packaging. If the hole is too shallow, it may cause too little exposed area of ​​each solder ball 12, thereby affecting the reliability of welding with the solder paste on the substrate 2 during subsequent mounting. The present application sets this depth so that after removing the glue, the cross-sectional area of ​​the solder ball 12 at the bottom of the slot of the hole accounts for 50% to 80% of the maximum cross-sectional area of ​​the solder ball 12, such as 60%, 70%, etc., which not only ensures the subsequent glue filling amount near the solder ball 12, but also ensures the exposed area of ​​the solder ball 12, thereby improving the reliability of welding.

[0057] In the above embodiment, the cross-sectional area of ​​each solder ball 12 at the opening depth can be referred to as Figure 6 and Figure 7 The cross-sectional area at the S1 mark in the figure, and the maximum cross-sectional area of ​​each solder ball 12 can be referred to Figure 6 and Figure 7 From the cross-sectional area at the S2 mark, it can be seen that S1 is larger than S2. When mounting the chip 1, the exposed solder balls 12 can ensure smooth soldering with the substrate 2. In addition, the positioning method of the openings at the top positions corresponding to the solder balls 12 can refer to the boundary lines between the grains for positioning.

[0058] Alternatively, if Figure 8 As shown, when the chip 1 is mounted on the substrate 2 , the solidified colloid 13 is melted and wraps each solder ball 12 .

[0059] Specifically, in this embodiment, when the chip 1 is mounted on the substrate 2, each solder ball 12 needs to be melted and connected to the solder ball 12 or solder paste at the corresponding position on the substrate 2 by welding, which is a key step for mounting. In this process, the mounting temperature needs to ensure that the colloid 13 is completely melted and fully flows to fill the gaps, and can completely wrap each solder ball 12, so that even if the gaps are not fully filled due to insufficient glue, insulation between the solder balls 12 can be achieved, further reducing the risk of short circuits and improving the yield of products.

[0060] Alternatively, if Figure 8 As shown, the chip 1 is mounted on the substrate 2 by SMT.

[0061] Specifically, SMT (Surface Mount Technology) usually includes tin printing (reference Figure 8 Step S01), chip 1 is mounted (reference Figure 8 Step S02) and reflow (reference Figure 8 Step S03).

[0062] Tin printing refers to printing solder paste on the substrate 2 . In this embodiment, solder paste is provided at positions corresponding to the mounting positions of the chip 1 and corresponding to the solder balls 12 , so as to facilitate mounting with the chip 1 .

[0063] Chip 1 patching refers to mounting the side (first surface) of the chip 1 with the solder ball 12 on the position of the tin printing on the substrate 2, that is, positioning and fixing the chip 1. In this process, other electronic components 3 can be patched at the same time.

[0064] Reflow refers to melting and welding the solder balls 12, solder paste, etc. at high temperature to form a connection between the chip 1 and the substrate 2. In this process, it is necessary to ensure that the cured glue can melt and wrap each solder ball 12 to improve the reliability of mounting. After reflow, the product can also be cleaned, tested, etc., which is not limited in this application.

[0065] The chip 1 is mounted using SMT technology, which can achieve high-density assembly, resulting in advantages such as small size, light weight, high reliability, strong vibration resistance, low solder joint defect rate, good high-frequency characteristics and low production cost, which can further improve the yield of packaged products and is suitable for mass production.

[0066] Alternatively, if Figure 2 As shown, the height of each solder ball 12 is less than 50 um, and the distance between two adjacent solder balls 12 is less than 70 um.

[0067] Specifically, in practical applications, if the solder ball 12 is relatively large and the distance between two adjacent solder balls 12 is relatively large, the risk of short circuit of the solder ball 12 can be reduced, while when the height of the solder ball 12 is relatively small and the distance between adjacent solder balls is relatively small, the phenomenon of short circuit of the solder ball 12 will easily occur. In particular, when the height of the solder ball 12 is less than 50um and the distance between two adjacent solder balls 12 is less than 70um, the packaging form of first bottom filling and then chip 1 mounting and plastic sealing of the present application can fully fill the gaps and clearances during bottom filling, and the amount of filling is easy to control, so that the glue can fully wrap each solder ball during subsequent reflow soldering, thereby improving its product yield and greatly reducing the packaging cost of such products.

[0068] According to the second aspect of the present application, Fig. 9 As shown, a packaging structure is provided, which is manufactured using the packaging method of the first aspect.

[0069] Specifically, in this embodiment, a packaging structure is provided, which is manufactured by the packaging method of the first aspect, so that the holes of the packaging structure are reduced, the yield is improved, and the functional reliability of the packaging structure is improved. In addition, its packaging density is high, which is conducive to the miniaturization of the packaging product.

[0070] According to the third aspect of the present application, reference Fig. 9 , provides an electronic device, including: the packaging structure of the second aspect.

[0071] Specifically, in this embodiment, the packaging structure of the second aspect is applied to electronic equipment, which can improve the overall reliability and safety of the electronic equipment and is beneficial to the miniaturization and cost control of the electronic equipment.

[0072] The above embodiments focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0073] Although some specific embodiments of the present application have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are only for illustration, not for limiting the scope of the present application. It should be understood by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A chip packaging method, characterized in that: A plurality of solder balls are arranged at intervals on the first surface of the chip, and the packaging method comprises: Setting an underfill on the first surface, and making the cured colloid cover each of the solder balls; removing part of the solidified colloid to expose at least part of each solder ball; The chip is mounted on the substrate through the solder balls, and the mounted product is plastic-sealed.

2. The packaging method according to claim 1, characterized in that: The step of enabling the cured colloid to cover each of the solder balls comprises: In the height direction of the solder balls, the height of the colloid is greater than the height of each of the solder balls; and the colloid fills the gaps between the solder balls.

3. The packaging method according to claim 2, characterized in that: In the height direction of the solder balls, the height of the colloid exceeds the height of each solder ball by 80 um to 100 um.

4. The packaging method according to claim 1, characterized in that: The removing of part of the cured glue includes: removing by laser method.

5. The packaging method according to claim 1, characterized in that: Exposing at least a portion of each solder ball includes: A hole is opened at a position corresponding to the top of each solder ball, and the cross-sectional area of ​​each solder ball at the depth of the hole is made to account for 50% to 80% of the maximum cross-sectional area of ​​each solder ball.

6. The packaging method according to claim 1, characterized in that: When the chip is mounted on a substrate, the solidified colloid is melted and wraps each of the solder balls.

7. The packaging method according to claim 1, characterized in that: The chip is mounted on the substrate by SMT.

8. The packaging method according to claim 1, characterized in that: The height of each solder ball is less than 50 um, and the distance between two adjacent solder balls is less than 70 um.

9. A packaging structure, characterized in that: The packaging method is adopted as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The packaging structure as claimed in claim 9.

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