Data transmission method, device and equipment

Abstract

The invention provides a data transmission method, device and equipment, and the method comprises the steps: responding to a target instruction, carrying out the configuration of a clock chip in a digital-to-analog conversion system based on the target instruction, generating a target clock, enabling the target instruction to be used for indicating the change of the current sampling rate in the digital-to-analog conversion system to a target sampling rate, and enabling the current sampling rate to be equal to the target sampling rate; the target clock is matched with a target sampling rate; interface parameters of a channel configurable interface in the digital-to-analog conversion system are configured based on a target instruction, the interface parameters comprise the number of interface channels, and the number of the configured interface channels is matched with a target sampling rate; modifying a line rate and a channel number of a core in the channel configurable interface based on an interface parameter and a target clock; and transmitting sampling data of the digital-to-analog conversion system based on the channel configurable interface after parameter adjustment. According to the data transmission method, the number of interface channels can be dynamically adjusted according to the change of the system sampling rate, and then the data transmission rate is adjusted.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a data transmission method, device and equipment. Background Art

[0002] Although the ADC / DAC using the JESD204B interface (JESD204B is an efficient transmission interface protocol designed for ADC (analog-to-digital converter) and DAC (digital-to-analog converter)) solves the problem of high-speed data transmission, with the development of technology, the requirements for signal processing are becoming more and more comprehensive, and both broadband and narrowband signals must be processed. At this time, if only high sampling rates are used to collect signals, when processing narrowband signals, it will cause resource waste and be more troublesome to process. Therefore, it is necessary to be able to dynamically adjust the sampling rate. As the amount of data to be transmitted changes, the parameters of the JESD204B interface must also change accordingly. Affected by the ADC / DAC chip, in the JESD204B protocol, the line rate of the ADC / DAC end is generally required to be 0.75Gsps-12.5Gsps. When the number of channels (L) of the JESD204B interface is fixed, the range of the number of transmissions is between 0.75*L-12.5*LGbps.

[0003] In real applications, there are situations where the data volume varies beyond this range. Specifically, the sampling rate of ADC / DAC is getting higher and higher, and the data throughput is getting larger and larger. It is difficult to meet the design requirements with traditional CMOS and LVDS, so JESD204B came into being. JESD204B is a serial interface standard based on SerDes (Serialization / DESerialization) technology, which is mainly used for data transmission between digital-to-analog converters (DACs) and logic devices. SerDes technology is a mainstream time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. It converts multi-bit parallel data into 1-bit serial data at the transmitting end, and restores the serial data to the original parallel data at the receiving end.

[0004] In JESD204B applications, a set of JESD204B parameters are generally determined based on the usage scenario. Two of these parameters are related to the transmission rate, one is the line rate, and the other is the number of channels. In FPGA-based ADC / DAC signal processing systems, the development of FPGA processing of JESD204B interfaces is generally implemented using Xilinx's JESD204 and JESD204 PHY IP cores. JESD204 PHY implements physical layer functions, and JESD204 implements protocol control of the link layer and transport layer.

[0005] The general process of developing a signal processing system based on the JESD204B protocol interface is as follows:

[0006] 1. Determine the maximum sampling rate in the application. The sampling rate can tell you how much data needs to be transmitted through the JESD204B interface.

[0007] 2. Determine a set of JESD204B parameters based on the ADC / DAC data sheet, including line rate and number of channels.

[0008] 3. On the FPGA side, the JESD204 and JESD204 PHY IP cores provided by Xilinx are used to implement the control and analysis of the JESD204B protocol. JESD204 PHY implements the physical layer function, and JESD204 implements the protocol control of the link layer and transport layer. Generate the IP core according to the parameters, and after completing the development of other FPGA modules, compile and generate the burning file or solidification file.

[0009] 4. Download the program, and then debug to check whether the JESD204B link is connected normally and whether data can be sent and received normally.

[0010] FPGA is a programmable logic chip. During the development process, the design can be modified repeatedly. In the development of JESD204B, the L value can be changed by modifying the relevant content in the program, such as the generation configuration of the IP core, and then recompiling. However, in a project that has been compiled and generated to generate a burning file, its structure cannot be changed.

[0011] Therefore, after the development is completed, during the operation of the system, it is impossible to physically reduce or increase the number of channels (L), which is a hardware-oriented setting. As described in point 1, when the number of channels (L) remains unchanged, it cannot fully adapt to some scenarios where the sampling rate changes greatly. Summary of the invention

[0012] The technical problem to be solved by the present invention is to provide a data transmission method, device and equipment which can dynamically adjust the number of interface channels according to changes in the system sampling rate, and thus adjust the data transmission rate.

[0013] The present invention includes a data transmission method, which is applied to a digital-analog conversion system with a channel configurable interface, wherein the digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the method includes:

[0014] In response to a target instruction, a clock chip in the digital-to-analog conversion system is configured based on the target instruction to generate a target clock, wherein the target instruction is used to instruct to change a current sampling rate in the digital-to-analog conversion system to a target sampling rate, and the target clock matches the target sampling rate;

[0015] Based on the target instruction, configure the interface parameters of the channel configurable interface in the digital-analog conversion system, wherein the interface parameters include the number of interface channels, and the configured number of interface channels matches the target sampling rate;

[0016] Modifying the line rate and number of channels of the core in the channel configurable interface based on the interface parameters and the target clock;

[0017] The channel configurable interface transmits the sampled data of the digital-to-analog conversion system based on the adjusted parameters.

[0018] In some embodiments, the cores in the channel configurable interface include at least two groups, each group of cores is used to process data in a first number of channels;

[0019] The modifying the line rate and the number of channels of the core in the channel configurable interface based on the interface parameters and the target clock includes:

[0020] determining a modified number of channels based on the interface parameters;

[0021] Comparing the modified number of channels with the first number;

[0022] Each group of cores in the channel configurable interface is reconfigured based on the size relationship and the target clock.

[0023] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0024] When the number of channels after the size relationship representation is modified is greater than the first number, determining the channels and the number of channels that the first group of cores and the second group of cores in the channel configurable interface are responsible for respectively based on the modified number of channels;

[0025] Based on the target clock and the channels and the number of channels that the first group of cores and the second group of cores are responsible for, the line rates and the number of channels of the first group of cores and the second group of cores are reconfigured respectively.

[0026] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0027] When the number of channels after the size relationship representation is modified is less than the first number, determining the number of channels that the first group of cores in the channel configurable interface is responsible for based on the modified number of channels;

[0028] The line rate and number of channels of the first group of cores are configured based on the target clock and the channels and number that the first group of cores are responsible for.

[0029] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0030] When the modified number of channels is not greater than the first number and the current number of channels is greater than the first number, the signals transmitted in the channel-configurable interface are separated for the first group of cores and the second group of cores, and the line rate and number of channels are configured for the first group of cores in combination with the target clock, so that the first group of cores and the channels corresponding to the first group of cores are used for processing and transmitting sampled data, while data transmitted by the channels corresponding to the second group of cores is ignored.

[0031] In some embodiments, configuring the line rate and the number of channels of the first group of cores in combination with the target clock includes:

[0032] The synchronization signal circuit parameters in the first group of cores are reconfigured in combination with the target clock and the target sampling rate to modify the current line rate, and the number of channels is modified based on the AXI configuration interface in the first group of cores.

[0033] In some embodiments, the method further comprises:

[0034] Determine the adjusted channel for data transmission and the core for data processing;

[0035] The sampling data transmitted by the channel is obtained, and the sampling data is intercepted by the core based on the number of bytes of each channel, and then the intercepted sampling data is formatted according to the target protocol format to obtain target sampling data matching the sampling point.

[0036] In some embodiments, the method further comprises:

[0037] In response to a target instruction, determining whether a current clock matches a target sampling rate in the target instruction;

[0038] If there is no match, the clock chip in the digital-analog conversion system is configured based on the target instruction to generate the target clock.

[0039] Another embodiment of the present invention also provides a data transmission device, which is applied to a digital-analog conversion system having a channel configurable interface, wherein the digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the device includes:

[0040] A first response module is used to respond to a target instruction and configure the clock chip in the digital-analog conversion system based on the target instruction to generate a target clock, wherein the target instruction is used to instruct to change the current sampling rate in the digital-analog conversion system to a target sampling rate, and the number of interface channels after configuration matches the target sampling rate;

[0041] A first configuration module, configured to configure interface parameters of a channel configurable interface in the digital-analog conversion system according to the target instruction, wherein the interface parameters include the number of interface channels, and the number of interface channels matches the target sampling rate;

[0042] A modification module, used to modify the line rate and number of channels of the core in the channel configurable interface according to the interface parameters and the target clock;

[0043] A transmission module is used to transmit the sampling data of the digital-analog conversion system according to the channel configurable interface after parameter adjustment.

[0044] Another embodiment of the present invention further provides an electronic device, comprising:

[0045] one or more processors;

[0046] a memory configured to store one or more programs;

[0047] When the one or more programs are executed by the one or more processors, the one or more processors implement the data transmission method as described in any one of the embodiments above.

[0048] The beneficial effect of the present invention is that the interface parameters and core parameters for different sampling rates are modified through the channel configurable interface in the digital-to-analog conversion system, so that the number of channels, line rate and system clock of the interface can change dynamically according to the change of the sampling rate, ensuring that the number of channels, line rate and clock can always match the sampling rate, thereby ensuring that the transmission rate of the sampled data always meets the requirements and does not cause waste of resources. The method in the present application reduces the development workload compared to the existing method of using multiple versions of programs and repeated burning programs, and in actual use, there is no need to switch the burning program back and forth according to the scene. Only a preset target instruction needs to be sent to achieve the adaptive modification of the parameters and change the transmission speed, which greatly improves the convenience and efficiency of operation.

[0049] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0050] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 The figure is a flowchart of a data transmission method in an embodiment of the present invention.

[0053] Figure 2 FIG. 4 is a clock connection relationship diagram in another embodiment of the present invention.

[0054] Figure 3 FIG. 4 is a flow chart of a data transmission method in another embodiment of the present invention.

[0055] Figure 4 4 is a structural block diagram of a data transmission device in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0057] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0058] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0059] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the accompanying drawings.

[0060] It should also be understood that, although the invention has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0061] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0062] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0063] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0064] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0065] like Figure 1 As shown, an embodiment of the present invention includes a data transmission method, which is applied to a digital-analog conversion system with a channel configurable interface, wherein the digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the method includes:

[0066] S1: In response to a target instruction, a clock chip in the digital-analog conversion system is configured based on the target instruction to generate a target clock, wherein the target instruction is used to instruct to change the current sampling rate in the digital-analog conversion system to a target sampling rate, and the target clock matches the target sampling rate;

[0067] S2: configuring interface parameters of a channel configurable interface in the digital-analog conversion system based on the target instruction, wherein the interface parameters include the number of channels, and the number of interface channels matches the target sampling rate;

[0068] S3: modifying the line rate and the number of channels of the core in the channel configurable interface based on the interface parameters and the target clock;

[0069] S4: The channel configurable interface transmits the sampled data of the digital-to-analog conversion system based on the adjusted parameters.

[0070] The target instruction can be an instruction formed by user input, the activation of a target program or a target function, and the target instruction is mainly used to instruct the digital-analog conversion system to update the current sampling rate to the target sampling rate. The change in sampling rate means that the amount of data transmission of the interface in the system changes, and the change in the amount of data transmitted involves the change in the number of channels used to transmit data, as well as the data transmission speed in the channel, that is, the change in line speed. In order to ensure that the interface still meets the requirements for the transmission of the adopted data at the target sampling rate, and there will be no significant decrease in transmission speed and no waste of resources, it is necessary to modify and reconfigure the various parameters of the interface in the system, so as to match the configuration of the interface with the data transmission requirements at the target sampling rate.

[0071] In this embodiment, if Figure 2 As shown, the digital-to-analog conversion system can be specifically a digital-to-analog conversion system, or an analog-to-digital conversion system, and the digital-to-analog conversion system is referred to as an ADC / DAC system hereinafter. The ADC / DAC system in this embodiment includes an ADC / DAC chip, which is used to perform data sampling, and perform digital-to-analog or analog-to-digital conversion, and can also be used to control the transmission of sampled data. The system also includes a clock chip and a programmable gate array chip. The clock chip is responsible for providing various clock signals required in the system. The programmable gate array chip, such as an FPGA chip, is not specific and can also be other chips with FPGA chip functions. The programmable gate array chip is responsible for the transmission of sampled data, including data reception, processing, etc.

[0072] When the system obtains the target instruction, in response to the target instruction, it first determines the target sampling rate and the current sampling rate in the target instruction, and adjusts the current parameters of the chip based on the target sampling rate and the current sampling rate to generate a new target clock that matches the target sampling rate. Then, based on the target sampling rate, the interface parameters of the channel configurable interface in the system are configured, specifically including the reconfiguration of the number of channels of the interface. Thereafter, based on the interface parameters and the target clock, the line rate and the number of channels of the core in the channel configurable interface are modified, and the parameter adjustment of the interface is completed. The ADC / DAC chip starts to sample data based on the target sampling rate, and transmits the sampled data through the channel configurable interface after parameter adjustment.

[0073] The beneficial effect of this embodiment is that the interface parameters and core parameters for different sampling rates are modified through the channel configurable interface in the digital-to-analog conversion system, so that the number of channels, line rate and system clock of the interface can change dynamically according to the change of the sampling rate, ensuring that the number of channels, line rate and clock can always match the sampling rate, thereby ensuring that the transmission rate of the sampled data always meets the requirements and does not cause resource waste. The method in this embodiment reduces the workload of program development compared to the existing method of using multiple versions of programs and repeated burning programs, and in actual use, there is no need to switch the burning program back and forth according to the scene. Only a preset target instruction needs to be sent to achieve the adaptive modification of the parameters and change the transmission speed, which greatly improves the convenience and efficiency of operation.

[0074] In one embodiment, the cores in the channel configurable interface include at least two groups, each group of cores is used to process data in a first number of channels. For example, each group of cores in this embodiment includes JESD204 PHY and JESD204 IP core, and the corresponding channel configurable interface is JESD204B interface. Of course, it can also be other types of interfaces and other types of cores. The specific ones are not unique. This embodiment takes JESD204B interface, JESD204 PHY and JESD204 IP core as examples for explanation; the method in this embodiment is designed according to the maximum sampling rate of 9600Msps, the number of channels L is 16, and the system includes a clock chip configuration module, an ADC chip configuration module and a JESD204B protocol controller module. The clock chip configuration module mainly writes the register configuration information into the clock chip through the SPI interface to generate the clock required for the normal operation of the system, namely the target clock; the ADC chip configuration module writes the register configuration information into the ADC chip through the SPI interface to configure the configuration of the JESD204B interface transmitter; the JESD204B protocol controller module is the receiving end of the JESD204B interface on the FPGA side, which mainly includes the JESD204 PHY and JESD204 IP core, as well as an auxiliary data format conversion module.

[0075] Furthermore, when the system operates normally, the workflow is as follows:

[0076] a) The device is powered on and the FPGA program is loaded into the FPGA chip;

[0077] b) Configure the clock chip;

[0078] c) Configure the ADC module;

[0079] d) JESD204B interface initialization and link connection;

[0080] e) Data format conversion, outputting the data collected by ADC.

[0081] When the working scenario changes, the system receives the target instruction, indicating that the sampling rate changes, and the interface parameters need to be modified. Assume that at a sampling rate of 9600Msps, L (number of channels) = 16; when working at a decimation of 128, that is, the actual sampling rate is 9600 / 128 = 75Msps, L is adjusted to 1, and the line rate is 75*20 / 1 = 1500Mbps, which meets the minimum line rate requirement of the protocol limit.

[0082] Specifically, modifying the line rate and the number of channels of the core in the channel configurable interface based on the interface parameters and the target clock includes:

[0083] S5: Determine the modified number of channels based on the interface parameters;

[0084] S6: comparing the modified number of channels with the first number;

[0085] S7: reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock.

[0086] For example, Figure 3 As shown in the figure, assuming that when the working scenario changes, 128 extraction needs to be achieved, 9600Msps / 128=75Msps sampling rate, then the interface parameters and core modifications need to be performed, including:

[0087] a) Receiving configuration change instructions;

[0088] b) Reconfigure the clock chip according to the instructions to generate a suitable clock;

[0089] c) Reconfigure the ADC module, change the ADC operating mode and the parameters of the JESD204B transmitter, including the number of channels L;

[0090] d) Modify the line rate and number of lanes L through the dynamic configuration interface of the JESD204 PHY and JESD204 IP core;

[0091] e) Reset the JESD204B protocol controller module and initialize the JESD204B interface link;

[0092] f) The data format conversion module intercepts the corresponding byte data according to the new L value, converts it according to the protocol, and outputs the ADC acquisition data.

[0093] In one embodiment, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0094] S8: when the number of channels after the size relationship representation is modified is greater than the first number, determining the channels and the number of channels that the first group of cores and the second group of cores in the channel configurable interface are responsible for respectively based on the modified number of channels;

[0095] S9: reconfiguring the line rate and number of channels of the first group of cores and the second group of cores based on the target clock and the channels and number of channels that the first group of cores and the second group of cores are responsible for respectively.

[0096] For example, assuming that the first number is 8, when the modified number of channels L=16, since the JESD204 PHY and JESD204 IP core on the FPGA side can only set L=8, two sets of JESD204 PHY and JESD204 IP cores with L=8 need to run in parallel to achieve the working scenario of L=16. The application process includes:

[0097] a) After the system is powered on, the clock chip is configured as needed to generate the clock required for the normal operation of the system;

[0098] b) configuring the ADC chip, configuring the number of channels of the transmitting end of the interface according to the actual L value (16), and configuring the line rate and number of channels of the JESD204 PHY and JESD204 IP cores. The number of channels corresponding to the two cores is the first number of channels;

[0099] c) Initialize the configured JESD204 PHY and JESD204 IP core to enable them to work normally.

[0100] In another embodiment, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0101] S10: when the number of channels after the size relationship representation is modified is less than the first number, determining the number of channels that the first group of cores in the channel configurable interface is responsible for based on the modified number of channels;

[0102] S11: configuring the line rate and number of channels of the first group of cores based on the target clock and the channels and number that the first group of cores are responsible for.

[0103] In this embodiment, the modified number of channels L<8 (the first number), so only one set of JESD204 PHY and JESD204 IP core is needed to realize the transmission of sampled data.

[0104] The reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0105] S12: When the modified number of channels is not greater than the first number and the current number of channels is greater than the first number, signals transmitted in the channel-configurable interface are separated for the first group of cores and the second group of cores, and the line rate and number of channels are configured for the first group of cores in combination with the target clock, so that the first group of cores and the channels corresponding to the first group of cores are used for processing and transmitting sampled data, while data transmitted by the channels corresponding to the second group of cores is ignored.

[0106] For example, when the current number of channels L changes from L>8 (first number) to L≤8, the steps include:

[0107] a) Confirm whether the clock relationship has changed after L is reduced. If so, reconfigure the clock chip. If not, skip this step.

[0108] b) Reconfigure the number of channels of the ADC chip and modify its L value to the new value;

[0109] c) On the FPGA side, the two groups of JESD204 PHY and JESD204 signals involved when the current number of channels L>8 (the first number) are separated, and only the signals of the group of channels with a low channel sequence are concerned, while the related signals of the group of channels with a high channel sequence can be ignored, that is, at this time, only the group of channels corresponding to the low sequence number is used to transmit sampled data, and a group of cores corresponding to the group of channels is in operation for processing sampled data, while the other group of channels and the corresponding cores do not respond;

[0110] d) Complete the JESD204B link initialization so that the configured interface can operate normally.

[0111] Further, configuring the line rate and number of channels of the first group of cores in combination with the target clock includes:

[0112] S13: reconfiguring the synchronization signal circuit parameters in the first group of cores in combination with the target clock and the target sampling rate to modify the current line rate, and modifying the number of channels based on the AXI configuration interface in the first group of cores.

[0113] In addition, the method further comprises:

[0114] S14: determining the adjusted channel for data transmission and the core for data processing;

[0115] S15: obtaining the sampled data transmitted by the channel, and intercepting the sampled data based on the number of bytes of each channel through the core, and then formatting the intercepted sampled data according to the target protocol format to obtain target sampled data matching the sampling point.

[0116] Exemplarily, when the number of channels changes to L≤8 (the first number), the system can modify or reconfigure the parameters and transmit and receive the sampled data through the following process:

[0117] a) Confirm whether the clock relationship has changed after L is reduced. If so, reconfigure the clock chip. If not, skip this step.

[0118] b) Reconfigure the number of channels of the ADC chip and modify its L value to the new value;

[0119] c) On the FPGA side, first configure the JESD204 PHY core according to the new clock relationship, reconfigure the PLL parameters through the AXI / DRP configuration interface of the JESD204 PHY core, modify the line rate, and then reset the JESD204 PHY core;

[0120] d) Modify the parameter configuration about the L value through the AXI configuration interface of the JESD204 IP core. After the configuration is completed, reset the JESD204 core.

[0121] e) Since the original JESD204 PHY and JESD204 IP core are configured according to L=8 (the first number), after the value of L is reconfigured, the sampled data intercepted and output will also change. Taking 4 bytes of data corresponding to each channel as an example, when intercepting the sampled data, it is necessary to start from the low bit of the channel sequence, intercept the low 4*L bytes of data, and then restore the intercepted sampled data to the form of matching sampling points according to the JESD204B protocol format.

[0122] Based on the above method, the dynamic configuration of the number of channels can be realized by utilizing the dynamically configurable interface of JESD204 PHY and JESD204 IP core. Through the dynamic interface and truncation operation, the system can adapt to a wider range of sampling rate changes, ensuring efficient transmission of sampled data without wasting transmission resources.

[0123] In another embodiment, the method further comprises:

[0124] S16: In response to the target instruction, determining whether the current clock matches the target sampling rate in the target instruction;

[0125] S17: If there is no match, the clock chip in the digital-analog conversion system is configured based on the target instruction to generate the target clock.

[0126] For example, in some scenarios, different clocks can cover different ranges of sampling rates, which is related to clock accuracy. When the sampling rate of the system changes within the same range, the corresponding clock can remain unchanged. When it exceeds the range, the clock needs to change. At this time, the system needs to reconfigure the clock chip to generate a corresponding new clock, that is, the target clock. Of course, once the sampling rate changes, no matter how much or how little, the system will update the clock accordingly. Even if the clocks are consistent, the adjustment process will be executed.

[0127] like Figure 4 As shown, another embodiment of the present invention also provides a data transmission device 100, which is applied to a digital-analog conversion system with a channel configurable interface, wherein the digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the device includes:

[0128] A first response module is used to respond to a target instruction, configure the clock chip in the digital-analog conversion system based on the target instruction, and generate a target clock, wherein the target instruction is used to instruct to change the current sampling rate in the digital-analog conversion system to a target sampling rate, and the target clock matches the target sampling rate;

[0129] A first configuration module, configured to configure interface parameters of a channel configurable interface in the digital-analog conversion system according to the target instruction, wherein the interface parameters include the number of interface channels, and the number of interface channels matches the target sampling rate;

[0130] A modification module, used to modify the line rate and number of channels of the core in the channel configurable interface according to the interface parameters and the target clock;

[0131] A transmission module is used to transmit the sampling data of the digital-analog conversion system according to the channel configurable interface after parameter adjustment.

[0132] In some embodiments, the cores in the channel configurable interface include at least two groups, each group of cores is used to process data in a first number of channels;

[0133] The modifying the line rate and the number of channels of the core in the channel configurable interface based on the interface parameters and the target clock includes:

[0134] determining a modified number of channels based on the interface parameters;

[0135] Comparing the modified number of channels with the first number;

[0136] Each group of cores in the channel configurable interface is reconfigured based on the size relationship and the target clock.

[0137] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0138] When the number of channels after the size relationship representation is modified is greater than the first number, determining the channels and the number of channels that the first group of cores and the second group of cores in the channel configurable interface are responsible for respectively based on the modified number of channels;

[0139] Based on the target clock and the channels and the number of channels that the first group of cores and the second group of cores are responsible for, the line rates and the number of channels of the first group of cores and the second group of cores are reconfigured respectively.

[0140] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0141] When the number of channels after the size relationship representation is modified is less than the first number, determining the number of channels that the first group of cores in the channel configurable interface is responsible for based on the modified number of channels;

[0142] The line rate and number of channels of the first group of cores are configured based on the target clock and the channels and number that the first group of cores are responsible for.

[0143] In some embodiments, reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes:

[0144] When the modified number of channels is not greater than the first number and the current number of channels is greater than the first number, the signals transmitted in the channel-configurable interface are separated for the first group of cores and the second group of cores, and the line rate and number of channels are configured for the first group of cores in combination with the target clock, so that the first group of cores and the channels corresponding to the first group of cores are used for processing and transmitting sampled data, while data transmitted by the channels corresponding to the second group of cores is ignored.

[0145] In some embodiments, configuring the line rate and the number of channels of the first group of cores in combination with the target clock includes:

[0146] The synchronization signal circuit parameters in the first group of cores are reconfigured in combination with the target clock and the target sampling rate to modify the current line rate, and the number of channels is modified based on the AXI configuration interface in the first group of cores.

[0147] In some embodiments, the apparatus further comprises:

[0148] A determination module, used to determine the adjusted channel for data transmission and the core for data processing;

[0149] The interception module is used to obtain the sampled data transmitted by the channel, and intercept the sampled data based on the number of bytes of each channel through the core, and then format the intercepted sampled data according to the target protocol format to obtain the target sampled data matching the sampling point.

[0150] In some embodiments, the apparatus further comprises:

[0151] A second response module, configured to respond to a target instruction and determine whether a current clock matches a target sampling rate in the target instruction;

[0152] If there is no match, the clock chip in the digital-analog conversion system is configured based on the target instruction to generate the target clock.

[0153] Another embodiment of the present invention further provides an electronic device, comprising:

[0154] one or more processors;

[0155] a memory configured to store one or more programs;

[0156] When the one or more programs are executed by the one or more processors, the one or more processors implement the data transmission method as described above.

[0157] Furthermore, an embodiment of the present invention also provides a storage medium on which a computer program is stored, and when the program is executed by a processor, the data transmission method described above is implemented. It should be understood that each solution in this embodiment has the corresponding technical effect in the above method embodiment, which will not be repeated here.

[0158] Furthermore, an embodiment of the present invention also provides a computer program product, which is tangibly stored on a computer-readable medium and includes computer-readable instructions, which, when executed, enable at least one processor to perform a data transmission method such as that in the embodiments described above.

[0159] It should be noted that the computer storage medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access storage medium (RAM), a read-only storage medium (ROM), an erasable programmable read-only storage medium (EPROM or flash memory), an optical fiber, a portable compact disk read-only storage medium (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate or transmit a program configured to be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, antenna, optical cable, RF, etc., or any suitable combination of the above.

[0160] In addition, it will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0161] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0162] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0163] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

Claims

1. A data transmission method, applied to a digital-to-analog conversion system having a channel configurable interface, characterized in that: The digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the method includes: In response to a target instruction, a clock chip in the digital-to-analog conversion system is configured based on the target instruction to generate a target clock, wherein the target instruction is used to instruct to change a current sampling rate in the digital-to-analog conversion system to a target sampling rate, and the target clock matches the target sampling rate; Based on the target instruction, configure the interface parameters of the channel configurable interface in the digital-analog conversion system, wherein the interface parameters include the number of channels, and the number of channels of the configured interface matches the target sampling rate; Modifying the line rate and number of channels of the core in the channel configurable interface based on the interface parameters and the target clock; The channel configurable interface transmits the sampled data of the digital-to-analog conversion system based on the adjusted parameters.

2. The data transmission method according to claim 1, characterized in that: The cores in the channel configurable interface include at least two groups, each group of cores is used to process data in a first number of channels; The modifying the line rate and the number of channels of the core in the channel configurable interface based on the interface parameters and the target clock includes: determining a modified number of channels based on the interface parameters; Comparing the modified number of channels with the first number; Each group of cores in the channel configurable interface is reconfigured based on the size relationship and the target clock.

3. The data transmission method according to claim 2, characterized in that: The reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes: When the number of channels after the size relationship representation is modified is greater than the first number, determining the channels and the number of channels that the first group of cores and the second group of cores in the channel configurable interface are responsible for respectively based on the modified number of channels; Based on the target clock and the channels and the number of channels that the first group of cores and the second group of cores are responsible for, the line rates and the number of channels of the first group of cores and the second group of cores are reconfigured respectively.

4. The data transmission method according to claim 2, characterized in that: The reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes: When the modified number of channels represented by the size relationship is less than the first number, determining the channels and number that the first group of cores in the channel configurable interface are responsible for based on the modified number of channels; The line rate and number of channels of the first group of cores are configured based on the target clock and the channels and number that the first group of cores are responsible for.

5. The data transmission method according to claim 2, characterized in that: The reconfiguring each group of cores in the channel configurable interface based on the size relationship and the target clock includes: When the modified number of channels is not greater than the first number and the current number of channels is greater than the first number, the signals transmitted in the channel-configurable interface are separated for the first group of cores and the second group of cores, and the line rate and number of channels are configured for the first group of cores in combination with the target clock, so that the first group of cores and the channels corresponding to the first group of cores are used for processing and transmitting sampled data, while data transmitted by the channels corresponding to the second group of cores is ignored.

6. The data transmission method according to claim 5, characterized in that: The configuring the line rate and the number of channels of the first group of cores in combination with the target clock includes: The synchronization signal circuit parameters in the first group of cores are reconfigured in combination with the target clock and the target sampling rate to modify the current line rate, and the number of channels is modified based on the AXI configuration interface in the first group of cores.

7. The data transmission method according to claim 5, characterized in that: The method further comprises: Determine the adjusted channel for data transmission and the core for data processing; The sampling data transmitted by the channel is obtained, and the sampling data is intercepted by the core based on the number of bytes of each channel, and then the intercepted sampling data is formatted according to the target protocol format to obtain target sampling data matching the sampling point.

8. The data transmission method according to claim 1, characterized in that: The method further comprises: In response to the target instruction, determining whether a current clock matches a target sampling rate in the target instruction; If there is no match, the clock chip in the digital-analog conversion system is configured based on the target instruction to generate the target clock.

9. A data transmission device, applied to a digital-to-analog conversion system with a channel configurable interface, characterized in that: The digital-analog conversion system includes a digital-analog conversion system or an analog-to-digital conversion system, and the device includes: A first response module is used to respond to a target instruction and configure the clock chip in the digital-analog conversion system based on the target instruction to generate a target clock, wherein the target instruction is used to instruct to change the current sampling rate in the digital-analog conversion system to a target sampling rate, and the number of interface channels after configuration matches the target sampling rate; A first configuration module, configured to configure interface parameters of a channel configurable interface in the digital-analog conversion system according to the target instruction, wherein the interface parameters include the number of interface channels, and the number of interface channels matches the target sampling rate; A modification module, used to modify the line rate and number of channels of the core in the channel configurable interface according to the interface parameters and the target clock; A transmission module is used to transmit the sampling data of the digital-analog conversion system according to the channel configurable interface after parameter adjustment.

10. An electronic device, characterized in that: include: one or more processors; a memory configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the data transmission method according to any one of claims 1 to 8.

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