TBC solar cell and preparation method thereof

Abstract

The invention relates to a TBC solar cell and a preparation method thereof. The TBC solar cell comprises a silicon wafer, a P region, an N region and an isolation region are arranged on the back face of the silicon wafer, the P region comprises a first tunneling layer, a second tunneling layer, a first boron-doped polycrystalline silicon layer, a third tunneling layer, a second boron-doped polycrystalline silicon layer, a passivation layer, an antireflection layer and a positive electrode, the N region comprises a fourth tunneling layer, a phosphorus-doped polycrystalline silicon layer, a passivation layer, an antireflection layer and a negative electrode which are sequentially laminated; the isolation region comprises a passivation layer and an antireflection layer which are sequentially laminated; wherein the first tunneling layer, the third tunneling layer and the fourth tunneling layer are silicon dioxide tunneling layers, and the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer. According to the TBC solar cell, ohmic contact of a P region is effectively improved, meanwhile, the carrier tunneling effect is improved, the cell conversion efficiency is excellent, and the application prospect is wide.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, in particular to a TBC solar cell and a preparation method thereof. Background Art

[0002] TBC solar cells are cross-finger back-contact solar cells that combine the excellent tunneling silicon oxide and doped polysilicon interface passivation technology of TOPCon solar cells. The emitter, surface field and metal electrodes are all arranged on the back of the cell and are distributed in a cross-finger manner. There is no grid line blocking the front of the cell, which maximizes the use of incident light, reduces optical losses, achieves more power generation area, improves cell conversion efficiency, and has a more beautiful appearance.

[0003] However, in order to improve the ohmic contact of the P region on the back side of the TBC solar cell, the existing technology usually increases the boron doping concentration of the boron-doped polysilicon layer. When the boron doping concentration is high, the boron element is prone to inward diffusion, thereby reducing the potential difference between the boron-doped polysilicon layer and the silicon wafer, thereby affecting the carrier tunneling effect, making it difficult to further improve the battery conversion efficiency.

[0004] Therefore, there is an urgent need for a TBC solar cell that can improve ohmic contact and simultaneously enhance carrier tunneling effect. Summary of the invention

[0005] Based on this, it is necessary to provide a TBC solar cell and a preparation method thereof to address the above problems. The TBC solar cell provided by the present invention effectively improves the ohmic contact of the P region and improves the carrier tunneling effect, has excellent battery conversion efficiency, and has broad application prospects.

[0006] The present invention provides a TBC solar cell, comprising a silicon wafer, wherein the back side of the silicon wafer has a P region, an N region and an isolation region, wherein the P region comprises a first tunneling layer, a second tunneling layer, a first boron-doped polysilicon layer, a third tunneling layer, a second boron-doped polysilicon layer, a passivation layer, an anti-reflection layer and a positive electrode which are stacked in sequence, the N region comprises a fourth tunneling layer, a phosphorus-doped polysilicon layer, a passivation layer, an anti-reflection layer and a negative electrode which are stacked in sequence, and the isolation region comprises a passivation layer and an anti-reflection layer which are stacked in sequence;

[0007] The first tunneling layer, the third tunneling layer and the fourth tunneling layer are all silicon dioxide tunneling layers, and the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer.

[0008] In one embodiment, the thickness of the first boron-doped polysilicon layer is less than the thickness of the second boron-doped polysilicon layer;

[0009] And / or, the boron doping concentration of the first boron doped polysilicon layer is less than the boron doping concentration of the second boron doped polysilicon layer.

[0010] In one embodiment, the thickness of the first boron-doped polysilicon layer is 30 nm to 50 nm, and the thickness of the second boron-doped polysilicon layer is 150 nm to 350 nm;

[0011] And / or, the boron doping concentration of the first boron-doped polysilicon layer is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

[0012] In one embodiment, the thickness of the first tunneling layer is greater than the thickness of the third tunneling layer.

[0013] In one embodiment, the thickness of the first tunneling layer is 3 nm to 6 nm, and the thickness of the third tunneling layer is 1 nm to 3 nm.

[0014] In one embodiment, the thickness of the aluminum oxide tunneling layer is 1 nm to 3 nm;

[0015] And / or, the thickness of the silicon nitride tunneling layer is 5 nm to 10 nm.

[0016] In one embodiment, the thickness of the fourth tunneling layer is 1.5 nm to 2.5 nm;

[0017] And / or, the thickness of the phosphorus-doped polysilicon layer is 120 nm to 320 nm;

[0018] And / or, the phosphorus doping concentration of the phosphorus doped polysilicon layer is 2E 20 cm -3 ~4.5E 20 cm -3 .

[0019] In one embodiment, the boron diffusion concentration in the P region is 1E 17 cm -3 ~1E 18 cm -3 , the inner expansion depth is 150nm~250nm;

[0020] And / or, in the N region, the internal diffusion concentration of phosphorus is 1E 16 cm -3 ~1E 18 cm -3 The internal expansion depth is 200nm~300nm.

[0021] In one embodiment, the thickness of the silicon wafer in the P region is greater than the thickness of the silicon wafer in the N region, and the thickness difference is 2.5 μm to 4.5 μm;

[0022] And / or, the thickness of the silicon wafer in the N region is greater than the thickness of the silicon wafer in the isolation region, and the thickness difference is 2.5 μm to 4.5 μm.

[0023] In the above-mentioned TBC solar cell, on the one hand, the first tunneling layer and the first boron-doped polysilicon layer effectively block the boron element from diffusing into the silicon wafer, which can not only ensure the potential difference between the second boron-doped polysilicon layer and the silicon wafer, improve the tunneling effect of the carriers, thereby improving the passivation effect of the battery, but also enable the second boron-doped polysilicon layer to have a higher boron doping concentration, effectively improve the ohmic contact of the P region, thereby improving the short-circuit current, open-circuit voltage and fill factor, and thus improving the battery conversion efficiency; on the other hand, the second tunneling layer is conducive to the accumulation and transmission of carriers, improves the tunneling effect of the carriers, thereby improving the passivation effect of the battery.

[0024] Therefore, the TBC solar cell of the present invention effectively improves the ohmic contact of the P region and simultaneously improves the carrier tunneling effect, has excellent cell conversion efficiency, and has broad application prospects.

[0025] The present invention also provides a method for preparing the TBC solar cell as described above, comprising the following steps:

[0026] S1, double-sided polishing of silicon wafer;

[0027] S2, sequentially depositing a first tunneling layer and a second tunneling layer on the back side of the silicon wafer;

[0028] S3, depositing a first polysilicon layer, a third tunneling layer and a second polysilicon layer in sequence on the back side of the silicon wafer by low pressure chemical vapor deposition;

[0029] S4, performing high temperature annealing on the back side of the silicon wafer and performing a first wet etching to remove the oxide layer grown on the surface of the second polysilicon layer;

[0030] S5, performing boron diffusion on the back side of the silicon wafer to form a first boron-doped polysilicon layer and a second boron-doped polysilicon layer;

[0031] S6, performing the first laser grooving on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region;

[0032] S7, performing a second wet etching on the back side of the silicon wafer to remove all layers on the silicon wafer in the N region and the isolation region;

[0033] S8, depositing a fourth tunneling layer and a phosphorus-doped polysilicon layer in sequence on the back side of the silicon wafer;

[0034] S9, performing a second laser grooving on the back of the silicon wafer to remove the phosphorus silicon glass layer in the P region and the isolation region;

[0035] S10, performing a third wet etching on the front side of the silicon wafer to remove all the layers of the front side and side plating;

[0036] S11, performing a fourth wet etching on the back side of the silicon wafer to remove all layers on the second boron-doped polysilicon layer in the P region and to remove all layers on the silicon wafer in the isolation region;

[0037] S12, the silicon wafer is textured on both sides and the phosphorus silicon glass layer in the N region is removed;

[0038] S13, preparing a passivation layer and an anti-reflection layer on both sides of the silicon wafer;

[0039] S14. Prepare a positive electrode and a negative electrode on the back side of the silicon wafer.

[0040] In the above preparation method, high temperature annealing is performed after the low pressure chemical vapor deposition process, which effectively optimizes the structures of the first polysilicon layer, the second polysilicon layer, the first tunneling layer and the third tunneling layer, thereby improving the conversion efficiency of the prepared TBC solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 Schematic diagram of the structure of a TBC solar cell according to one embodiment of the present invention.

[0043] Figure numerals: 1, silicon wafer; 2, first tunneling layer; 3, second tunneling layer; 31, aluminum oxide tunneling layer; 32, silicon nitride tunneling layer; 41, first boron-doped polysilicon layer; 42, second boron-doped polysilicon layer; 5, third tunneling layer; 6, fourth tunneling layer; 7, phosphorus-doped polysilicon layer; 8, passivation layer; 9, anti-reflection layer; 10, positive electrode; 11, negative electrode. DETAILED DESCRIPTION

[0044] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0046] like Figure 1 As shown, a TBC solar cell structure provided in an embodiment of the present invention comprises a silicon wafer 1, wherein the back side of the silicon wafer 1 comprises a P region, an N region and an isolation region, wherein the P region comprises a first tunneling layer 2, an aluminum oxide tunneling layer 31, a silicon nitride tunneling layer 32, a first boron-doped polysilicon layer 41, a third tunneling layer 5, a second boron-doped polysilicon layer 42, a passivation layer 8, an anti-reflection layer 9 and a positive electrode 10 which are sequentially stacked, wherein the N region comprises a fourth tunneling layer 6, a phosphorus-doped polysilicon layer 7, a passivation layer 8, an anti-reflection layer 9 and a negative electrode 11 which are sequentially stacked, and wherein the isolation region comprises a passivation layer 8 and an anti-reflection layer 9 which are sequentially stacked;

[0047] The first tunneling layer 2 , the third tunneling layer 5 and the fourth tunneling layer 6 are all silicon dioxide tunneling layers.

[0048] It can be understood that the second tunneling layer 3 of the present invention can be a stack of an aluminum oxide tunneling layer 31 and a silicon nitride tunneling layer 32, or an aluminum oxide tunneling layer 31 or a silicon nitride tunneling layer 32, and the stacking positions of the aluminum oxide tunneling layer 31 and the silicon nitride tunneling layer 32 in the second tunneling layer 3 can be interchanged.

[0049] In the above-mentioned TBC solar cell, on the one hand, the first tunneling layer 2 and the first boron-doped polysilicon layer 41 effectively block the boron element from diffusing into the silicon wafer 1, which can not only ensure the potential difference between the second boron-doped polysilicon layer 42 and the silicon wafer 1, improve the tunneling effect of the carriers, thereby improving the battery passivation effect, but also enable the second boron-doped polysilicon layer 42 to have a higher boron doping concentration, effectively improve the ohmic contact of the P region, thereby improving the short-circuit current, open-circuit voltage and fill factor, and thus improve the battery conversion efficiency; on the other hand, the second tunneling layer 3 is conducive to the accumulation and transmission of carriers, improves the tunneling effect of the carriers, thereby improving the battery passivation effect.

[0050] Therefore, the TBC solar cell of the present invention effectively improves the ohmic contact of the P region and simultaneously improves the carrier tunneling effect, has excellent cell conversion efficiency, and has broad application prospects.

[0051] It should be noted that the silicon wafer 1 is selected from an N-type silicon wafer or a P-type silicon wafer, preferably an N-type silicon wafer.

[0052] In one embodiment, the thickness of the first boron-doped polysilicon layer 41 is less than the thickness of the second boron-doped polysilicon layer 42, which further improves the contact resistance and helps to block the internal expansion of the boron element, thereby improving the carrier tunneling effect and further improving the passivation effect.

[0053] Preferably, the thickness of the first boron-doped polysilicon layer 41 is 30 nm to 50 nm, and the thickness of the second boron-doped polysilicon layer 42 is 150 nm to 350 nm.

[0054] In one embodiment, the boron doping concentration of the first boron-doped polysilicon layer 41 is less than the boron doping concentration of the second boron-doped polysilicon layer 42, which further improves the contact resistance and is beneficial to increase the potential difference between the second boron-doped polysilicon layer 42 and the silicon wafer 1, thereby improving the carrier tunneling effect and further improving the passivation effect.

[0055] Preferably, the boron doping concentration of the first boron-doped polysilicon layer 41 is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer 42 is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

[0056] In one embodiment, the thickness of the first tunneling layer 2 is greater than the thickness of the third tunneling layer 5 , which is beneficial to further improve the passivation effect, thereby improving the conversion efficiency of the TBC solar cell.

[0057] Preferably, the thickness of the first tunneling layer 2 is 3 nm to 6 nm, and the thickness of the third tunneling layer 5 is 1 nm to 3 nm.

[0058] Specifically, in the P region, the concentration of boron diffusion is 1E 17 cm -3 ~1E 18 cm -3 The inner expansion depth is 150nm to 250nm, which is beneficial to increase the potential difference between the second boron-doped polysilicon layer 42 and the silicon wafer 1, thereby improving the carrier tunneling effect and further improving the passivation effect.

[0059] In one embodiment, the thickness of the aluminum oxide tunneling layer 31 is 1 nm to 3 nm. The aluminum oxide tunneling layer 31 carries a negative charge, which further promotes the accumulation and transmission of carriers and improves the carrier tunneling effect, thereby further improving the conversion efficiency of the TBC solar cell.

[0060] In one embodiment, the silicon nitride tunneling layer 32 has a thickness of 5 nm to 10 nm. The silicon nitride tunneling layer 32 can effectively block further inward expansion of boron and reduce recombination, thereby further improving the conversion efficiency of the TBC solar cell.

[0061] In one embodiment, the thickness of the fourth tunneling layer 6 is 1.5 nm to 2.5 nm, including but not limited to any point value among 1.5 nm, 1.6 nm, 1.8 nm, 2 nm, 2.1 nm, 2.3 nm, and 2.5 nm, or a range value between any two of them.

[0062] In one embodiment, the thickness of the phosphorus-doped polysilicon layer 7 is 120nm to 320nm, including but not limited to any point value among 120nm, 125nm, 150nm, 180nm, 200nm, 230nm, 250nm, 280nm, 300nm, 310nm, and 320nm or a range value between any two of them.

[0063] Preferably, the phosphorus doping concentration of the phosphorus-doped polysilicon layer 7 is 2E 20 cm -3 ~4.5E 20 cm -3 .

[0064] In one embodiment, the internal diffusion concentration of phosphorus in the N region is 1E 16 cm -3 ~1E 18 cm -3 The internal expansion depth is 200nm~300nm.

[0065] In one embodiment, the thickness of the silicon wafer 1 in the P region is greater than the thickness of the silicon wafer 1 in the N region, and the thickness difference is 2.5μm to 4.5μm. The thickness of the silicon wafer 1 in the N region is greater than the thickness of the silicon wafer 1 in the isolation region, and the thickness difference is 2.5μm to 4.5μm, which is conducive to forming insulation isolation.

[0066] It should be noted that the present invention has no special restrictions on the materials and thicknesses of the passivation layer 8 and the anti-reflection layer 9. For example, the passivation layer 8 is an aluminum oxide layer, the anti-reflection layer 9 is a silicon nitride layer, the thickness of the passivation layer 8 is 3nm to 5nm, the thickness of the anti-reflection layer 9 on the front side of the silicon wafer 1 is 70nm to 80nm, and the thickness of the anti-reflection layer 9 on the back side is 80nm to 120nm.

[0067] The present invention also provides a method for preparing the TBC solar cell as described above, comprising the following steps:

[0068] S1, silicon wafer 1 is double-sided polished;

[0069] S2, sequentially depositing a first tunneling layer 2 and a second tunneling layer 3 on the back side of the silicon wafer 1;

[0070] S3, depositing a first polysilicon layer, a third tunneling layer 5 and a second polysilicon layer in sequence on the back side of the silicon wafer 1 by low pressure chemical vapor deposition;

[0071] S4, performing high temperature annealing on the back side of the silicon wafer 1, and performing a first wet etching to remove the oxide layer grown on the surface of the second polysilicon layer;

[0072] S5, performing boron diffusion on the back side of the silicon wafer 1 to form a first boron-doped polysilicon layer 41 and a second boron-doped polysilicon layer 42;

[0073] S6, performing the first laser grooving on the back side of the silicon wafer 1 to remove the borosilicate glass layer in the N region and the isolation region;

[0074] S7, performing a second wet etching on the back side of the silicon wafer 1 to remove all layers on the silicon wafer 1 in the N region and the isolation region;

[0075] S8, depositing a fourth tunneling layer 6 and a phosphorus-doped polysilicon layer 7 on the back side of the silicon wafer 1 in sequence;

[0076] S9, performing a second laser grooving on the back of the silicon wafer 1 to remove the phosphorus silicon glass layer in the P region and the isolation region;

[0077] S10, performing a third wet etching on the front side of the silicon wafer 1 to remove all the layers plated on the front side and the side surfaces;

[0078] S11, performing a fourth wet etching on the back side of the silicon wafer 1 to remove all layers on the second boron-doped polysilicon layer 42 in the P region and to remove all layers on the silicon wafer 1 in the isolation region;

[0079] S12, performing double-sided texturing on the silicon wafer 1 and removing the phosphorus silicon glass layer in the N region;

[0080] S13, a passivation layer 8 and an anti-reflection layer 9 are prepared on both sides of the silicon wafer 1;

[0081] S14, a positive electrode 10 and a negative electrode 11 are prepared on the back side of the silicon wafer 1.

[0082] In the above preparation method, after the low-pressure chemical vapor deposition process, the first polysilicon layer and the second polysilicon layer are further crystallized by high-temperature annealing, and the crystal size is increased, which is beneficial to improving the ohmic contact. In addition, the tunneling pinhole density of the first tunneling layer 2 and the third tunneling layer 5 is increased, thereby improving the carrier tunneling effect, thereby improving the conversion efficiency of the prepared TBC solar cell.

[0083] In one embodiment, in step S1, the tower base of the silicon wafer 1 after double-side polishing is 10 μm to 30 μm.

[0084] It should be noted that the present invention adopts the existing method to deposit the tunneling layer and the polysilicon layer. For example, the silicon dioxide layer can be prepared by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD) or atomic layer deposition (ALD), the polysilicon layer can be prepared by LPCVD or PECVD, the aluminum oxide layer is prepared by ALD, and the silicon nitride layer is prepared by PECVD. The present invention does not elaborate on this.

[0085] In one embodiment, the temperature of the high temperature annealing treatment is 1000° C. to 1050° C., and the thickness of the formed oxide layer is 15 nm to 18 nm.

[0086] In one embodiment, the thickness of the borosilicate glass layer is 40 nm to 70 nm.

[0087] In one embodiment, the thickness of the phosphosilicate glass layer is 30 nm to 50 nm.

[0088] In steps S6 and S7, the borosilicate glass layer in the N region and the isolation region is removed by laser grooving and wet etching, and then all layers on the silicon wafer 1 are removed, while the P region is not corroded under the protection of the borosilicate glass layer.

[0089] Preferably, during the second wet etching, all layers on the silicon wafer 1 in the N region and the isolation region are removed while etching to a certain depth of the silicon wafer 1, the depth being 2.5 μm to 4.5 μm.

[0090] It should be noted that the laser used in the first laser grooving and the second laser grooving may be a picosecond laser or a femtosecond laser.

[0091] In step 11, all layers on the second boron-doped polysilicon layer 42 in the P region are removed by wet etching, and all layers on the silicon wafer 1 in the isolation region are removed. Then, in step S12, double-sided texturing is performed to form a textured surface on the front and back isolation regions of the silicon wafer 1, and finally the phosphosilicate glass layer in the N region is removed.

[0092] Preferably, during the fourth wet etching, while removing all layers on the silicon wafer 1 in the isolation region, etching is performed to a certain depth of the silicon wafer 1, which is 2.5 μm to 4.5 μm, which is conducive to physical isolation of the P region and the N region.

[0093] In one embodiment, in the velvet surface of the isolation regions on the front and back sides of the silicon wafer 1 , the width of the tower base is 1.2 μm to 1.5 μm, the tower height is 1 μm to 1.2 μm, and the reflectivity is 8% to 10%.

[0094] The TBC solar cell and its preparation method will be further described below through the following specific examples. However, those skilled in the art will understand that the following examples are only used to illustrate the present invention and should not be considered to limit the scope of the present invention. If no specific conditions are specified in the examples, the conventional conditions or the conditions recommended by the manufacturer are followed. The reagents or instruments used without indicating the manufacturer are all conventional products that can be purchased commercially.

[0095] Example 1

[0096] S1, double-sided polishing of silicon wafer;

[0097] S2, depositing a 5 nm first tunneling layer, a 3 nm aluminum oxide tunneling layer, and a 10 nm silicon nitride tunneling layer on the back side of the silicon wafer in sequence;

[0098] S3, depositing a 35nm first polysilicon layer, a 2nm third tunneling layer and a 280nm second polysilicon layer on the back side of the silicon wafer in sequence by low pressure chemical vapor deposition;

[0099] S4, performing high temperature annealing on the back side of the silicon wafer at a temperature of 1000° C., and performing a first wet etching to remove the oxide layer grown on the surface of the second polysilicon layer, the thickness of which is 15 nm;

[0100] S5, the back of the silicon wafer is expanded with boron to form the first boron-doped polysilicon layer (boron doping concentration is 2E 19 cm -3 ) and the second boron-doped polysilicon layer (boron doping concentration is 4E 19 cm -3 ), the internal diffusion concentration of boron is 5E 17 cm -3 , the inner expansion depth is 150nm;

[0101] S6, performing the first laser grooving on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region;

[0102] S7, the back side of the silicon wafer is wet-etched for the second time to remove all layers on the silicon wafer in the N region and the isolation region, and to etch part of the silicon wafer so that the difference in thickness between the silicon wafer in the P region and the silicon wafer in the N region is 3 μm;

[0103] S8, a 2nm fourth tunneling layer and a 300nm phosphorus-doped polysilicon layer (phosphorus doping concentration is 3E) are sequentially deposited on the back of the silicon wafer. 19 cm -3 ), the internal concentration of phosphorus is 3E 17 cm -3 , the inner expansion depth is 200nm;

[0104] S9, performing a second laser grooving on the back of the silicon wafer to remove the phosphorus silicon glass layer in the P region and the isolation region;

[0105] S10, performing a third wet etching on the front side of the silicon wafer to remove all the layers of the front side and side plating;

[0106] S11, the back side of the silicon wafer is wet-etched for the fourth time to remove all layers on the second boron-doped polysilicon layer in the P region, remove all layers on the silicon wafer in the isolation region, and etch part of the silicon wafer, so that the difference in thickness between the silicon wafer in the N region and the silicon wafer in the isolation region is 3 μm;

[0107] S12, the silicon wafer is textured on both sides and the phosphorus silicon glass layer in the N region is removed;

[0108] S13, a 3nm aluminum oxide passivation layer and an 80nm silicon nitride anti-reflection layer are prepared on both sides of the silicon wafer;

[0109] S14. Prepare a positive electrode in the P region on the back side of the silicon wafer and a negative electrode in the N region.

[0110] Example 2

[0111] The difference between Example 2 and Example 1 is that in step S2, a 5 nm first tunneling layer, a 1.5 nm aluminum oxide tunneling layer, and a 5 nm silicon nitride tunneling layer are sequentially deposited;

[0112] In step S3, a first polysilicon layer of 35 nm, a third tunneling layer of 2 nm, and a second polysilicon layer of 280 nm are sequentially deposited;

[0113] In step S5, the first boron-doped polysilicon layer (boron doping concentration is 1.8E 19 cm -3 ) and the second boron-doped polysilicon layer (boron doping concentration is 3.5E 19 cm -3 ), the internal diffusion concentration of boron is 6E 17 cm -3 , the inner expansion depth is 170nm;

[0114] In step S7, the difference between the thickness of the silicon wafer in the P region and the thickness of the silicon wafer in the N region is 3 μm.

[0115] Example 3

[0116] The difference between Example 3 and Example 1 is that in step S2, a 2nm first tunneling layer, a 3nm silicon nitride tunneling layer and a 10nm aluminum oxide tunneling layer are sequentially deposited;

[0117] In step S3, a first polysilicon layer of 35 nm, a third tunneling layer of 2 nm, and a second polysilicon layer of 280 nm are sequentially deposited;

[0118] In step S11 , the difference in silicon wafer thickness between the N region and the isolation region is 3 μm.

[0119] Example 4

[0120] The difference between Example 4 and Example 1 is that in step S2, a 6 nm first tunneling layer and a 10 nm silicon nitride tunneling layer are sequentially deposited without an aluminum oxide tunneling layer.

[0121] Example 5

[0122] The difference between Example 5 and Example 1 is that in step S2, a 5 nm first tunneling layer and a 3 nm aluminum oxide tunneling layer are sequentially deposited without a silicon nitride tunneling layer.

[0123] Comparative Example 1

[0124] The difference between Comparative Example 1 and Example 1 is that in step S2, only a first tunneling layer of 6 nm is deposited.

[0125] Comparative Example 2

[0126] The difference between Comparative Example 2 and Example 1 is that in step S3, only a first polysilicon layer of 360 nm is deposited.

[0127] The performance of the TBC solar cells prepared in all embodiments and comparative examples was tested using a Halm tester to measure the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and conversion efficiency (Eta). All test results are shown in Table 1.

[0128] Table 1

[0129]

[0130]

[0131] According to the results in Table 1, the TBC solar cells prepared in all embodiments have high cell conversion efficiency, and high open circuit voltage, short circuit current density, and fill factor, while the conversion efficiency, open circuit voltage, short circuit current density, and fill factor of the TBC solar cells in all comparative examples are significantly lower. Therefore, the TBC solar cell provided by the present invention effectively improves the ohmic contact of the P region and improves the carrier tunneling effect, has excellent cell conversion efficiency, and has broad application prospects.

[0132] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A TBC solar cell, comprising a silicon wafer, wherein the back side of the silicon wafer has a P region, an N region and an isolation region, characterized in that: The P region includes a first tunneling layer, a second tunneling layer, a first boron-doped polysilicon layer, a third tunneling layer, a second boron-doped polysilicon layer, a passivation layer, an anti-reflection layer and a positive electrode which are stacked in sequence, the N region includes a fourth tunneling layer, a phosphorus-doped polysilicon layer, a passivation layer, an anti-reflection layer and a negative electrode which are stacked in sequence, and the isolation region includes a passivation layer and an anti-reflection layer which are stacked in sequence; The first tunneling layer, the third tunneling layer and the fourth tunneling layer are all silicon dioxide tunneling layers, and the second tunneling layer is at least one of an aluminum oxide tunneling layer and a silicon nitride tunneling layer.

2. The TBC solar cell according to claim 1, characterized in that: The thickness of the first boron-doped polysilicon layer is less than the thickness of the second boron-doped polysilicon layer; And / or, the boron doping concentration of the first boron doped polysilicon layer is less than the boron doping concentration of the second boron doped polysilicon layer.

3. The TBC solar cell according to claim 1 or 2, characterized in that: The thickness of the first boron-doped polysilicon layer is 30nm-50nm, and the thickness of the second boron-doped polysilicon layer is 150nm-350nm; And / or, the boron doping concentration of the first boron-doped polysilicon layer is 1.5E 19 cm -3 ~2.5E 19 cm -3 The boron doping concentration of the second boron-doped polysilicon layer is 2.5E 19 cm -3 ~4.5E 19 cm -3 .

4. The TBC solar cell according to claim 1, characterized in that: The thickness of the first tunneling layer is greater than the thickness of the third tunneling layer.

5. The TBC solar cell according to claim 1 or 4, characterized in that: The thickness of the first tunneling layer is 3 nm to 6 nm, and the thickness of the third tunneling layer is 1 nm to 3 nm.

6. The TBC solar cell according to claim 1, characterized in that: The thickness of the aluminum oxide tunneling layer is 1 nm to 3 nm; And / or, the thickness of the silicon nitride tunneling layer is 5 nm to 10 nm.

7. The TBC solar cell according to claim 1, characterized in that: The thickness of the fourth tunneling layer is 1.5 nm to 2.5 nm; And / or, the thickness of the phosphorus-doped polysilicon layer is 120 nm to 320 nm; And / or, the phosphorus doping concentration of the phosphorus doped polysilicon layer is 2E 20 cm -3 ~4.5E 20 cm -3 .

8. The TBC solar cell according to claim 1, characterized in that: In the P region, the concentration of boron diffusion is 1E 17 cm -3 ~1E 18 cm -3 , the inner expansion depth is 150nm~250nm; And / or, in the N region, the internal diffusion concentration of phosphorus is 1E 16 cm -3 ~1E 18 cm -3 The internal expansion depth is 200nm~300nm.

9. The TBC solar cell according to claim 1, characterized in that: The thickness of the silicon wafer in the P region is greater than that of the silicon wafer in the N region, and the thickness difference is 2.5 μm to 4.5 μm; And / or, the thickness of the silicon wafer in the N region is greater than the thickness of the silicon wafer in the isolation region, and the thickness difference is 2.5 μm to 4.5 μm.

10. A method for preparing a TBC solar cell according to any one of claims 1 to 9, characterized in that: The preparation method comprises the following steps: S1, double-sided polishing of silicon wafer; S2, sequentially depositing a first tunneling layer and a second tunneling layer on the back side of the silicon wafer; S3, depositing a first polysilicon layer, a third tunneling layer and a second polysilicon layer in sequence on the back side of the silicon wafer by low pressure chemical vapor deposition; S4, performing high temperature annealing on the back side of the silicon wafer and performing a first wet etching to remove the oxide layer grown on the surface of the second polysilicon layer; S5, performing boron diffusion on the back side of the silicon wafer to form a first boron-doped polysilicon layer and a second boron-doped polysilicon layer; S6, performing the first laser grooving on the back of the silicon wafer to remove the borosilicate glass layer in the N region and the isolation region; S7, performing a second wet etching on the back side of the silicon wafer to remove all layers on the silicon wafer in the N region and the isolation region; S8, depositing a fourth tunneling layer and a phosphorus-doped polysilicon layer in sequence on the back side of the silicon wafer; S9, performing a second laser grooving on the back of the silicon wafer to remove the phosphorus silicon glass layer in the P region and the isolation region; S10, performing a third wet etching on the front side of the silicon wafer to remove all the layers of the front side and side plating; S11, performing a fourth wet etching on the back side of the silicon wafer to remove all layers on the second boron-doped polysilicon layer in the P region and to remove all layers on the silicon wafer in the isolation region; S12, the silicon wafer is textured on both sides and the phosphorus silicon glass layer in the N region is removed; S13, preparing a passivation layer and an anti-reflection layer on both sides of the silicon wafer; S14. Prepare a positive electrode and a negative electrode on the back side of the silicon wafer.

Images