Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. A pixel circuit is arranged in the array substrate, and the pixel circuit comprises a storage capacitor and a compensation transistor; the storage capacitor comprises a first capacitor plate; the array substrate comprises a substrate, a first conductive layer, a first active layer and a first connecting line, the first conductive layer is located on one side of the substrate; the first capacitor plate is located on the first conductive layer. The first active layer is located on the side, away from the substrate, of the first conductive layer and comprises a first active part of the compensation transistor; the first connecting line is located on the side, away from the substrate, of the first active layer; the first active part is connected with a first connecting line through a first via hole, and the first connecting line is connected with a first capacitor plate; the orthographic projection of the first via hole on the substrate is at least partially overlapped with the orthographic projection of the first capacitor plate on the substrate. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the rapid development of display technology, the application of display products using organic light emitting devices (OLED) is becoming more and more widespread.

[0003] However, the performance of current OLED display panels needs to be improved. Summary of the invention

[0004] The present invention provides an array substrate and a display panel to improve the performance of the display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, wherein a pixel circuit is disposed in the array substrate, wherein the pixel circuit comprises a storage capacitor and a compensation transistor; the storage capacitor comprises a first capacitor plate;

[0006] The array substrate comprises:

[0007] substrate;

[0008] A first conductive layer is located on one side of the substrate; the first capacitor plate is located on the first conductive layer;

[0009] A first active layer, located on a side of the first conductive layer away from the substrate, the first active layer comprising a first active portion of the compensation transistor;

[0010] A first connecting line is located on a side of the first active layer away from the substrate; the first active portion is connected to the first connecting line through a first via hole, and the first connecting line is connected to the first capacitor plate; the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the first capacitor plate on the substrate.

[0011] Optionally, an orthographic projection of the first via hole on the substrate is located within an orthographic projection of the first capacitor plate on the substrate.

[0012] Optionally, the array substrate further includes: a power connection line;

[0013] The first active portion includes a first channel region and a first electrode of the compensation transistor; the first electrode is connected to the first connection line; the first electrode includes a first portion and a second portion;

[0014] The first channel region, the first portion and the second portion are arranged along a first direction and extend along the first direction; an orthographic projection of the second portion on the substrate overlaps with an orthographic projection of the power connection line on the substrate and overlaps with an orthographic projection of the first capacitor plate on the substrate;

[0015] Preferably, the length of the first portion in the second direction is the same as the length of the first channel region in the second direction, and the length of the second portion in the second direction is greater than the length of the first portion in the second direction; wherein the first direction intersects the second direction;

[0016] Preferably, the second portion includes a first sub-portion, a second sub-portion and a third sub-portion arranged along the first direction; the orthographic projection of the second sub-portion on the substrate overlaps with the orthographic projection of the power connection line on the substrate; the orthographic projection of the third sub-portion on the substrate overlaps with the orthographic projection of the first capacitor plate on the substrate;

[0017] The length of the first sub-portion in the second direction gradually increases along the first direction;

[0018] The length of the second sub-portion in the second direction is the same as the maximum length of the first sub-portion in the second direction;

[0019] A length of the third sub-portion in the second direction is greater than a length of the second sub-portion in the second direction.

[0020] Optionally, the storage capacitor further includes a second capacitor plate;

[0021] The array substrate further includes:

[0022] A power connection line and a power line, wherein the power connection line is connected between the second capacitor plate and the power line; the power line extends along the first direction, and the power connection line extends along the second direction;

[0023] Preferably, the power connection line is arranged on the same layer as the second capacitor plate.

[0024] Optionally, the first connecting line is connected to the first capacitor plate through a second via hole, and the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the first capacitor plate on the substrate.

[0025] Optionally, the pixel circuit further includes a first reset transistor;

[0026] The first active layer further includes a second active portion of the first reset transistor; the first active portion includes a first electrode, a second electrode and a first channel region of the compensation transistor; the first electrode is connected to the first connection line;

[0027] The second active portion includes a second channel region of the first reset transistor, a third electrode and a fourth electrode; the third electrode is connected to the second electrode, and the fourth electrode is connected to the first reset signal line;

[0028] Preferably, the third electrode is reused as the second electrode;

[0029] Preferably, the array substrate further includes:

[0030] A first scan line and a second scan line; located on a side of the first capacitor plate away from the substrate and extending along a second direction; an orthographic projection of the first scan line on the substrate partially overlaps with an orthographic projection of the first channel region on the substrate; an orthographic projection of the second scan line on the substrate partially overlaps with an orthographic projection of the second channel region on the substrate;

[0031] Preferably, the storage capacitor further includes a second capacitor plate;

[0032] The array substrate further includes:

[0033] A power connection line and a power line, wherein the power connection line is connected between the second capacitor plate and the power line; the power line extends along a first direction, and the power connection line extends along a second direction;

[0034] The first scanning line and the power connection line are arranged in the same layer;

[0035] Along the first direction, a distance between the first scanning line and the power connection line is less than 3 micrometers.

[0036] Optionally, the pixel circuit further includes a driving transistor and a data writing transistor;

[0037] The array substrate further includes:

[0038] a third scanning line and a second connecting line; the third scanning line extends along the second direction;

[0039] Along the first direction, the orthographic projection of the third scanning line on the substrate is located between the orthographic projection of the first scanning line on the substrate and the orthographic projection of the second scanning line on the substrate;

[0040] The second electrode is connected to the second connection line through a third via hole, and the second connection line is connected to the first electrode of the driving transistor; the orthographic projection of the third via hole on the substrate at least partially overlaps with the orthographic projection of the third scanning line on the substrate;

[0041] Preferably, the third scanning line is arranged in the same layer as the first capacitor plate;

[0042] Preferably, the second connecting line is arranged in the same layer as the first connecting line;

[0043] Preferably, the array substrate further includes:

[0044] A second active layer is located on one side of the substrate and on a side of the first capacitor plate close to the substrate; the second active layer includes a third channel region, a fifth electrode and a sixth electrode of the driving transistor; the fifth electrode is the first electrode of the driving transistor;

[0045] The second active layer further includes a fourth channel region, a seventh electrode and an eighth electrode of the data writing transistor;

[0046] The orthographic projection of the third scanning line on the substrate partially overlaps with the orthographic projection of the fourth channel region on the substrate;

[0047] The seventh electrode is connected to the sixth electrode, and the eighth electrode is connected to the data line;

[0048] Preferably, the first capacitor plate is reused as the gate of the driving transistor.

[0049] Optionally, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor;

[0050] The array substrate further includes:

[0051] a light emitting control line, located on a side of the second active layer away from the substrate and extending along a second direction;

[0052] The second active layer further includes a fifth channel region, a ninth electrode and a tenth electrode of the first light emission control transistor;

[0053] The orthographic projection of the fifth channel region on the substrate partially overlaps with the orthographic projection of the light emitting control line on the substrate;

[0054] The ninth electrode is reused as the fifth electrode, and the tenth electrode is connected to the first electrode of the light emitting element;

[0055] The second active layer further includes a sixth channel region, an eleventh electrode and a twelfth electrode of the second light emission control transistor;

[0056] The orthographic projection of the sixth channel region on the substrate partially overlaps with the orthographic projection of the light emitting control line on the substrate;

[0057] The eleventh electrode is connected to the sixth electrode; the twelfth electrode is connected to the power line;

[0058] Preferably, the storage capacitor further includes a second capacitor plate;

[0059] The array substrate further includes:

[0060] A third connecting line, the third connecting line is connected between the second capacitor plate and the power line;

[0061] Preferably, the array substrate further includes:

[0062] a fourth connecting line connected between the third connecting line and the twelfth electrode;

[0063] Preferably, two pixel circuits adjacent to each other along the second direction share one fourth connecting line.

[0064] Optionally, the pixel circuit further includes a second reset transistor and a third reset transistor;

[0065] The array substrate further includes:

[0066] a fourth scanning line, located at a side of the second active layer away from the substrate and extending along the second direction;

[0067] A third reset signal line is located at a side of the film layer where the fourth scan line is located away from the substrate and extends along the second direction;

[0068] A second reset signal line is located at a side of the film layer where the third reset signal line is located away from the substrate and extends along the second direction;

[0069] The second active layer further includes a seventh channel region, a thirteenth electrode and a fourteenth electrode of the second reset transistor;

[0070] The orthographic projection of the seventh channel region on the substrate partially overlaps with the orthographic projection of the fourth scanning line on the substrate;

[0071] The thirteenth electrode is connected to the tenth electrode, and the fourteenth electrode is connected to the second reset signal line;

[0072] The second active layer further includes an eighth channel region, a fifteenth electrode and a sixteenth electrode of the third reset transistor;

[0073] The orthographic projection of the eighth channel region on the substrate partially overlaps with the orthographic projection of the fourth scanning line on the substrate;

[0074] The array substrate further includes a fifth connecting line, the fifteenth electrode is connected to the fifth electrode through the fifth connecting line, and the sixteenth electrode is connected to the third reset signal line;

[0075] Preferably, the array substrate further comprises a sixth connecting line, wherein the sixth connecting line is connected between the sixteenth electrode and the third reset signal line;

[0076] Preferably, two pixel circuits adjacent to each other along the second direction share one sixth connecting line;

[0077] Preferably, the third reset transistor is a dual-gate transistor;

[0078] Preferably, the orthographic projection of the third reset signal line on the substrate partially overlaps with the orthographic projection of the fourth scan line on the substrate;

[0079] Preferably, an orthographic projection of the third reset signal line on the substrate partially overlaps with an orthographic projection of the second reset signal line on the substrate.

[0080] Optionally, the array substrate further includes a second conductive layer, a third conductive layer and a fourth conductive layer; the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are stacked;

[0081] The second active layer is located on one side of the substrate, and the first conductive layer is located on a side of the second active layer away from the substrate;

[0082] The first capacitor plate, the third scan line, the fourth scan line and the light emitting control line are located in the first conductive layer;

[0083] The storage capacitor further includes a second capacitor plate, and the second capacitor plate, the first scan line and the second scan line are located in the second conductive layer;

[0084] The first active layer is located on a side of the second conductive layer away from the substrate;

[0085] The compensation transistor includes a first gate and a second gate, and the first scan line overlaps with the first channel region of the compensation transistor to form the first gate; the first reset transistor includes a third gate and a fourth gate, and the second scan line overlaps with the second channel region of the first reset transistor to form the third gate;

[0086] The second gate, the fourth gate and the third reset signal line are located in the third conductive layer;

[0087] The first reset signal line, the second reset signal line, the first connection line, the second connection line, the third connection line, the fourth connection line and the fifth connection line are located in the fourth conductive layer;

[0088] Preferably, the array substrate further comprises a fifth conductive layer located on a side of the fourth conductive layer away from the substrate;

[0089] The data line and the power line are located in the fifth conductive layer;

[0090] Preferably, the array substrate further includes a first insulating layer located between the first active layer and the third conductive layer, and a second insulating layer located between the third conductive layer and the fourth conductive layer, and the first via hole penetrates the first insulating layer and the second insulating layer;

[0091] Preferably, the first connecting line is connected to the first capacitor plate through a second via, and the array substrate also includes a third insulating layer located between the first conductive layer and the second conductive layer, and a fourth insulating layer located between the second conductive layer and the first active layer; the second via passes through the second insulating layer, the third insulating layer, the fourth insulating layer and the first insulating layer.

[0092] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate described in any embodiment of the present invention.

[0093] The technical solution of the embodiment of the present invention is to set the orthographic projection of the first via hole on the substrate to at least partially overlap with the orthographic projection of the first capacitor plate on the substrate, so that the space occupied by the first via hole is smaller, thereby reducing the space occupied by each pixel circuit, so that more pixel circuits can be set in the array substrate, which is convenient for improving the pixel density of the display panel formed by the array substrate, thereby improving the performance of the display panel.

[0094] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0096] Figure 1 is a structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0097] Figure 2 yes Figure 1 Cross-sectional view along the direction a1-a2;

[0098] Figure 3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0099] Figure 4 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0100] Figure 5 yes Figure 4 A partial enlarged view of

[0101] Figure 6 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0102] Figure 7 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0103] Figure 8 It is a schematic diagram of the layout structure of the second active layer and the first conductive layer of the array substrate provided by an embodiment of the present invention;

[0104] Fig. 9 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0105] Fig.10 yes Fig. 9 A cross-sectional view along the direction a3-a4;

[0106] Fig.11 yes Figure 7 A cross-sectional view along the direction a5-a6;

[0107] Fig.12 It is a schematic diagram of the layout structure of the second conductive layer, the first active layer and the third conductive layer of the array substrate provided by an embodiment of the present invention;

[0108] Fig.13 is a schematic diagram of the layout structure of the fourth conductive layer of the array substrate provided in an embodiment of the present invention;

[0109] Fig.14 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0110] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0111] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0112] As mentioned in the background technology, the existing display panels have the problem of performance improvement. The inventors have found that the reason for this problem is that as the resolution of the display panel becomes higher and higher, the circuits in the display panel become more and more complex, making the layout space more and more tight. When the pixel density is high, the line width and line spacing of the existing layout space design are small, making the preparation difficult. If the thickness of the display panel is increased by increasing the process flow to leave more space for the wiring of each layer, it will lead to increased costs or reduced product yield. If the requirements for line width and line spacing are met, a higher pixel density cannot be achieved, resulting in poor performance of the display panel.

[0113] In view of the above technical problems, an embodiment of the present invention provides an array substrate. Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention, Figure 2 yes Figure 1 The cross-sectional view along the direction a1-a2, Figure 3 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, with reference to Figure 1 , Figure 2 and Figure 3 , a pixel circuit 100 is provided in the array substrate, and the pixel circuit 100 includes a storage capacitor Cst and a compensation transistor T1; the storage capacitor Cst includes a first capacitor plate C1;

[0114] The array substrate comprises:

[0115] Substrate 110;

[0116] A first conductive layer M1 is located on one side of the substrate 110; a first capacitor plate C1 is located on the first conductive layer M1;

[0117] A first active layer 120, located at a side of the first conductive layer M1 away from the substrate 110, and the first active layer 120 includes a first active portion 121 of the compensation transistor T1;

[0118] The first connecting line L1 is located on a side of the first active layer 120 away from the substrate 110; the first active portion 121 is connected to the first connecting line L1 through a first via hole V1, and the first connecting line L1 is connected to the first capacitor plate C1; the orthographic projection of the first via hole V1 on the substrate 110 at least partially overlaps with the orthographic projection of the first capacitor plate C1 on the substrate 110.

[0119] Among them, at least one pixel circuit 100 is provided in the array substrate, and the pixel circuit 100 can be a 7T1C pixel circuit and its deformation, which is not limited here. The pixel circuit 100 can generate a driving current to drive the corresponding light-emitting element to emit light. The pixel circuit 100 includes a driving transistor, and the driving transistor can generate a driving current. The compensation transistor T1 can perform threshold compensation on the driving transistor to prevent the threshold voltage drift of the driving transistor from affecting the driving current. The storage capacitor Cst can maintain the gate voltage of the driving transistor, thereby maintaining the driving current generated by the driving transistor.

[0120] Among them, the substrate 110 has the functions of supporting, protecting and buffering. The substrate 110 can be a flexible substrate or a hard substrate, which is not limited in this embodiment. The array substrate may include multiple conductive layers, and the multiple conductive layers include a first conductive layer M1. For example, the first active layer 120 is an oxide active layer, that is, the first active layer 120 includes an oxide semiconductor material, and the compensation transistor T1 is an oxide transistor. In some other embodiments, the first active layer 120 may also be a polysilicon active layer, which is not limited here. The first connecting line L1 is connected between the first active part 121 and the first capacitor plate C1, so that the compensation transistor T1 is connected to the storage capacitor Cst through the first connecting line L1. For example, the pixel circuit 100 also includes a driving transistor, and the first capacitor plate C1 is reused as the gate of the driving transistor, then the compensation transistor T1 can be connected to the gate of the driving transistor through the first connecting line L1, so as to perform threshold compensation on the driving transistor. The first connection line L1 is located on a side of the first active layer 120 away from the substrate 110, that is, the first connection line L1 and the first active layer 120 are not arranged on the same layer, and need to be connected by punching, that is, the first connection line L1 is connected to the first active portion 121 of the first active layer 120 through the first via hole V1. The first via hole V1 is filled with a conductive material.

[0121] Specifically, by setting the orthographic projection of the first via hole V1 on the substrate 110 to at least partially overlap with the orthographic projection of the first capacitor plate C1 on the substrate 110, the space occupied by the first via hole V1 is smaller, thereby reducing the space occupied by each pixel circuit 100, and further making the space occupied by each pixel circuit 100 smaller, so that more pixel circuits 100 can be set in the array substrate, which is convenient for improving the pixel density of the display panel formed by the array substrate, and improving the performance of the display panel. In addition, there is no need to increase the process to improve the pixel density, which can reduce the preparation cost. In addition, more space can be reserved for routing, so as to ensure that the width and spacing of the routing meet the requirements.

[0122] The technical solution of this embodiment is to set the orthographic projection of the first via hole on the substrate to at least partially overlap with the orthographic projection of the first capacitor plate on the substrate, so that the space occupied by the first via hole is smaller, thereby reducing the space occupied by each pixel circuit, so that more pixel circuits can be set in the array substrate, which is convenient for improving the pixel density of the display panel formed by the array substrate, and improving the performance of the display panel.

[0123] On the basis of the above technical solution, optionally, the orthographic projection of the first via hole V1 on the substrate 110 is located within the orthographic projection of the first capacitor plate C1 on the substrate 110. That is, the first via hole V1 is located on the first capacitor plate C1. In this way, the space occupied by the first via hole V1 can be further reduced, which facilitates further improving the pixel density of the display panel formed by the array substrate, and improves the performance of the display panel.

[0124] On the basis of the above technical solutions, the structures that the array substrate may further include and the specific structure of the first active portion 121 are described below, but this is not intended to limit the present application.

[0125] Figure 4 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 5 yes Figure 4 , optionally, refer to Figure 4 and Figure 5 , the array substrate further includes: a power connection line VL; the first active portion 121 includes a first channel region T11 of the compensation transistor T1 and a first electrode T12; the first electrode T12 is connected to the first connection line L1; the first electrode T12 includes a first portion A1 and a second portion A2;

[0126] The first channel region T11, the first part A1 and the second part A2 are arranged along the first direction Y and extend along the first direction Y; the orthographic projection of the second part A2 on the substrate 110 overlaps with the orthographic projection of the power connection line VL on the substrate 110, and overlaps with the orthographic projection of the first capacitor plate C1 on the substrate 110.

[0127] Specifically, by arranging the first channel region T11, the first portion A1 and the second portion A2 along the first direction Y and extending along the first direction Y, the first electrode T12 does not include a portion extending along the second direction X, thereby eliminating the need to reserve a distance between the first electrode T12 and other traces extending along the second direction X (such as the power connection line VL), and reducing the size in the first direction Y, thereby saving space and facilitating the realization of a higher pixel density.

[0128] Optionally, refer to Figure 5 , the length of the first portion A1 in the second direction X is the same as the length of the first channel region T11 in the second direction X, and the length of the second portion A2 in the second direction X is greater than the length of the first portion A1 in the second direction X. In this way, the length of the second portion A2 close to the first capacitor plate C1 and the second capacitor plate C2 in the second direction X is larger, and in the process of the first active portion 121 climbing from the blank position to the second capacitor plate C2, the width of the first active portion 121 is larger, and the width of the portion of the first active portion 121 on the second capacitor plate C2 is larger, thereby avoiding the problem of the first active portion 121 being easily disconnected when climbing, thereby preventing the first active portion 121 from being disconnected, and ensuring the accuracy of signal transmission.

[0129] Optionally, refer to Figure 5 , the second portion A2 includes a first sub-portion A21, a second sub-portion A22 and a third sub-portion A23 arranged along the first direction Y; the orthographic projection of the second sub-portion A22 on the substrate 110 overlaps with the orthographic projection of the power connection line VL on the substrate 110; the orthographic projection of the third sub-portion A23 on the substrate 110 overlaps with the orthographic projection of the first capacitor plate C1 on the substrate 110;

[0130] The length of the first sub-portion A21 in the second direction X gradually increases along the first direction Y;

[0131] The length of the second sub-portion A22 in the second direction X is the same as the maximum length of the first sub-portion A21 in the second direction X;

[0132] The length of the third sub-portion A23 in the second direction X is greater than the length of the second sub-portion A22 in the second direction X.

[0133] Specifically, the first sub-portion A21 contacts the first channel region T11 of the compensation transistor T1, the second sub-portion A22 is located between the first sub-portion A21 and the third sub-portion A23, and the third sub-portion A23 is located on the second capacitor plate C2. By setting the length of the first sub-portion A21 in the second direction X to gradually increase along the first direction Y, the width of the first active portion 121 begins to gradually increase before climbing, and the width of the second sub-portion A22 can remain unchanged after the increase, so that the width of the second sub-portion A22 is larger, that is, the width of the first active portion 121 during the climbing process is larger. By setting the length of the third sub-portion A23 in the second direction X to be greater than the length of the second sub-portion A22 in the second direction X, it is convenient for the third sub-portion A23 to surround the first via hole V1, thereby ensuring that the third sub-portion A23 is connected to the first connection line L1 through the first via hole V1, that is, ensuring that the first active portion 121 is connected to the first connection line L1 through the first via hole V1.

[0134] Optionally, refer to Figure 1 , the storage capacitor Cst also includes a second capacitor plate C2;

[0135] Optionally, refer to Figure 4 , the array substrate further comprises:

[0136] The power connection line VL and the power connection line VDD, the power connection line VL is connected between the second capacitor plate C2 and the power line VDD; the power line VDD extends along a first direction Y, and the power connection line VL extends along a second direction X, and the first direction Y and the second direction X intersect.

[0137] Specifically, the second capacitor plate C2 and the first capacitor plate C1 are opposite to form a storage capacitor Cst. By setting a power connection line VL, all second capacitor plates C2 in the same row are connected to facilitate connection with the power line VDD, and the impedance on the power line VDD can be reduced, which is convenient for transmission of power signals.

[0138] Optionally, the power connection line VL and the second capacitor plate C2 are arranged in the same layer. For example, the power connection line VL and the second capacitor plate C2 are designed to be integrated, which is convenient for reducing the process flow and the manufacturing cost.

[0139] Optionally, refer to Figure 4 The first connection line L1 is connected to the first capacitor plate C1 through the second via hole V2, and the orthographic projection of the second via hole V2 on the substrate 110 is located within the orthographic projection of the first capacitor plate C1 on the substrate 110. The second via hole V2 is filled with a conductive material.

[0140] Specifically, if the first connection line L1 and the first capacitor plate C1 are not in the same film layer, the first connection line L1 is connected to the first capacitor plate C1 through the second via hole V2. By setting the orthographic projection of the second via hole V2 on the substrate 110 to be located within the orthographic projection of the first capacitor plate C1 on the substrate 110, the space occupied by the second via hole V2 can be reduced, thereby further reducing the occupied area of ​​the pixel circuit 100, which is conducive to improving the pixel density of the display panel formed by the array substrate.

[0141] On the basis of the above technical solution, the following describes structures that the array substrate may also include, but this is not intended to limit the present application.

[0142] Optionally, refer to Figure 3 , the pixel circuit 100 further includes a first reset transistor T2; the first reset transistor T2 is an oxide transistor.

[0143] Figure 6 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 6 , the first active layer 120 further includes a second active portion 122 of the first reset transistor T2; the first active portion 121 includes a first electrode T12, a second electrode T13 and a first channel region T11 of the compensation transistor T1; the first electrode T12 is connected to the first connection line L1;

[0144] The second active portion 122 includes a second channel region T21 of the first reset transistor T2 , a third electrode T22 , and a fourth electrode T23 ; the third electrode T22 is connected to the second electrode T13 , and the fourth electrode T23 is connected to the first reset signal line Vref1 .

[0145] Specifically, when the first reset transistor T2 and the compensation transistor T1 are turned on, the first reset transistor T2 can transmit the first reset voltage on the first reset signal line Vref1 to the first capacitor plate C1 through the compensation transistor T1, that is, to the gate of the driving transistor, to achieve resetting the gate of the driving transistor. For example, the first active portion 121 and the second active portion 122 are an integrated structure, which is convenient for integrated molding, can reduce the process flow, and reduce the preparation cost.

[0146] Optionally, refer to Figure 6 , the third electrode T22 is reused as the second electrode T13. In this way, the occupied space of the pixel circuit 100 can be reduced, so as to further improve the pixel density of the display panel formed by the array substrate.

[0147] Optionally, refer to Figure 6 , the array substrate further comprises:

[0148] The first scan line S1 and the second scan line S2 are located on a side of the first capacitor plate C1 away from the substrate 110 and extend along the second direction X; the orthographic projection of the first scan line S1 on the substrate 110 partially overlaps with the orthographic projection of the first channel region T11 on the substrate 110; the orthographic projection of the second scan line S2 on the substrate 110 partially overlaps with the orthographic projection of the second channel region T21 on the substrate 110.

[0149] Specifically, the portion where the first scan line S1 overlaps with the first channel region T11 forms the first gate of the compensation transistor T1, and the portion where the second scan line S2 overlaps with the second channel region T21 forms the first gate of the first reset transistor T2. In this way, there is no need to additionally set a gate layer, the thickness of the array substrate can be reduced, and the thin and light design of the display panel is convenient. By setting the first scan line S1, the first scan signal on the first scan line S1 can control the compensation transistor T1 to be turned on or off, thereby controlling the turn-on timing of the compensation transistor T1. By setting the second scan line S2, the second scan signal on the second scan line S2 can control the first reset transistor T2 to be turned on or off, thereby controlling the turn-on timing of the first reset transistor T2, and further controlling the timing of the pixel circuit 100.

[0150] Optionally, the storage capacitor Cst further includes a second capacitor plate C2;

[0151] The array substrate also includes:

[0152] A power connection line VL and a power connection line VDD, wherein the power connection line VL is connected between the second capacitor plate C2 and the power line VDD; the power line VDD extends along a first direction Y, and the power connection line VL extends along a second direction X;

[0153] Optionally, refer to Figure 6 , the first scanning line S1 and the power connection line VL are arranged on the same layer;

[0154] Along the first direction Y, a distance D1 between the first scan line S1 and the power connection line VL is less than 3 micrometers.

[0155] Specifically, the first channel region T11, the first portion A1 and the second portion A2 on the first active portion 121 are arranged along the first direction Y and extend along the first direction Y, so that the first active portion 121 does not include a portion extending along the second direction X, so there is no need to reserve a distance between the first active portion 121 and other traces extending along the second direction X (for example, the power connection line VL), and the size in the first direction Y can be reduced. The spacing D1 between the first scan line S1 and the power connection line VL is less than 3 microns, for example, 2 microns, thereby saving space and facilitating the realization of a higher pixel density.

[0156] On the basis of the above-mentioned technical solutions, the structures that the array substrate may further include are described below, but are not intended to limit the present application.

[0157] Optionally, refer to Figure 3 , the pixel circuit also includes a driving transistor T3 and a data writing transistor T4;

[0158] Figure 7 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 7 , the array substrate further comprises:

[0159] A third scan line S3 and a second connecting line L2; the third scan line S3 extends along the second direction X;

[0160] Along the first direction Y, the orthographic projection of the third scanning line S3 on the substrate 110 is located between the orthographic projection of the first scanning line S1 on the substrate 110 and the orthographic projection of the second scanning line S2 on the substrate 110;

[0161] The second electrode T13 is connected to the second connection line L2 through the third via hole V3, and the second connection line L2 is connected to the first electrode of the driving transistor T3; the orthographic projection of the third via hole V3 on the substrate 110 at least partially overlaps with the orthographic projection of the third scanning line S3 on the substrate 110. The third via hole V3 is filled with a conductive material.

[0162] Specifically, the third scan line S3 is connected to the gate of the data writing transistor T4, and the third scan signal on the third scan line S3 can control the data writing transistor T4 to be turned on or off, thereby controlling the turn-on timing of the data writing transistor T4. When the third scan signal on the third scan line S3 controls the data writing transistor T4 to be turned on, the data writing transistor T4 can transmit the data voltage on the data line to the gate of the driving transistor T3, so that the driving transistor T3 generates a driving current according to the data voltage. The second electrode T13 is connected to the second connection line L2 through the third via V3, and the second connection line L2 is connected to the first electrode of the driving transistor T3, so that the compensation transistor T1 is connected to the first electrode of the driving transistor T3, and the first electrode T12 of the compensation transistor T1 is connected to the gate of the driving transistor T3, so that the compensation transistor T1 is connected between the gate of the driving transistor T3 and the first electrode of the driving transistor T3, so that the compensation transistor T1 performs threshold compensation on the driving transistor T3.

[0163] By setting the orthographic projection of the third via hole V3 on the substrate 110 to at least partially overlap with the orthographic projection of the third scan line S3 on the substrate 110, the space occupied by the third via hole V3 can be reduced, thereby reducing the space occupied by the pixel circuit 100, thereby facilitating the realization of a higher pixel density.

[0164] Optionally, the third scanning line S3 and the first capacitor plate C1 are arranged in the same layer. This arrangement can reduce the number of film layers, thereby reducing the thickness of the array substrate, and facilitating a lightweight and thin design.

[0165] Optionally, the second connection line L2 is arranged in the same layer as the first connection line L1. This arrangement can further reduce the number of film layers, thereby reducing the thickness of the array substrate and facilitating a lightweight and thin design.

[0166] Figure 8 is a schematic diagram of the layout structure of the second active layer and the first conductive layer of the array substrate provided in an embodiment of the present invention. Figure 7 and Figure 8 , the array substrate further comprises:

[0167] The second active layer 130 is located on one side of the substrate 110 and on the side of the first capacitor plate C1 close to the substrate; the second active layer 130 includes a third channel region T31, a fifth electrode T32 and a sixth electrode T33 of the driving transistor T3; the fifth electrode T32 is the first electrode of the driving transistor T3;

[0168] The second active layer 130 further includes a fourth channel region T41, a seventh electrode T42, and an eighth electrode T43 of the data writing transistor T4;

[0169] The orthographic projection of the third scanning line S3 on the substrate 110 partially overlaps with the orthographic projection of the fourth channel region T41 on the substrate 110;

[0170] The seventh electrode T42 is connected to the sixth electrode T33, and the eighth electrode T43 is connected to the data line Data.

[0171] Specifically, for example, if the second active layer 130 is a polysilicon active layer, that is, the material of the second active layer 130 includes a polysilicon semiconductor material, the driving transistor T3 and the data writing transistor T4 are polysilicon transistors. The portion where the third scan line S3 overlaps with the fourth channel region T41 forms the gate of the data writing transistor T4, so there is no need to set the gate of the data writing transistor T4 separately, which can reduce the occupied space of the pixel circuit 100, reduce the thickness of the array substrate, and facilitate the thin and light design of the array substrate. By setting the eighth electrode T43 to connect the data line Data, when the data writing transistor T4 is turned on, the data voltage on the data line Data can be transmitted to the gate of the driving transistor T3, so that the driving transistor T3 can generate a driving current according to the data voltage.

[0172] Optionally, the first capacitor plate C1 is reused as the gate of the driving transistor T3. In this way, the number of conductive blocks can be reduced, and the occupied space of the pixel circuit 100 can be reduced.

[0173] On the basis of the above technical solutions, optionally, refer to Figure 3 , the pixel circuit further includes a first light emission control transistor T5 and a second light emission control transistor T6;

[0174] refer to Figure 7 and Figure 8 , the array substrate further comprises:

[0175] The light emitting control line EM is located at a side of the second active layer 130 away from the substrate 110 and extends along the second direction X;

[0176] The second active layer 130 further includes a fifth channel region T51, a ninth electrode T52, and a tenth electrode T53 of the first light emission control transistor T5;

[0177] The orthographic projection of the fifth channel region T51 on the substrate 110 partially overlaps with the orthographic projection of the light emitting control line EM on the substrate 110;

[0178] The ninth electrode T52 is multiplexed as the fifth electrode T32, and the tenth electrode T53 is connected to the first electrode of the light emitting element OLED;

[0179] The second active layer 130 further includes a sixth channel region T61, an eleventh electrode T62 and a twelfth electrode T63 of the second light emission control transistor T6;

[0180] The orthographic projection of the sixth channel region T61 on the substrate 110 partially overlaps with the orthographic projection of the light emitting control line EM on the substrate 110;

[0181] The eleventh electrode T62 is connected to the sixth electrode T33 ; the twelfth electrode T63 is connected to the power line VDD.

[0182] The first light emission control transistor T5 and the second light emission control transistor T6 are polysilicon transistors.

[0183] Specifically, by setting the first light-emitting control transistor T5 and the second light-emitting control transistor T6, it is possible to control whether the driving transistor T3 generates a driving current and whether the driving current is transmitted to the light-emitting element OLED. The second electrode of the light-emitting element OLED is connected to the second power line VSS. When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, the power line VDD, the second light-emitting control transistor T6, the driving transistor T3, the first light-emitting control transistor T5, the light-emitting element OLED and the second power line VSS form a current loop, so that the driving transistor T3 generates a driving current, and the light-emitting element OLED emits light in response to the driving current.

[0184] By setting the orthographic projection of the fifth channel region T51 on the substrate 110 to overlap with the orthographic projection of the light emitting control line EM on the substrate 110, and the orthographic projection of the sixth channel region T61 on the substrate 110 to overlap with the orthographic projection of the light emitting control line EM on the substrate 110, the light emitting control line EM overlaps with the fifth channel region T51 to form the gate of the first light emitting control transistor T5, and the light emitting control line EM overlaps with the sixth channel region T61 to form the gate of the second light emitting control transistor T6. In this way, there is no need to set up an additional electrode block, and the occupied space of the pixel circuit 100 can be reduced.

[0185] Optionally, refer to Figure 7 , the storage capacitor Cst also includes a second capacitor plate C2;

[0186] The array substrate also includes:

[0187] The third connection line L3 is connected between the second capacitor plate C2 and the power line VDD.

[0188] Specifically, the second capacitor plate C2 is connected to the third connection line L3 through a via, and the third connection line L3 is connected to the power line VDD through a via, so that the second capacitor plate C2 is connected to the power line VDD, which is convenient for maintaining the voltage of the second capacitor plate C2, so that the voltage of the first capacitor plate C1 is stable, that is, the voltage of the gate of the driving transistor T3 can be stabilized, thereby maintaining the driving current generated by the driving transistor T3.

[0189] Optionally, refer to Figure 7 , the array substrate further comprises:

[0190] The fourth connection line L4 is connected between the third connection line L3 and the twelfth electrode T63 .

[0191] Specifically, one end of the fourth connection line L4 is connected to the third connection line L3, and the other end of the fourth connection line L4 is connected to the twelfth electrode T63 through a via hole, so that the second light-emitting control transistor T6 is connected to the power line VDD through the fourth connection line L4 and the third connection line L3. For example, the fourth connection line L4 and the third connection line L3 are arranged in the same layer, which can reduce the number of film layers, reduce the thickness of the array substrate, and facilitate the realization of a lightweight design of the array substrate.

[0192] Optionally, refer to Figure 7 , two pixel circuits 100 adjacent to each other along the second direction X share a fourth connection line L4. In this way, the number of connection lines can be reduced, and the occupied space of the pixel circuits 100 is further reduced, thereby further improving the pixel density of the display panel formed by the array substrate.

[0193] On the basis of the above technical solutions, optionally, refer to Figure 3 The pixel circuit further includes a second reset transistor T7 and a third reset transistor T8; the second reset transistor T7 and the third reset transistor T8 are polysilicon transistors.

[0194] Fig. 9 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Fig. 9 , the array substrate further comprises:

[0195] The fourth scan line S4 is located at a side of the second active layer 130 away from the substrate 110 and extends along the second direction X;

[0196] A third reset signal line Vref3 is located at a side of the film layer where the fourth scan line S4 is located away from the substrate 110 and extends along the second direction X;

[0197] The second reset signal line Vref2 is located at a side of the film layer where the third reset signal line Vref3 is located away from the substrate 110 and extends along the second direction X;

[0198] Optionally, refer to Fig.10 , the second active layer 130 further includes a seventh channel region T71 , a thirteenth electrode T72 and a fourteenth electrode T73 of the second reset transistor T7 ;

[0199] The orthographic projection of the seventh channel region T71 on the substrate 110 partially overlaps with the orthographic projection of the fourth scan line S4 on the substrate 110;

[0200] The thirteenth electrode T72 is connected to the tenth electrode T53, and the fourteenth electrode T73 is connected to the second reset signal line Vref2;

[0201] The second active layer 130 further includes an eighth channel region T81, a fifteenth electrode T82, and a sixteenth electrode T83 of the third reset transistor T8;

[0202] The orthographic projection of the eighth channel region T81 on the substrate 110 partially overlaps with the orthographic projection of the fourth scan line S4 on the substrate 110 .

[0203] Specifically, by setting the fourth scan line S4, the fourth scan line S4 can control the turn-on timing of the second reset transistor T7 and the third reset transistor T8. When the fourth scan signal on the fourth scan line S4 controls the second reset transistor T7 and the third reset transistor T8 to turn on, the second reset transistor T7 can transmit the second reset voltage on the second reset signal line Vref2 to the first electrode of the light-emitting element OLED to reset the first electrode of the light-emitting element OLED. The third reset transistor T8 can transmit the third reset voltage on the third reset signal line Vref3 to the first electrode of the driving transistor T3 to reset the first electrode of the driving transistor T3, so that the driving transistor T3 can better generate the driving current, and the light-emitting element OLED can better respond to the driving current to emit light.

[0204] Optionally, refer to Fig. 9 The array substrate further includes a fifth connection line L5, the fifteenth electrode T82 is connected to the fifth electrode T32 through the fifth connection line L5, and the sixteenth electrode T83 is connected to the third reset signal line Vref3.

[0205] Specifically, the fifteenth electrode T82 is connected to the fifth connection line L5 through a via, and the fifth connection line L5 is connected to the fifth electrode T32 through a via, so that the fifteenth electrode T82 is connected to the fifth electrode T32 (the first electrode of the driving transistor T3) through the fifth connection line L5, so that the third reset transistor T8 can transmit the third reset voltage on the third reset signal line Vref3 to the first electrode of the driving transistor T3.

[0206] Optionally, refer to Fig. 9 The array substrate further includes a sixth connection line L6, which is connected between the sixteenth electrode T83 and the third reset signal line Vref3. In this way, the third reset transistor T8 can be connected to the third reset signal line Vref3, so that the third reset transistor T8 can transmit the third reset voltage on the third reset signal line Vref3 to the first electrode of the driving transistor T3.

[0207] Optionally, refer to Fig. 9 , two pixel circuits 100 adjacent to each other along the second direction X share a sixth connection line L6. In this way, the number of connection lines can be reduced, the occupied space of the pixel circuits 100 is further reduced, and the pixel density of the display panel formed by the array substrate is improved.

[0208] Optionally, refer to Figure 8 and Fig. 9 , the third reset transistor T8 is a double-gate transistor.

[0209] Specifically, Figure 8As shown, the fourth scan line S4 includes a main body S41 and an extension S42, the main body S41 overlaps with the second active layer 130 to form a first gate T8_1 of the third reset transistor T8, and the extension S42 overlaps with the second active layer 130 to form a second gate T8_2 of the third reset transistor T8, so that the third reset transistor T8 forms a double-gate transistor. In this way, the leakage current of the driving transistor T3 along the third reset transistor T8 can be reduced, and the stability of the driving current generated by the driving transistor T3 can be improved.

[0210] Optionally, refer to Fig. 9 , the orthographic projection of the third reset signal line Vref3 on the substrate 110 partially overlaps with the orthographic projection of the fourth scan line S4 on the substrate 110. In this way, the occupied space in the first direction Y and the second direction X can be reduced, and the occupied space of the pixel circuit 100 can be further reduced, thereby improving the pixel density of the display panel formed by the array substrate.

[0211] Optionally, refer to Fig. 9 , the orthographic projection of the third reset signal line Vref3 on the substrate 110 partially overlaps with the orthographic projection of the second reset signal line Vref2 on the substrate 110. In this way, the occupied space in the first direction Y and the second direction X can be reduced, the occupied space of the pixel circuit can be further reduced, and the pixel density of the display panel formed by the array substrate can be improved.

[0212] On the basis of the above technical solutions, the structure of the array substrate is further described below in combination with the specific film layers where the electrodes and wirings are located, but this is not intended to limit the present application.

[0213] Optionally, Fig.10 yes Fig. 9 The cross-sectional view along the direction a3-a4, Fig.11 yes Figure 7 The cross-sectional view along the direction a5-a6, Fig.12 is a schematic diagram of the layout structure of the second conductive layer, the first active layer and the third conductive layer of the array substrate provided in an embodiment of the present invention, Fig.13 is a schematic diagram of the layout structure of the fourth conductive layer of the array substrate provided in an embodiment of the present invention. Figure 2 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 , the array substrate further includes a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4; the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 are stacked;

[0214] The second active layer 130 is located on one side of the substrate 110 , and the first conductive layer M1 is located on a side of the second active layer 130 away from the substrate 110 ;

[0215] The first capacitor plate C1, the third scan line S3, the fourth scan line S4 and the light emitting control line EM are located in the first conductive layer M1;

[0216] The storage capacitor Cst further includes a second capacitor plate C2, and the second capacitor plate C2, the first scan line S1 and the second scan line S2 are located in the second conductive layer M2;

[0217] The first active layer 120 is located on a side of the second conductive layer M2 away from the substrate 110;

[0218] The compensation transistor T1 includes a first gate T1_1 and a second gate T1_2, and the first scan line S1 overlaps with the first channel region T11 of the compensation transistor T1 to form the first gate T1_1; the first reset transistor T2 includes a third gate T2_1 and a fourth gate T2_2, and the second scan line S2 overlaps with the second channel region T21 of the first reset transistor T2 to form the third gate T2_1;

[0219] The second gate T1_2, the fourth gate T2_2 and the third reset signal line Vref3 are located in the third conductive layer M3;

[0220] The first reset signal line Vref1 , the second reset signal line Vref2 , the first connection line L1 , the second connection line L2 , the third connection line L3 , the fourth connection line L4 and the fifth connection line L5 are located in the fourth conductive layer M4 .

[0221] In this way, the number of wirings and electrodes provided in each conductive layer will not be too many or too few, which is convenient for improving the pixel density of the display panel and facilitating the lightweight design of the display panel.

[0222] Optionally, refer to Fig.11 , the array substrate further includes a fifth conductive layer M5 located on a side of the fourth conductive layer M4 away from the substrate 110;

[0223] The data line Data and the power line VDD are located in the fifth conductive layer M5.

[0224] Specifically, the data line Data can transmit a data voltage, and the power line VDD can transmit a power voltage. By arranging the data line Data and the power line VDD in the fifth conductive layer M5, the number of film layers can be reduced, which facilitates the thin and light design of the array substrate.

[0225] Optionally, refer to Figure 2The array substrate further includes a first insulating layer 140 located between the first active layer 120 and the third conductive layer M3 , and a second insulating layer 150 located between the third conductive layer M3 and the fourth conductive layer M4 , and the first via hole V1 penetrates the first insulating layer 140 and the second insulating layer 150 .

[0226] Specifically, the first insulating layer 140 and the second insulating layer 150 can be inorganic insulating layers. By setting a first via hole V1 that penetrates the first insulating layer 140 and the second insulating layer 150, the first connecting line L1 located in the fourth conductive layer M4 can be connected to the first active part 121 of the first active layer 120 through the first via hole V1, so that the compensation transistor T1 is connected to the first capacitor plate C1 through the first connecting line L1.

[0227] Optionally, refer to Figure 2 The first connecting line L1 is connected to the first capacitor plate C1 through the second via V2. The array substrate also includes a third insulating layer 160 located between the first conductive layer M1 and the second conductive layer M2, and a fourth insulating layer 170 located between the second conductive layer M2 and the first active layer 120. The second via V2 penetrates the second insulating layer 150, the third insulating layer 160, the fourth insulating layer 170 and the first insulating layer 140.

[0228] Specifically, the third insulating layer 160 and the fourth insulating layer 170 can be inorganic insulating layers. By setting a second via hole V2 that penetrates the first insulating layer 140, the second insulating layer 150, the third insulating layer 160 and the fourth insulating layer 170, the first connecting line L1 located in the fourth conductive layer M4 can be connected to the first capacitor plate C1 located in the first conductive layer M1 through the second via hole V2, so that the compensation transistor T1 is connected to the first capacitor plate C1 through the first connecting line L1.

[0229] This embodiment also provides a display panel, Fig.14 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.14 As shown, the display panel includes the array substrate provided by any of the above embodiments. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc. The display panel includes the array substrate provided by any embodiment of the present invention, and thus has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here.

[0230] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate is provided with a pixel circuit, the pixel circuit comprising a storage capacitor and a compensation transistor; the storage capacitor comprises a first capacitor plate; The array substrate comprises: substrate; A first conductive layer is located on one side of the substrate; the first capacitor plate is located on the first conductive layer; A first active layer, located on a side of the first conductive layer away from the substrate, the first active layer comprising a first active portion of the compensation transistor; A first connecting line is located on a side of the first active layer away from the substrate; the first active portion is connected to the first connecting line through a first via hole, and the first connecting line is connected to the first capacitor plate; the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the first capacitor plate on the substrate.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first capacitor plate on the substrate.

3. The array substrate according to claim 1, characterized in that: The array substrate further comprises: a power connection line; The first active portion includes a first channel region and a first electrode of the compensation transistor; the first electrode is connected to the first connection line; the first electrode includes a first portion and a second portion; The first channel region, the first portion and the second portion are arranged along a first direction and extend along the first direction; an orthographic projection of the second portion on the substrate overlaps with an orthographic projection of the power connection line on the substrate and overlaps with an orthographic projection of the first capacitor plate on the substrate; Preferably, the length of the first portion in the second direction is the same as the length of the first channel region in the second direction, and the length of the second portion in the second direction is greater than the length of the first portion in the second direction; wherein the first direction intersects the second direction; Preferably, the second portion includes a first sub-portion, a second sub-portion and a third sub-portion arranged along the first direction; the orthographic projection of the second sub-portion on the substrate overlaps with the orthographic projection of the power connection line on the substrate; the orthographic projection of the third sub-portion on the substrate overlaps with the orthographic projection of the first capacitor plate on the substrate; The length of the first sub-portion in the second direction gradually increases along the first direction; The length of the second sub-portion in the second direction is the same as the maximum length of the first sub-portion in the second direction; The length of the third sub-portion in the second direction is greater than the length of the second sub-portion in the second direction; Preferably, the storage capacitor further includes a second capacitor plate; The array substrate further includes: A power connection line and a power line, wherein the power connection line is connected between the second capacitor plate and the power line; the power line extends along the first direction, and the power connection line extends along the second direction; Preferably, the power connection line is arranged on the same layer as the second capacitor plate.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The first connecting line is connected to the first capacitor plate through a second via hole, and the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the first capacitor plate on the substrate.

5. The array substrate according to any one of claims 1 to 3, characterized in that: The pixel circuit further includes a first reset transistor; The first active layer further includes a second active portion of the first reset transistor; the first active portion includes a first electrode, a second electrode and a first channel region of the compensation transistor; the first electrode is connected to the first connection line; The second active portion includes a second channel region of the first reset transistor, a third electrode and a fourth electrode; the third electrode is connected to the second electrode, and the fourth electrode is connected to the first reset signal line; Preferably, the third electrode is reused as the second electrode; Preferably, the array substrate further includes: A first scan line and a second scan line; located on a side of the first capacitor plate away from the substrate and extending along a second direction; an orthographic projection of the first scan line on the substrate partially overlaps with an orthographic projection of the first channel region on the substrate; an orthographic projection of the second scan line on the substrate partially overlaps with an orthographic projection of the second channel region on the substrate; Preferably, the storage capacitor further includes a second capacitor plate; The array substrate further includes: A power connection line and a power line, wherein the power connection line is connected between the second capacitor plate and the power line; the power line extends along a first direction, and the power connection line extends along a second direction; The first scanning line and the power connection line are arranged in the same layer; Along the first direction, a distance between the first scanning line and the power connection line is less than 3 micrometers.

6. The array substrate according to claim 5, characterized in that: The pixel circuit also includes a driving transistor and a data writing transistor; The array substrate further includes: a third scanning line and a second connecting line; the third scanning line extends along the second direction; Along the first direction, the orthographic projection of the third scanning line on the substrate is located between the orthographic projection of the first scanning line on the substrate and the orthographic projection of the second scanning line on the substrate; The second electrode is connected to the second connection line through a third via hole, and the second connection line is connected to the first electrode of the driving transistor; the orthographic projection of the third via hole on the substrate at least partially overlaps with the orthographic projection of the third scanning line on the substrate; Preferably, the third scanning line is arranged in the same layer as the first capacitor plate; Preferably, the second connecting line is arranged in the same layer as the first connecting line; Preferably, the array substrate further includes: A second active layer is located on one side of the substrate and on a side of the first capacitor plate close to the substrate; the second active layer includes a third channel region, a fifth electrode and a sixth electrode of the driving transistor; the fifth electrode is the first electrode of the driving transistor; The second active layer further includes a fourth channel region, a seventh electrode and an eighth electrode of the data writing transistor; The orthographic projection of the third scanning line on the substrate partially overlaps with the orthographic projection of the fourth channel region on the substrate; The seventh electrode is connected to the sixth electrode, and the eighth electrode is connected to the data line; Preferably, the first capacitor plate is reused as the gate of the driving transistor.

7. The array substrate according to claim 6, characterized in that: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor; The array substrate further includes: a light emitting control line, located on a side of the second active layer away from the substrate and extending along a second direction; The second active layer further includes a fifth channel region, a ninth electrode and a tenth electrode of the first light emission control transistor; The orthographic projection of the fifth channel region on the substrate partially overlaps with the orthographic projection of the light emitting control line on the substrate; The ninth electrode is reused as the fifth electrode, and the tenth electrode is connected to the first electrode of the light emitting element; The second active layer further includes a sixth channel region, an eleventh electrode and a twelfth electrode of the second light emission control transistor; The orthographic projection of the sixth channel region on the substrate partially overlaps with the orthographic projection of the light emitting control line on the substrate; The eleventh electrode is connected to the sixth electrode; the twelfth electrode is connected to the power line; Preferably, the storage capacitor further includes a second capacitor plate; The array substrate further includes: A third connecting line, the third connecting line is connected between the second capacitor plate and the power line; Preferably, the array substrate further includes: a fourth connecting line connected between the third connecting line and the twelfth electrode; Preferably, two pixel circuits adjacent to each other along the second direction share one fourth connecting line.

8. The array substrate according to claim 7, characterized in that: The pixel circuit further includes a second reset transistor and a third reset transistor; The array substrate further includes: a fourth scanning line, located at a side of the second active layer away from the substrate and extending along the second direction; A third reset signal line is located at a side of the film layer where the fourth scan line is located away from the substrate and extends along the second direction; A second reset signal line is located at a side of the film layer where the third reset signal line is located away from the substrate and extends along the second direction; The second active layer further includes a seventh channel region, a thirteenth electrode and a fourteenth electrode of the second reset transistor; The orthographic projection of the seventh channel region on the substrate partially overlaps with the orthographic projection of the fourth scanning line on the substrate; The thirteenth electrode is connected to the tenth electrode, and the fourteenth electrode is connected to the second reset signal line; The second active layer further includes an eighth channel region, a fifteenth electrode and a sixteenth electrode of the third reset transistor; The orthographic projection of the eighth channel region on the substrate partially overlaps with the orthographic projection of the fourth scanning line on the substrate; The array substrate further includes a fifth connecting line, the fifteenth electrode is connected to the fifth electrode through the fifth connecting line, and the sixteenth electrode is connected to the third reset signal line; Preferably, the array substrate further comprises a sixth connecting line, wherein the sixth connecting line is connected between the sixteenth electrode and the third reset signal line; Preferably, two pixel circuits adjacent to each other along the second direction share one sixth connecting line; Preferably, the third reset transistor is a dual-gate transistor; Preferably, the orthographic projection of the third reset signal line on the substrate partially overlaps with the orthographic projection of the fourth scan line on the substrate; Preferably, an orthographic projection of the third reset signal line on the substrate partially overlaps with an orthographic projection of the second reset signal line on the substrate.

9. The array substrate according to claim 8, characterized in that: The array substrate further comprises a second conductive layer, a third conductive layer and a fourth conductive layer; the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are stacked; The second active layer is located on one side of the substrate, and the first conductive layer is located on a side of the second active layer away from the substrate; The first capacitor plate, the third scan line, the fourth scan line and the light emitting control line are located in the first conductive layer; The storage capacitor further includes a second capacitor plate, and the second capacitor plate, the first scan line and the second scan line are located in the second conductive layer; The first active layer is located on a side of the second conductive layer away from the substrate; The compensation transistor includes a first gate and a second gate, and the first scan line overlaps with the first channel region of the compensation transistor to form the first gate; the first reset transistor includes a third gate and a fourth gate, and the second scan line overlaps with the second channel region of the first reset transistor to form the third gate; The second gate, the fourth gate and the third reset signal line are located in the third conductive layer; The first reset signal line, the second reset signal line, the first connection line, the second connection line, the third connection line, the fourth connection line and the fifth connection line are located in the fourth conductive layer; Preferably, the array substrate further comprises a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; The data line and the power line are located in the fifth conductive layer; Preferably, the array substrate further includes a first insulating layer located between the first active layer and the third conductive layer, and a second insulating layer located between the third conductive layer and the fourth conductive layer, and the first via hole penetrates the first insulating layer and the second insulating layer; Preferably, the first connecting line is connected to the first capacitor plate through a second via, and the array substrate also includes a third insulating layer located between the first conductive layer and the second conductive layer, and a fourth insulating layer located between the second conductive layer and the first active layer; the second via passes through the second insulating layer, the third insulating layer, the fourth insulating layer and the first insulating layer.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

Images