Superconducting transistor device and preparation method thereof

Abstract

The invention discloses a superconducting transistor device and a preparation method thereof, and belongs to the field of superconducting electronics, and the superconducting transistor device comprises a first grid electrode and / or a second grid electrode, a superconducting nanowire, a first electrode and a second electrode. Wherein the first grid electrode and the second grid electrode are located on the two sides of the superconducting nanowire respectively, or the first grid electrode or the second grid electrode is located on the side edge of the superconducting nanowire; two ends of the superconducting nanowire are respectively connected with the first electrode and the second electrode; the first grid electrode and / or the second grid electrode, the first electrode and the second electrode are used for being connected with an external electrode. The superconducting transistor device with a logic function is obtained through construction of the superconducting nanowires and the grid electrodes, the structure of a superconducting logic circuit is simplified, the integration level and expansibility of the device are improved, the preparation difficulty and the requirement for magnetic shielding are greatly reduced, and a new technical route is provided for development of superconducting integrated circuits.

Description

Technical Field

[0001] The present application belongs to the field of superconducting electronics, and specifically relates to a superconducting transistor device and a method for preparing the same. Background Art

[0002] Historically, Moore's Law has set the tone for the development of semiconductor integrated circuits, emphasizing the continuous reduction in the size of individual transistors and advances in lithography. This development, characterized by increased transistor density, improved performance, and improved energy efficiency, has been the cornerstone of the semiconductor industry. However, as traditional silicon-based technologies approach the limits of physics and materials science, researchers are exploring alternative solutions, such as superconducting integrated circuits, the exploration of new materials (such as two-dimensional materials and carbon nanotubes), quantum computing, photonic integrated circuits, etc. Among these solutions, superconducting electronics offers unique advantages, such as zero resistance and quantum effects, providing new ways to surpass the limitations of classical CMOS integrated circuits.

[0003] At present, the realization of superconducting integrated circuits is mainly based on superconducting digital integrated circuits based on Josephson junctions. However, the device structure of this integrated circuit is complex, the preparation process is difficult, and strict magnetic shielding conditions are required, which greatly limits the scalability. In addition, a series of recent experiments have proved that the superconductivity of low-dimensional devices can be completely suppressed by the gate electric field. The construction of superconducting transistors based on this is not only applicable to two-dimensional and even three-dimensional bridge junction superconducting devices of different configurations, but also to various superconducting thin film materials. However, most of the current research is limited to the study of the physical properties of a single field effect device, and technical research on logic function devices and new superconducting integrated circuits is relatively rare. Summary of the invention

[0004] In order to solve the problems of complex structure, difficult preparation process, harsh magnetic shielding conditions, and limited scalability of existing superconducting digital integrated circuits based on Josephson junctions, the present application proposes a superconducting transistor device and a preparation method thereof. The device of the present application is directly constructed based on superconducting nanowires, which improves the integration and scalability of the basic units of superconducting integrated circuits and reduces the difficulty of preparation and the requirements for magnetic shielding.

[0005] This application is implemented through the following technical solutions:

[0006] A superconducting transistor device, comprising: a first gate and / or a second gate, a superconducting nanowire, a first electrode and a second electrode;

[0007] Wherein, the first gate and the second gate are respectively located on both sides of the superconducting nanowire, or the first gate or the second gate is located on the side of the superconducting nanowire;

[0008] Two ends of the superconducting nanowire are connected to the first electrode and the second electrode respectively;

[0009] The first gate and / or the second gate, the first electrode and the second electrode are all used to connect to an external electrode.

[0010] In some embodiments, the first gate and the second gate have the same shape, and the first gate and the second gate are symmetrically distributed on both sides of the superconducting nanowire.

[0011] In some embodiments, the first gate and / or the second gate is close to one end of the superconducting nanowire and is in a rectangular configuration or a pointed configuration;

[0012] The first gate and / or the second gate are obtained from thin film materials or are obtained by stripping off metal thin film deposition.

[0013] In some embodiments, the superconducting nanowire is made of NbTiN, NbN, MoRe, YBCO or BSCCO.

[0014] In some embodiments, the superconducting nanowire adopts a structure of two nanowires connected in parallel, and the first gate and the second gate respectively control one of the two nanowires in the structure of parallel.

[0015] In some embodiments, the two nanowires have the same width and substantially the same critical current, and the spacing between the two nanowires should satisfy the anti-interference distance.

[0016] In some embodiments, the superconducting transistor device further includes: electronic components, wherein the electronic components are configured to realize more logic functions with the superconducting nanowire, the first electrode, and the second electrode.

[0017] In some embodiments, the superconducting transistor device has substantially consistent threshold voltage and regulation trend when a single gate is grounded or a double gate is grounded, and the superconducting transistor device loses superconductivity when the gate voltage is greater than or equal to a certain voltage value.

[0018] In a second aspect, the present application proposes a method for preparing the above-mentioned superconducting transistor device, comprising:

[0019] Growing a silicon dioxide oxide layer on the surface of the silicon wafer and polishing the silicon dioxide oxide layer;

[0020] Depositing a superconducting thin film on the polished silicon dioxide oxide layer;

[0021] The first gate and / or the second gate and the pattern of the superconducting nanowire are obtained by exposure, and the superconducting nanowire regional structure is obtained by etching;

[0022] Obtaining electrode patterns of the first gate and / or the second gate, the first electrode and the second electrode by exposure, and obtaining an electrode region structure by etching;

[0023] The superconducting transistor device is obtained by packaging.

[0024] In some embodiments, the preparation method further comprises:

[0025] Through metal thin film deposition technology and stripping technology, other electronic components and the superconducting transistor device can be integrated on-chip to build more complex on-chip functional devices.

[0026] In a third aspect, the present application proposes a superconducting logic gate device, which uses the above-mentioned superconducting transistor device to realize single-input and dual-input logic gate functions.

[0027] In some embodiments, the superconducting logic gate device can implement logic gate functions including: OR gate, NOR gate, AND gate, NAND gate, and NOT gate.

[0028] The present application proposes a superconducting transistor device and a method for preparing the same. A superconducting transistor device with logic functions is obtained by constructing superconducting nanowires and gates, which simplifies the structure of superconducting logic circuits, improves the integration and scalability of the device, greatly reduces the difficulty of preparation and the requirements for magnetic shielding, and provides a new technical route for the development of superconducting integrated circuits.

[0029] A superconducting transistor device and a preparation method thereof proposed in this application use compatible materials and preparation processes, which facilitate the combination of superconducting logic gates with existing semiconductor processes, realize the coexistence of superconducting and semiconductor integrated circuits, and provide a new technical reference for the research of large-scale quantum measurement and control systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and do not constitute a limitation on the embodiments of the present application. In the drawings:

[0031] Figure 1 The plan view schematic diagram and circuit principle diagram of the dual-gate superconducting transistor device of the embodiment of the present application; wherein (a) is the plan view schematic diagram of the device; (b) is the circuit principle diagram of the device;

[0032] Figure 2 for Figure 1 The relationship between the critical current and the gate voltage of the double-gate superconducting transistor device shown;

[0033] Figure 3 Based on Figure 1The circuit schematic diagram and timing diagram of the dual-input or logic gate device implemented by the dual-gate superconducting transistor device shown in the figure; wherein (a) is the circuit schematic diagram of the device; (b) is the input and output timing diagram of the device;

[0034] Figure 4 The circuit schematic diagram and timing diagram of a single-input NOT gate device implemented based on a single-gate superconducting transistor device according to an embodiment of the present application; wherein (a) is a circuit schematic diagram of the device; (b) is an input-output timing diagram of the device;

[0035] Figure 5 The circuit schematic diagram and timing diagram of a dual-input AND gate device implemented based on a single-gate superconducting transistor device according to an embodiment of the present application; wherein (a) is a circuit schematic diagram of the device; (b) is an input and output timing diagram of the device;

[0036] Figure 6 It is a plan schematic diagram of the optimized dual-gate superconducting transistor device of the embodiment of the present application and a circuit schematic diagram of a dual-input AND gate device implemented based on it; wherein, (a) is a plan schematic diagram of the transistor device; (b) is a circuit schematic diagram of the AND gate device. DETAILED DESCRIPTION

[0037] Hereinafter, the term "include" or "may include" used in various embodiments of the present application indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items.

[0038] In various embodiments of the present application, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the words listed at the same time. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0039] The expressions (such as "first", "second", etc.) used in the various embodiments of the present application may modify the various constituent elements in the various embodiments, but may not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used for the purpose of distinguishing one element from other elements. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, without departing from the scope of the various embodiments of the present application, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0040] It should be noted that if it is described that one component element is “connected” to another component element, the first component element may be directly connected to the second component element, and a third component element may be “connected” between the first component element and the second component element. Conversely, when one component element is “directly connected” to another component element, it can be understood that there is no third component element between the first component element and the second component element.

[0041] The terms used in the various embodiments of the application are only used to describe the purpose of specific embodiments and are not intended to limit the various embodiments of the application. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as the meanings commonly understood by ordinary technicians in the field of the various embodiments of the application. The terms (such as the terms defined in the dictionary generally used) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the application.

[0042] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with examples and drawings. The illustrative implementation scheme of the present application and its description are only used to explain the present application and are not intended to limit the present application.

[0043] Embodiment 1:

[0044] At present, the realization of superconducting integrated circuits is mainly based on superconducting digital integrated circuits based on Josephson junctions. However, the device structure of this integrated circuit is complex, the preparation process is difficult, and strict magnetic shielding conditions are required, which greatly limits the scalability. In view of this, this embodiment proposes a superconducting transistor device. This embodiment obtains a superconducting transistor device with logic functions by constructing superconducting nanowires and gates, simplifies the structure of superconducting logic circuits, improves the integration of devices, greatly reduces the difficulty of preparation and the requirements for magnetic shielding, has good environmental stability and scalability, and provides a new technical route for the development of superconducting integrated circuits.

[0045] The superconducting transistor device proposed in this embodiment includes: a first gate and / or a second gate, a superconducting nanowire, a first electrode, and a second electrode.

[0046] The first gate and the second gate are respectively located on both sides of the superconducting nanowire, or the first gate or the second gate is located on the side of the superconducting nanowire. The first gate and / or the second gate are used to control the superconducting performance of the superconducting nanowire. When the gate voltage of the first gate and / or the second gate is greater than or equal to a certain voltage value, the superconducting nanowire loses its superconductivity, that is, it is in an off state, otherwise, the superconducting nanowire is in an on state.

[0047] Two ends of the superconducting nanowire are respectively connected to the first electrode and the second electrode, that is, the two ends of the superconducting nanowire are respectively led out through the first electrode and the second electrode.

[0048] The first gate and / or the second gate, the first electrode and the second electrode are all connected to the external electrode Pad.

[0049] The superconducting transistor device proposed in this embodiment is directly constructed by superconducting nanowires. With superconducting nanowires as the core of the device and combined with gate control, basic logic functions can be realized, which simplifies the structure of the superconducting logic circuit, improves the integration of the device, greatly reduces the difficulty of preparation and the requirements for magnetic shielding, and has good scalability, providing a new technical route for the development of superconducting integrated circuits.

[0050] Furthermore, the superconducting transistor device proposed in this embodiment has basically the same threshold voltage and regulation trend when the single gate is grounded or the double gate is grounded, and the superconducting transistor device loses superconductivity when the gate voltage is greater than or equal to a certain voltage value.

[0051] Furthermore, the first gate and the second gate have the same shape, and the first gate and the second gate can be symmetrically arranged on both sides of the superconducting nanowire, and the first gate and the second gate have the same spacing from the superconducting nanowire.

[0052] Furthermore, the first gate and / or the second gate may have a rectangular or pointed shape at one end close to the superconducting nanowire. The spacing between the first gate and / or the second gate and the superconducting nanowire is 10 nm to 200 nm.

[0053] Furthermore, the first gate and / or the second gate can be directly obtained from a thin film material, or obtained by depositing and stripping a metal thin film material, so as to meet different performance requirements.

[0054] Furthermore, the width of the superconducting nanowire is 30nm to 200nm, the length of the superconducting nanowire is 0.05μm to 20μm, and the thickness of the superconducting nanowire is 4nm to 50nm.

[0055] Furthermore, the superconducting nanowires can be prepared by using superconducting thin film materials such as NbTiN, NbN, MoRe, YBCO or BSCCO.

[0056] Furthermore, superconducting nanowires can use a structure of two nanowires in parallel to realize complex logic functions. The first gate is used to control the superconducting performance of one nanowire in the structure of two nanowires in parallel, and the second gate is used to control the superconducting performance of the other nanowire in the structure of two nanowires in parallel. At this time, the total bias current of the device should be less than the sum of the critical currents of the two nanowires, and the uniformity of the two nanowires should be ensured as much as possible to ensure that the critical currents of the two nanowires are consistent or close, and the two nanowires have sufficient spacing to avoid mutual interference, that is, the spacing between the two nanowires should meet the anti-interference distance. This embodiment uses a nanowire parallel structure to construct a more complex superconducting integrated circuit, realize a variety of logic functions, and increase the scope of application. At the same time, it can also optimize the logic gate and improve performance.

[0057] Furthermore, the superconducting transistor device proposed in this embodiment also includes:

[0058] Electronic components, such as resistors, are used to realize more (more complex) logic functions in conjunction with the superconducting nanowires, the first electrode and the second electrode.

[0059] The superconducting transistor device proposed in this embodiment can also be integrated with other electronic components to facilitate the construction of more complex superconducting integrated circuits, realize more logical functions, and have strong scalability.

[0060] Furthermore, this embodiment also proposes a method for preparing the above-mentioned superconducting transistor device, and the specific process is as follows:

[0061] Step 1, growing a silicon dioxide oxide layer on the surface of a silicon wafer, and obtaining a smooth silicon dioxide oxide layer surface through a polishing process;

[0062] Step 2, depositing a superconducting thin film on the silicon dioxide oxide layer;

[0063] Step 3, obtaining the first gate and / or the second gate and the pattern of the superconducting nanowire by exposure (such as electron beam exposure technology), and obtaining the superconducting nanowire regional structure by etching (such as reactive ion etching technology);

[0064] Step 4: obtaining electrode patterns of the first gate and / or the second gate, the first electrode and the second electrode by exposure (such as ultraviolet exposure technology), and obtaining the structure of the electrode region by etching.

[0065] Step 5: Finally, discrete devices are obtained by dicing, and the devices are packaged and tested.

[0066] The preparation method proposed in this embodiment helps to reduce the leakage current of the gate through the substrate and reduce the influence of the electrothermal effect by setting a silicon dioxide oxide layer and performing a polishing process. The preparation process proposed in this embodiment is simple, and at the same time, superconductivity is combined with existing semiconductor processes to achieve the coexistence of superconductivity and semiconductor integrated circuits, providing a new technical reference for the realization of large-scale quantum measurement and control systems.

[0067] Furthermore, the preparation method proposed in this embodiment also includes:

[0068] Through metal thin film deposition technology and lift-off technology, other electronic components (such as resistors, etc.) and superconducting transistor devices can be integrated on-chip to build more complex on-chip functional devices.

[0069] Furthermore, this embodiment also proposes a superconducting logic gate device, which uses the above-mentioned superconducting transistor device to realize single-input and dual-input logic gate functions. After the superconducting transistor device is connected to an external power supply (such as a constant current source), an external signal, and a ground, various basic logic functions can be realized, including but not limited to: OR gate, NOR gate, AND gate, NAND gate, NOT gate, etc.

[0070] Furthermore, the superconducting nanowire adopts a structural design of two nanowires connected in parallel to obtain an optimized superconducting AND gate, and the first gate and the second gate respectively control one of the two nanowires in parallel.

[0071] This embodiment constructs a logic gate circuit through superconducting transistor devices, uses a gate electric field to regulate the superconductivity of superconducting nanowires, realizes logic operation functions, simplifies the structure of superconducting logic circuits, reduces manufacturing costs, and provides a new approach for the research of superconducting integrated circuits and quantum measurement and control systems.

[0072] Embodiment 2:

[0073] This embodiment exemplarily illustrates the dual-gate superconducting transistor device and its manufacturing method and dual-input logic application proposed in the above-mentioned embodiment 1.

[0074] Specific as Figure 1 As shown in (a), the dual-gate superconducting transistor device of this embodiment mainly includes: a first gate G1, a second gate G2, a superconducting nanowire NW, a first electrode P1 and a second electrode P2. The first gate G1 and the second gate G2 are respectively located on both sides of the superconducting nanowire NW. The two ends of the superconducting nanowire NW are respectively led out through the first electrode P1 and the second electrode P2. The first gate G1 and the second gate G2 are in a rectangular configuration at one end close to the superconducting nanowire NW.

[0075] The dual-gate superconducting transistor device of this embodiment can be prepared according to the following steps:

[0076] Step 1, growing a silicon dioxide oxide layer on the surface of the silicon wafer by a thermal oxidation process; and obtaining a flat and uniform silicon dioxide oxide layer surface by a mechanical polishing process, and controlling the thickness of the silicon dioxide oxide layer to be 100 nm;

[0077] Step 2, depositing a superconducting film on the silicon dioxide oxide layer, wherein the material of the superconducting film is NbTiN and the thickness is 10 nm;

[0078] Step 3, obtaining the patterns of the first gate G1, the second gate G2 and the superconducting nanowire NW by electron beam exposure, and obtaining the main structure of the device (i.e., the structure of the superconducting nanowire region) by reactive ion etching, wherein the width of the superconducting nanowire NW is 100 nm and the length is 5 μm, and the shapes of the first gate G1 and the second gate G2 close to the superconducting nanowire are rectangular, and the distance between the first gate G1 and the second gate G2 and the superconducting nanowire NW is 60 nm;

[0079] Step 4, obtaining an electrode pattern including the first electrode P1, the second electrode P2, the first gate G1 and the second gate G2 by ultraviolet exposure technology; and obtaining a structure of the electrode region by reactive ion etching technology;

[0080] Step 5, obtain discrete devices through dicing, package the devices, and test them.

[0081] This embodiment uses constant current bias to test the device. Figure 1 As shown in (b), the dotted box is the schematic diagram of the device; the dual-gate superconducting transistor device has basically the same threshold voltage and regulation trend when the single gate is grounded or the dual gate is grounded. The device loses superconductivity at a larger gate voltage, such as Figure 2 As shown, when the gate voltage reaches 1, the superconducting nanowire is in the off state, and when the gate voltage reaches 0, the superconducting nanowire is in the on state.

[0082] The dual-gate superconducting transistor device prepared above was electrically tested in a low-temperature environment, and the logic function of a dual-input OR gate can be realized. The specific principle and timing diagram are shown in Figure 2. Figure 3 As shown in (a) and (b). The input terminal A and the input terminal B are connected to the first gate G1 and the second gate G2 respectively, and the first electrode P1 is connected to the constant current source I b The second electrode P2 is connected to the ground voltage GND, and an extension line is led out through the first electrode P1 as an output terminal Y. When at least one of the input terminals A and B is input with a high level signal, the output terminal Y outputs a high level signal (that is, when at least one of the input terminals A and B is 1, at this time, according to Figure 2 The characteristics of the superconducting nanowire shown in FIG. 1 show that the superconducting nanowire is in the off state, so that the output terminal Y is connected to the constant current source and outputs a high level signal), otherwise it outputs a low level signal (that is, when the input terminal A and the output terminal are both 0, at this time according to Figure 2 From the characteristics of the superconducting nanowire shown, it can be seen that the superconducting nanowire is in a conducting state, so that the output terminal Y is grounded and a low-level signal is output), realizing the logic function of the OR gate.

[0083] Embodiment 3:

[0084] This embodiment exemplarily illustrates the single-gate superconducting transistor device and its preparation method and single-input logic application proposed in the above-mentioned embodiment 1.

[0085] The single-gate superconducting transistor device of this embodiment mainly includes: a first gate G1, a superconducting nanowire NW, a series resistor R s , a first electrode P1 and a second electrode P2. The first gate G1 is located on the side of the superconducting nanowire NW, and the two ends of the superconducting nanowire NW are connected through the first electrode P1, the series resistor R s And the second electrode P2 is led out.

[0086] The single-gate superconducting transistor device of this embodiment can be prepared according to the following steps:

[0087] Step 1-step 2 are the same as step 1-step 2 in the above embodiment 2;

[0088] Step 3 is the same as step 3 in the above embodiment 2, except that there is only a single gate in the superconducting nanowire region;

[0089] Step 4: Obtain the series resistance R by electron beam exposure s and patterns of electrodes (electrodes including a first grid electrode, a first electrode, and a second electrode) and extended lines;

[0090] Step 5, depositing a Ti metal film by magnetron sputtering;

[0091] Step 6: Get the series resistor R by stripping process s and electrodes and extension cords;

[0092] Step 7 is the same as step 5 in the above embodiment 2.

[0093] The single-gate superconducting transistor device prepared above was electrically tested in a low-temperature environment, and the logic function of a single-input NOT gate can be realized. The specific principle and timing diagram are shown in the figure. Figure 4 As shown in (a) and (b). The input terminal A is connected to the first gate G1, and the first electrode P1 is connected to the constant current source I b Connect, series resistor R s The second electrode P2 is connected to the ground voltage GND, and a series resistor R s The non-ground electrode is extended as the output terminal Y. When the input terminal A is a high-level signal input, the output terminal Y outputs a low-level signal, otherwise it outputs a high-level signal to realize the logical function of the NOT gate.

[0094] Embodiment 4:

[0095] This embodiment exemplifies the single-gate superconducting transistor device and its preparation method and dual-input logic application proposed in the above-mentioned embodiment 1.

[0096] The single-gate superconducting transistor device of this embodiment mainly includes: a first gate G1, a superconducting nanowire NW, a series resistor R s , a first electrode P1 and a second electrode P2. The first gate G1 is located on the side of the superconducting nanowire NW, and the two ends of the superconducting nanowire NW are connected through the first electrode P1 and the series resistor R s , and the second electrode P2 is led out.

[0097] The single-gate superconducting transistor device of this embodiment can be prepared according to the following steps:

[0098] Step 1 to step 3 are the same as steps 1 to step 3 in the above embodiment 3;

[0099] Step 4 to step 6 are the same as steps 4 to step 6 in the above embodiment 3, but in this embodiment, the patterns of the series resistor and its electrodes and the extension wire are different;

[0100] Step 7 is the same as step 7 in the above embodiment 3.

[0101] The single-gate superconducting transistor device prepared above was electrically tested in a low-temperature environment, and the logic function of a dual-input AND gate can be realized. The specific principle and timing diagram are shown in Figure 2. Figure 5 As shown in (a) and (b). The input terminal A is connected to the sIt is connected to the first electrode P1, the input terminal B is connected to the first gate G1, the second electrode P2 is connected to the ground voltage GND, and the first electrode P1 leads to an extended line as the output terminal Y. When both the input terminal A and the output terminal B are high-level signal inputs, the output terminal Y outputs a high-level signal, otherwise it outputs a low-level signal, thereby realizing the logical function of the AND gate.

[0102] Embodiment 5:

[0103] This embodiment exemplifies the optimized dual-gate superconducting transistor device and its preparation method and dual-input logic application proposed in the above-mentioned embodiment 1.

[0104] Specific as Figure 6 As shown in (a), the optimized dual-gate superconducting transistor device of this embodiment mainly includes: a first gate G1, a second gate G2, a superconducting nanowire NW, a first electrode P1 and a second electrode P2. Among them, the first gate G1 and the second gate G2 are respectively located on both sides of the superconducting nanowire NW. The two ends of the superconducting nanowire NW are respectively led out through the first electrode P1 and the second electrode P2. The superconducting nanowire NW is a structure of two nanowires connected in parallel, and the first gate G1 and the second gate G2 respectively control one of the nanowires, and the two nanowires have the same design width and basically the same critical current.

[0105] The optimized dual-gate superconducting transistor device of this embodiment can be prepared according to the following steps:

[0106] Step 1-step 2 are the same as step 1-step 2 in the above embodiment 2;

[0107] Step 3 is the same as step 3 in the above embodiment 2, but in this embodiment, the pattern of the superconducting nanowire NW is a structure of two nanowires connected in parallel;

[0108] Step 4-Step 5 are the same as Step 4-Step 5 in the above-mentioned Example 2.

[0109] The optimized dual-gate superconducting transistor device prepared above is electrically tested in a low-temperature environment, and the logical function of the AND gate can be realized. The specific principle is as follows Figure 6 As shown in (b), the input terminal A and the input terminal B are connected to the first gate G1 and the second gate G2 respectively, and the first electrode P1 is connected to the constant current source I b connected, and the device is working b The second electrode P2 is connected to the ground voltage GND, and the first electrode P1 leads to an extension line as the output terminal Y. When both the input terminal A and the input terminal B are high-level signal inputs, the output terminal Y outputs a high-level signal (that is, when both the input terminal A and the output terminal B are 1, at this time, according to Figure 2The characteristics of the superconducting nanowires shown in FIG. 1 show that both nanowires are in the off state, so that the output terminal Y is connected to a constant current source and outputs a high level signal), otherwise a low level signal is output (that is, when at least one of the input terminal A and the output terminal B is 0, at this time according to Figure 2 From the characteristics of the superconducting nanowires shown, it can be seen that at least one nanowire in the parallel structure is in a conducting state, so that the output terminal Y is grounded and a low-level signal is output), realizing the logical function of the AND gate.

[0110] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A superconducting transistor device, characterized in that: include: A first gate and / or a second gate, a superconducting nanowire, a first electrode, and a second electrode; Wherein, the first gate and the second gate are respectively located on both sides of the superconducting nanowire, or the first gate or the second gate is located on the side of the superconducting nanowire; Two ends of the superconducting nanowire are connected to the first electrode and the second electrode respectively; The first gate and / or the second gate, the first electrode and the second electrode are all used to connect to an external electrode.

2. A superconducting transistor device according to claim 1, characterized in that: The first gate and the second gate have the same shape, and are symmetrically distributed on both sides of the superconducting nanowire.

3. A superconducting transistor device according to claim 1, characterized in that: The first gate and / or the second gate is / are close to one end of the superconducting nanowire and is / are in a rectangular configuration or a pointed configuration; The first gate and / or the second gate are obtained from thin film materials or are obtained by stripping off metal thin film deposition.

4. A superconducting transistor device according to claim 1, characterized in that: The material of the superconducting nanowire is NbTiN, NbN, MoRe, YBCO or BSCCO.

5. A superconducting transistor device according to claim 1, characterized in that: The superconducting nanowire adopts a structure of two nanowires connected in parallel, and the first gate and the second gate respectively control one of the two nanowires in the structure of parallel connection.

6. A superconducting transistor device according to claim 5, characterized in that: The two nanowires have the same width and substantially the same critical current, and the spacing between the two nanowires should satisfy the anti-interference distance.

7. A superconducting transistor device according to claim 1, characterized in that: Also includes: An electronic component is used to realize more logic functions in combination with a superconducting nanowire, a first electrode and a second electrode.

8. A superconducting transistor device according to any one of claims 1 to 7, characterized in that: The superconducting transistor device has a substantially consistent threshold voltage and regulation trend when a single gate is grounded or a double gate is grounded, and the superconducting transistor device loses superconductivity when the gate voltage is greater than or equal to a certain voltage value.

9. A method for preparing a superconducting transistor device according to any one of claims 1 to 8, characterized in that: include: Growing a silicon dioxide oxide layer on the surface of the silicon wafer and polishing the silicon dioxide oxide layer; Depositing a superconducting thin film on the polished silicon dioxide oxide layer; The pattern of the first gate and / or the second gate and the superconducting nanowire is obtained by exposure, and the superconducting nanowire regional structure is obtained by etching; Obtaining electrode patterns of the first gate and / or the second gate, the first electrode and the second electrode by exposure, and obtaining an electrode region structure by etching; The superconducting transistor device is obtained by packaging.

10. The preparation method according to claim 9, characterized in that: Also includes: Through metal thin film deposition technology and stripping technology, other electronic components and the superconducting transistor device can be integrated on-chip to build more complex on-chip functional devices.

11. A superconducting logic gate device, characterized in that: The superconducting transistor device according to any one of claims 1 to 8 is used to realize single-input and dual-input logic gate functions.

12. A superconducting logic gate device according to claim 11, characterized in that: The logic gate functions that can be realized by the superconducting logic gate device include: OR gate, NOR gate, AND gate, NAND gate, and NOT gate.

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