Burst mode clock data recovery circuit and method with adaptive bandwidth capability
By adaptively adjusting the CDR gain and introducing the metastable state detection algorithm of the Bang-Bang phase detector, the frequency offset tracking capability of the BM-CDR is improved, achieving fast locking and low jitter for high-speed data transmission.
CN120729431APending Publication Date: 2025-09-30NAT UNIV OF DEFENSE TECH
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Patent Information
- Application Number
- CN202510878373.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-30
AI Technical Summary
Technical Problem
Traditional BM-CDR has insufficient tracking capability when facing frequency offset, resulting in prolonged locking time and failure to meet the demand for increased data transmission rate.
Method used
A burst mode clock data recovery circuit with adaptive bandwidth capability is used to improve CDR performance by adaptively adjusting the gains of the proportional and integral paths in the CDR and combining it with the metastable state detection algorithm of the Bang-Bang phase detector.
Benefits of technology
With a frequency offset of 100ppm, the locking time is shortened to 6.4ns, meeting the requirements of high-speed data transmission and reducing post-lock jitter.
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Abstract
The invention discloses a burst mode clock data recovery circuit with self-adaptive bandwidth capability, which is applied to an optical link, an input optical signal is converted into an electric signal, the electric signal is input into an analog front end to be processed to obtain digital input, and a data path adopts a quarter architecture to sample the digital input to obtain edge information and data information, namely a digital signal; the burst mode clock data recovery module comprises a phase discriminator, a voting device, a second-order loop filter and a self-adaptive bandwidth control algorithm; the phase discriminator receives the edge information and the data information and outputs multiple groups of parallel phase discrimination results, and the voting device receives and processes the phase discrimination results and dynamically adjusts the output proportion and integral gain according to a self-adaptive bandwidth control algorithm; the second-order loop filter outputs a phase control code according to the proportion and the integral gain; the clock path generates an eight-phase clock signal according to the phase control code for sampling control of the data path. According to the method, the locking time is 6.4 ns under the conditions that the data rate is 40Gb / s and the frequency deviation is 100ppm.
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