Gaas solar cell back surface photon structure based on recycled silicon wafer template and preparation method

Abstract

The application belongs to the technical field of solar cells, and discloses a GaAs solar cell back surface photon structure based on a regenerated silicon wafer template and a preparation method. The method comprises the following steps: 1) the regenerated silicon wafer is subjected to ozone oxidation treatment; an oxide layer is formed on the micron-level rough surface of the regenerated silicon wafer; 2) the treated silicon wafer is inclined, and then subjected to geometric constraint etching, so that a periodic gradually changing Bragg reflection nanometer grating is generated on the micron-level rough surface of the silicon wafer; 3) the micron-level rough surface and the nanometer grating structure of the silicon wafer are transferred to the back surface of a GaAs substrate, and gas etching is performed, so that micron scattering pits are formed on the back surface of the GaAs substrate; and 4) a back electrode is prepared on the back surface of the GaAs substrate with the micron scattering pits, and a positive electrode is prepared on the front surface of the GaAs cell. The method is simple, reduces the energy consumption for preparing the template, realizes atomic-level conformal combination of the Bragg reflection array and the micron scattering base, and the obtained photon reflection structure has high efficiency and low optical loss.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology and relates to a photonic structure on the back surface of a GaAs solar cell based on a regenerated silicon wafer template and its preparation method. Background Technology

[0002] Current GaAs solar cells primarily employ single-scale gratings or random textured surfaces for their photonic back reflection structures, making it difficult to simultaneously achieve synergistic control of broad-spectrum scattering and specific wavelength reflection. Traditional nanoimprint lithography relies on high-precision silicon templates for electron beam lithography, but its periodic structures are limited by artificial design and the fabrication process is complex, resulting in theoretical limits to optical response bandwidth and reflection efficiency. Especially for multi-junction cell systems, the back reflection structure needs to achieve broad-area light scattering at the micrometer scale to extend the optical path, while simultaneously precisely matching the absorption edge wavelengths of each sub-cell through nanoscale Bragg reflection. This places stringent requirements on the spatial arrangement and geometric parameters of the cross-scale structure.

[0003] In existing technologies, the combination of micron-textured surfaces and nanostructures often employs step-by-step photolithography or stacking processes, which suffer from drawbacks such as large alignment deviations (>200nm) in heterostructures and high interfacial recombination losses. Furthermore, etching processes based on the textured surface (random pyramid structure) of ordinary silicon wafers struggle to guide the directional self-assembly of nanostructures due to the disordered distribution of substrate curvature, resulting in broadened Bragg reflection peaks (FWHM > 50nm) and severely weakened wavelength selectivity. In addition, traditional processes require mirror polishing of the silicon substrate to eliminate textured surface interference, which not only increases energy consumption but also destroys the guiding effect of the natural curvature gradient on the self-alignment of nanostructures.

[0004] This invention utilizes the gradient textured surface structure (a composite morphology of pyramidal substrate and submicron protrusions) formed on retired silicon wafers during long-term service as a geometric constraint template for self-aligned etching. Through the synergistic control of ozone gradient oxidation and plasma incident angle, periodically varying nanogratings are etched in different curvature regions of the micron-textured surface, achieving an atomically conformal integration of the Bragg reflector array and the micron-scattering substrate. This cross-scale structure breaks through the physical limits of traditional single-level optical design, simultaneously achieving full-band scattering enhancement and narrow-band reflection phase matching without the need for precision photolithography, paving the way for high-efficiency, low-optical-loss back reflection designs. Simultaneously, this method reduces the processing cost of high-purity templates by utilizing the resource-based morphology of retired silicon wafers, offering the dual advantages of improved technical performance and simplified processes. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention aims to provide a GaAs solar cell photonic back-reflection structure (i.e., a back-surface photonic structure) based on a reclaimed silicon wafer template and its fabrication method. This invention solves the problems of limited optical control dimensions and high fabrication costs associated with GaAs solar cell photonic back-reflection structures. This invention utilizes a retired silicon wafer (a composite morphology of pyramids and submicron protrusions) as a geometrically constrained template for self-aligned etching. Through the synergistic control of ozone gradient oxidation and plasma incident angle, periodically varying nanogratings are directionally etched in different curvature regions of a micron-textured surface, achieving an atomically conformal integration of the Bragg reflector array and the micron-scattering substrate. The photonic reflection structure obtained by the method of this invention exhibits high efficiency and low optical loss.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A method for fabricating a GaAs solar cell photonic back reflection structure (i.e., back surface photonic structure) based on a regenerated silicon wafer template includes the following steps:

[0008] 1) The recycled silicon wafer is treated with ozone oxidation to form a thickness difference oxide layer on the top and slope of the micron-scale textured surface of the recycled silicon wafer; the micron-scale textured surface is composed of micron-scale pyramids and protrusions on the slope of the pyramids or is composed of the base of the micron-scale pyramids and submicron-scale protrusions (protrusions formed by corrosion of the pyramid tip);

[0009] 2) The treated silicon wafer is tilted and placed in the plasma chamber, and then geometrically constrained etching is performed to generate a periodically gradient Bragg reflection nanograting on the micron-scale textured surface of the silicon wafer.

[0010] 3) The micron-scale textured surface and nano-grating structure of the silicon wafer are transferred onto the back side of the GaAs substrate of the GaAs cell, and gas etching is performed to form micron-scale scattering pits on the back side of the GaAs substrate; the surface of the micron-scale scattering pits has a periodically graded Bragg reflection nano-grating structure; the micron-scale scattering pits coincide with or are similar to the micron-scale textured surface and nano-grating structure of the silicon wafer.

[0011] 4) A back electrode is fabricated on the back side of a GaAs substrate with micron-sized scattering pits, and a positive electrode is fabricated on the front side of the GaAs cell.

[0012] The period of the nanograting in step 2) is

[0013] 150 is the base period. Angle factor;

[0014] The etching depth of the nanograting is

[0015] D(R,θ)=120·R 0.7·(0.9+0.02·θ); 0.9+0.02·θ is the angle correction term.

[0016] D: Etching depth (nm) of the columnar nanostructure (nanograting);

[0017] R: Local radius of curvature; for example, the radius of curvature from the top to the bottom of a pyramid changes from 1.25 μm to 3 μm;

[0018] θ: Plasma incident angle (°) (i.e., the angle at which the silicon wafer is tilted);

[0019] P: Nanostructure period (nm) (i.e., the period of the nanograting).

[0020] The plasma incident angle is 45° or 60°.

[0021] Different curvature regions (pyramid slope, top) exhibit etching rate gradients due to local incident angle differences, leading to the self-assembly of periodically varied structures. The range of these periodic gradients is determined by both the tilt angle and the surface curvature. The curvature gradient determines the local plasma flux density; the high curvature region (top) exhibits concentrated ion flux and a rapid etching rate.

[0022] The recycled silicon wafer described in step 1) is treated with potassium hydroxide solution to retain its micron-scale texture before undergoing ozone oxidation.

[0023] The concentration of KOH solution is 5-15 wt%. Conditions for potassium hydroxide solution treatment: treat at 60-90℃ for 20-40 minutes.

[0024] The micron-scale textured surface of the regenerated silicon wafer is formed by treatment with potassium hydroxide solution, and its roughness Ra = 1-2 μm.

[0025] The surface of retired silicon wafers has a micron-level textured surface. After treatment with potassium hydroxide solution, its roughness Ra = 1-2 μm is formed, which consists of micron-level pyramids and protrusions on the pyramid slopes, or micron-level pyramid bases and micron-level protrusions (protrusions formed by corrosion at the pyramid tip).

[0026] The height of the pyramids or the base of the pyramids is 2-6 μm, while the height of the protrusions on the slopes of the pyramids or the protrusions formed by corrosion at the top of the pyramids is 0.5-1 μm.

[0027] Preferably, the potassium hydroxide solution treatment refers to treating the surface with 8-12 wt% KOH at 75-85°C for 25-35 minutes, resulting in a surface roughness Ra of 1.5 ± 0.3 μm and an increase in submicron protrusion density to 10. 4 -10 5 / cm 2 Wide-angle scattering efficiency is improved by 20%.

[0028] During the ozone oxidation treatment in step 1), due to the micron-scale texture of the regenerated silicon wafer, an oxide layer with a thickness difference is automatically formed on the top of the textured surface and the slope.

[0029] The etching described in step 2) refers to geometrically constrained etching using a Cl2 / BCl3 mixed gas.

[0030] The periodically gradient Bragg reflection nanograting refers to a nanograting with a periodically gradient formed at the top, slope and / or bottom of each pyramid.

[0031] Step 3) involves the following steps: A UV-curable adhesive containing nano-SiO2 particles is spin-coated onto the back of the GaAs substrate of the GaAs cell. Pressure imprinting combined with nitrogen-assisted UV curing is used to transfer the micron-scale textured surface and nano-grating structure of the silicon wafer into a porous colloidal mask. Using the colloidal mask as a protective layer, the GaAs substrate is etched with a Cl2 / BCl3 mixed gas. After removing the adhesive layer, micron-scale scattering pits are simultaneously formed on the GaAs substrate. The surface of the micron-scale scattering pits has a periodically gradient Bragg reflection nano-grating structure. The micron-scale scattering pits overlap with or are similar to the micron-scale textured surface and nano-grating structure of the silicon wafer.

[0032] In step 4), an epitaxial layer is prepared on the front side of the GaAs substrate, and then a transparent conductive electrode is prepared on the epitaxial layer as the positive electrode, thereby completing the battery integration.

[0033] In step 2), the grating structure is optimized to achieve a Bragg reflection wavelength (800-1200nm) and a reflectivity >95%.

[0034] In step 3), the imprinting pressure is 5-10 MPa, and the UV curing energy is 1000-1500 mJ / cm². 2 The UV-curable adhesive contains 1-5 wt% nano-SiO2 particles (20-100 nm in diameter) and has a spin-coating thickness of 1.5-2.5 μm.

[0035] Imprint pressure gradient control: 10MPa at the center → 7MPa at the edge, deviation <0.3MPa, demolding integrity rate >99.5%.

[0036] In step 3), the volume ratio of Cl2 to BCl2 is 3:1 to 5:1, and the etching selectivity ratio (GaAs:colloid) is >50:1 (this ratio is the etching rate ratio (etching rate of GaAs material:colloid mask >50:1)).

[0037] In step 3), the depth of the micron-scattering pit is 2-6 μm.

[0038] This invention uses laser interference to monitor the etching depth in real time. Etching is terminated when the micron-sized pits reach the required depth. The depth ratio between the micron-sized textured surface and the nano-periodic gradient grating structure is maintained at 10-30:1, resulting in a full-band reflectivity of >95%.

[0039] Preferably, in step 4), the back metal electrode is an Au / Ge / Ni alloy with a thickness of 100-200 nm, and the annealing conditions are 350-400℃ (N2 atmosphere, 8-12 minutes). This process forms a low-resistance ohmic contact with a series resistance <0.5 Ω·cm. 2 Ni is deposited first in the back electrode, followed by AuGe, which is an alloy.

[0040] The front electrode adopts a Ti, Pd and / or Ag gate structure; or a Ti / Pd / Ag gate line structure with a line width of <10μm and a spacing of 1-2mm.

[0041] The deviation between the grating period formed by etching in step 4) and the grating period of the silicon template in step 2) is ≤10%. The depth ratio (GaAs:silicon) is 1.1-1.5:1 (i.e., the ratio of pit depth to the height of the pyramid on the silicon wafer).

[0042] Compared with the prior art, the advantages of the present invention are as follows:

[0043] (1) Optimization of light management performance: The wide-angle scattering (divergence angle > 110°) of the micron-scale textured surface and the narrow-band high reflectivity (reflectivity at 900nm > 96%) of the periodically graded nano-Bragg grating work together to increase the average reflectivity in the 800-1200nm band to 95%-96%, which is 20%-25% higher than that of the traditional single-level structure.

[0044] (2) Low-cost self-aligned process: This invention utilizes the geometric constraint effect of the micron structure on the surface of retired silicon wafers to eliminate the need for traditional photolithography masks and electron beam exposure equipment, reducing process steps by more than 40% and reducing template preparation costs to 10%-15% of traditional methods;

[0045] (3) Efficient recycling of silicon resources: This invention directly uses the service morphology of retired silicon wafers as a template substrate, reducing the consumption of primary silicon materials and CO2 emissions, and realizing closed-loop resource utilization in the photovoltaic industry chain; Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of the GaAs multi-junction solar cell with a back surface photonic structure according to the present invention; 1-positive electrode, 2-multi-junction GaAs solar cell, 3-back surface photonic structure, 4-back electrode;

[0047] Figure 2 A schematic diagram of the photonic structure on the back surface of a GaAs substrate after etching.

[0048] Figure 3 A schematic diagram of the fabrication process of the back surface photonic structure of a GaAs solar cell;

[0049] Figure 4 The JV curves are for the solar cells of Example 1 and Comparative Example 1. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto. A schematic diagram of the structure of the GaAs multi-junction solar cell with a back surface photonic structure of the present invention is shown below. Figure 1 As shown, from bottom to top, it includes a back electrode 4, a multi-junction GaAs solar cell 2, and a positive electrode 1; the back of the GaAs substrate of the multi-junction GaAs solar cell is provided with a photonic structure 3, which is filled with the back electrode 4, and the thickness of the back electrode is greater than the depth of the photonic structure; the positive electrode is disposed at both ends of the multi-junction GaAs solar cell.

[0051] The photonic structure has a micron-scale textured surface and a periodically gradient Bragg reflection nanograting structure.

[0052] Figure 2 This is a schematic diagram of the photonic structure on the back surface of a GaAs substrate after etching. The photonic structure is an inverted pyramid shape with a periodically graded Bragg reflection nanograting structure on the sloping side and bottom. Figure 2 It is to combine the GaAs substrate and photonic structure according to Figure 1 The settings are reversed.

[0053] Figure 3 This is a schematic diagram of the fabrication process of the back surface photonic structure of a GaAs solar cell.

[0054] Example 1

[0055] A method for fabricating a photonic structure on the back surface of a GaAs solar cell includes the following steps:

[0056] Step 1: Clean the 6-inch decommissioned monocrystalline silicon wafer (500μm thickness) by ultrasonic treatment with acetone, ethanol and deionized water for 10 minutes each, and then dry it with a nitrogen gun.

[0057] Step 2: Etch with 10wt% KOH solution at 80℃ for 30 minutes to restore the micron-scale pyramid textured surface (Ra=1.3±0.2μm); in this embodiment, the height of the textured pyramid is 5μm, the height of the submicron protrusions is 0.5μm, and the density of the protrusions is 8×10⁻⁶. 4 ;

[0058] Step 3: Place the silicon wafer in an ozone treatment chamber (O2 concentration 50ppm, gas flow rate 30cm / s) for 8 minutes to form a 6±0.5nm oxide layer on the top of the textured surface, and the thickness gradient of the oxide layer on the sloped surface decreases to 2.5-4nm (i.e. a thickness gradient is formed from the top of the pyramid to the sloped surface).

[0059] Step 4: Tilting the silicon wafer at 45°, perform Cl2 / BCl3 (volume ratio 3:1) plasma etching to generate hexagonal close-packed columnar or grating array nanogratings with a period gradually changing in the range of 300-500nm (the etching depth of the nanogratings is 252-466nm).

[0060] Step 5: Spin-coat NOA81 UV adhesive (containing 3wt% 50nm SiO2 particles, 2μm thickness) onto the back of the purchased multi-junction GaAs solar cell substrate (GaAs substrate); use gradient pressure imprinting (10MPa at the center → 7MPa at the edge) and nitrogen-assisted curing (1200mJ / cm²). 2 The structure on the silicon wafer is transferred;

[0061] Step 6: Etch the GaAs substrate with Cl2 / BCl3 (4:1) to form micro-pits with a depth of 5.5 μm. The slope and bottom of the micro-pits have nano-gratings with a period gradually changing in the range of 300-510 nm, and finally obtain a composite back reflection structure. The micro-pits are inverted pyramid shape, and the micro-pits coincide with or are similar to the micro-scale textured surface on the silicon wafer.

[0062] Step 7: Using an electron beam evaporation system, deposit a 200nm Ag gate electrode; deposit an Au / Ge / Ni alloy back electrode (150nm thick) on the back side, and anneal at 400℃ for 10 minutes (N2 atmosphere).

[0063] The electrical performance of the multi-junction solar cell with a back-side photonic structure obtained in Example 1 was tested, and the results are as follows: Figure 4 As shown, the short-circuit current density of this device is 12.96 mA / cm². 2 The open-circuit voltage is 2.89V and the fill factor is 80.28.

[0064] Example 2:

[0065] The difference between this embodiment and embodiment 1 is that in step 4, the plasma incident angle is adjusted to 60° to generate a nanograting with a gradually changing perimeter in the range of 316-549nm and a depth of 295-544nm.

[0066] The reflectivity at a wavelength of 900nm was measured to be 97.5%, making it suitable for high-concentration photovoltaic systems.

[0067] Example 3:

[0068] This embodiment differs from Example 1 in that the KOH solution concentration used in step 2 is 12wt%, the treatment temperature is 90℃, the treatment time is 20min, and the roughness Ra = 1.5±0.2μm. Other steps and parameters are the same as in Example 1. In this embodiment, the height of the velvety pyramid is 5μm, the height of the submicron protrusions is 0.7μm, and the density of the protrusions is 9.6×10⁻⁶. 4 .

[0069] Comparative Example 1

[0070] A multi-junction gallium arsenide solar cell with an Ag gate electrode on the front and an Au / Ge / Ni alloy electrode on the back, but without a back-side photonic structure, is described. In other words, the difference between this comparative example and Example 1 is that the GaAs substrate lacks a photonic structure.

[0071] Performance testing:

[0072] The electrical performance of the solar cells obtained in Examples 1-3 and Comparative Example 1 was tested, and the results are shown in Table 1.

[0073] Table 1 shows the electrical performance of the solar cells obtained in Examples 1-3 and Comparative Example 1.

[0074]

[0075] As shown in Table 1, the solar cells obtained in Examples 1-3 have significantly higher back reflectivity (average reflectivity) and short-circuit current compared to the solar cell in Comparative Example 1, and the photoelectric conversion efficiency is improved by approximately 7-14%. This indicates that the fabricated back surface photonic structure significantly improves the utilization of incident photons, increases the short-circuit current of the device, and thus enhances the final conversion efficiency.

Claims

1. A method for fabricating a GaAs solar cell back surface photonic structure based on a regenerated silicon wafer template, characterized in that: Includes the following steps: 1) The recycled silicon wafer is treated with ozone oxidation to form a thickness difference oxide layer on the top and slope of the micron-scale textured surface of the recycled silicon wafer; the micron-scale textured surface is composed of micron-scale pyramids and protrusions on the pyramid slopes or is composed of the base of a micron-scale pyramid and submicron-scale protrusions; 2) The treated silicon wafer is tilted and placed in the plasma chamber, and then geometrically constrained etching is performed to generate a periodically gradient Bragg reflection nanograting on the micron-scale textured surface of the silicon wafer. The etching depth of the nanograting is ; 0.9 + 0.02·θ is the angle correction term; D: Etching depth of the nanograting, nm; R: Local radius of curvature, i.e., the radius of curvature from the top of the pyramid to the bottom of the pyramid; θ: Plasma incident angle, i.e., the angle at which the silicon wafer is tilted; 3) The micron-scale textured surface and nano-grating structure of the silicon wafer are transferred onto the back side of the GaAs substrate of the GaAs cell, and gas etching is performed to form micron-scale scattering pits on the back side of the GaAs substrate; the surface of the micron-scale scattering pits has a periodically graded Bragg reflection nano-grating structure; the micron-scale scattering pits coincide with or are similar to the micron-scale textured surface and nano-grating structure of the silicon wafer. 4) A back electrode is fabricated on the back side of a GaAs substrate with micron-sized scattering pits, and a positive electrode is fabricated on the front side of the GaAs cell.

2. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 1, characterized in that: The tilt angle of the silicon wafer is the plasma incident angle, which is 45° or 60°. The period of the nanograting in step 2) is 150 is the base period. Angle factor; P: The period of the nanostructure is the period of the nanograting, in nm.

3. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 1, characterized in that: The recycled silicon wafer described in step 1) is treated with potassium hydroxide solution to retain its micron-scale texture before undergoing ozone oxidation.

4. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 3, characterized in that: The concentration of the potassium hydroxide solution is 5-15 wt%; the conditions for potassium hydroxide solution treatment are: treatment at 60-90℃ for 20-40 minutes. The micron-scale textured surface of the regenerated silicon wafer is treated with potassium hydroxide solution, and its roughness Ra = 1-2 μm.

5. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 4, characterized in that: The potassium hydroxide solution treatment refers to treating the surface with an 8-12 wt% potassium hydroxide solution at 75-85℃ for 25-35 minutes, resulting in a surface roughness Ra of 1.5 ± 0.3 μm and an increase in submicron protrusion density to 10. 4 -10 5 / cm².

6. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 1, characterized in that: In step 1), the height of the pyramid or the base of the pyramid is 2-6 μm, and the height of the protrusions on the slope of the pyramid or the protrusions formed by the corrosion of the pyramid tip is 0.5-1 μm. The depth of the micron-scattering pit described in step 3) is 2-7 μm.

7. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 1, characterized in that: The etching described in step 2) refers to geometrically constrained etching using a Cl2 / BCl3 mixed gas. Step 3) involves the following steps: A UV-curable adhesive containing nano-SiO2 particles is spin-coated onto the back of the GaAs substrate of the GaAs cell. Pressure imprinting combined with nitrogen-assisted UV curing is used to transfer the micron-scale textured surface and nano-grating structure of the silicon wafer into a porous colloidal mask. Using the colloidal mask as a protective layer, the GaAs substrate is etched with a Cl2 / BCl3 mixed gas. After removing the adhesive layer, micron-scale scattering pits are simultaneously formed on the GaAs substrate. The surface of the micron-scale scattering pits has a periodically gradient Bragg reflection nano-grating structure. The micron-scale scattering pits overlap with or are similar to the micron-scale textured surface and nano-grating structure of the silicon wafer.

8. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 7, characterized in that: The imprinting pressure in step 3) is 5-10 MPa, the UV curing energy is 1000-1500 mJ / cm², the UV curing adhesive contains 1-5 wt% nano SiO2 particles with a diameter of 20-100 nm, and the spin coating thickness is 1.5-2.5 μm. The imprinting pressure gradient control is as follows: 10 MPa at the center to 7 MPa at the edge, with a deviation of <0.3 MPa. The volume ratio of Cl2 to BCl3 in step 3) is 3:1 to 5:

1.

9. The method for fabricating the back surface photonic structure of a GaAs solar cell based on a regenerated silicon wafer template according to claim 1, characterized in that: The ratio of the depth of the micron-sized scattering pit to the height of the pyramid on the silicon wafer in step 3) is 1.1-1.5:1; The back electrode mentioned in step 4) is an Au / Ge / Ni alloy with a thickness of 100-200 nm. The back electrode is annealed during preparation, and the annealing conditions are 350-400℃. The positive electrode adopts a Ti, Pd and / or Ag gate structure; In step 4), a back electrode is fabricated on the back side of the GaAs substrate with micron-sized scattering pits, an epitaxial layer is fabricated on the front side of the GaAs substrate, and then a positive electrode is fabricated on the epitaxial layer to complete the battery integration. The deviation between the grating period formed by etching in step 3) and the grating period of the silicon template in step 2) is ≤10%.

10. A GaAs solar cell back surface photonic structure based on a regenerated silicon wafer template, obtained by the preparation method according to any one of claims 1 to 9.

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